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From 5632874311dbf432c698fcbe0cf7a49e01ebf324 Mon Sep 17 00:00:00 2001
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Michal Suchanek |
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From: Christophe Lombard <clombard@linux.vnet.ibm.com>
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Michal Suchanek |
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Date: Fri, 8 Sep 2017 15:52:11 +0200
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Michal Suchanek |
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Subject: [PATCH] cxl: Add support for POWER9 DD2
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Michal Suchanek |
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References: bsc#1055014
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Patch-mainline: queued
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Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
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Git-commit: 5632874311dbf432c698fcbe0cf7a49e01ebf324
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The PSL initialization sequence has been updated to DD2.
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This patch adapts to the changes, retaining compatibility with DD1.
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The patch includes some changes to DD1 fix-ups as well.
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Tests performed on some of the old/new hardware.
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The function is_page_fault(), for POWER9, lists the Translation Checkout
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Responses where the page fault will be handled by copro_handle_mm_fault().
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This list is too restrictive and not necessary.
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This patches removes this restriction and all page faults, whatever the
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reason, will be handled. In this case, the interruption is always
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acknowledged.
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The following features will be added soon:
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- phb reset when switching to capi mode.
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- cxllib update to support new functions.
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Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
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Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
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Reviewed-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
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Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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Acked-by: Michal Suchanek <msuchanek@suse.de>
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---
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drivers/misc/cxl/cxl.h | 2 ++
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drivers/misc/cxl/fault.c | 15 ++-------------
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drivers/misc/cxl/pci.c | 47 ++++++++++++++++++++++++-----------------------
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3 files changed, 28 insertions(+), 36 deletions(-)
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diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
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index b1afeccbb97f..0167df81df62 100644
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--- a/drivers/misc/cxl/cxl.h
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+++ b/drivers/misc/cxl/cxl.h
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@@ -100,6 +100,8 @@ static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158};
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static const cxl_p1_reg_t CXL_XSL_DSNCTL = {0x0168};
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/* PSL registers - CAIA 2 */
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static const cxl_p1_reg_t CXL_PSL9_CONTROL = {0x0020};
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+static const cxl_p1_reg_t CXL_XSL9_INV = {0x0110};
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+static const cxl_p1_reg_t CXL_XSL9_DEF = {0x0140};
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static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};
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static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};
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static const cxl_p1_reg_t CXL_PSL9_FIR2 = {0x0308};
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diff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c
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index f17f72ea0545..70dbb6de102c 100644
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--- a/drivers/misc/cxl/fault.c
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+++ b/drivers/misc/cxl/fault.c
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@@ -220,22 +220,11 @@ static bool cxl_is_segment_miss(struct cxl_context *ctx, u64 dsisr)
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static bool cxl_is_page_fault(struct cxl_context *ctx, u64 dsisr)
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{
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- u64 crs; /* Translation Checkout Response Status */
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-
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if ((cxl_is_power8()) && (dsisr & CXL_PSL_DSISR_An_DM))
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return true;
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- if (cxl_is_power9()) {
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- crs = (dsisr & CXL_PSL9_DSISR_An_CO_MASK);
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- if ((crs == CXL_PSL9_DSISR_An_PF_SLR) ||
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- (crs == CXL_PSL9_DSISR_An_PF_RGC) ||
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- (crs == CXL_PSL9_DSISR_An_PF_RGP) ||
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- (crs == CXL_PSL9_DSISR_An_PF_HRH) ||
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- (crs == CXL_PSL9_DSISR_An_PF_STEG) ||
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- (crs == CXL_PSL9_DSISR_An_URTCH)) {
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- return true;
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- }
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- }
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+ if (cxl_is_power9())
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+ return true;
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return false;
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}
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diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
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index 3ba04f371380..b4ce9ea113a9 100644
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--- a/drivers/misc/cxl/pci.c
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+++ b/drivers/misc/cxl/pci.c
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@@ -401,7 +401,8 @@ int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
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*capp_unit_id = get_capp_unit_id(np, *phb_index);
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of_node_put(np);
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if (!*capp_unit_id) {
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- pr_err("cxl: invalid capp unit id\n");
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+ pr_err("cxl: invalid capp unit id (phb_index: %d)\n",
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+ *phb_index);
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return -ENODEV;
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}
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@@ -475,37 +476,37 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
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psl_fircntl |= 0x1ULL; /* ce_thresh */
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cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
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- /* vccredits=0x1 pcklat=0x4 */
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- cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0000000000001810ULL);
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-
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- /*
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- * For debugging with trace arrays.
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- * Configure RX trace 0 segmented mode.
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- * Configure CT trace 0 segmented mode.
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- * Configure LA0 trace 0 segmented mode.
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- * Configure LA1 trace 0 segmented mode.
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+ /* Setup the PSL to transmit packets on the PCIe before the
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+ * CAPP is enabled
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*/
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- cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000000ULL);
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- cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000003ULL);
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- cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000005ULL);
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- cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000006ULL);
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+ cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000002A10ULL);
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/*
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* A response to an ASB_Notify request is returned by the
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* system as an MMIO write to the address defined in
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- * the PSL_TNR_ADDR register
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+ * the PSL_TNR_ADDR register.
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+ * keep the Reset Value: 0x00020000E0000000
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*/
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- /* PSL_TNR_ADDR */
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- /* NORST */
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- cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
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+ /* Enable XSL rty limit */
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+ cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);
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+
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+ /* Change XSL_INV dummy read threshold */
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+ cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);
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+
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+ if (phb_index == 3) {
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+ /* disable machines 31-47 and 20-27 for DMA */
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+ cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);
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+ }
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- /* allocate the apc machines */
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- cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000003FFFF0000ULL);
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+ /* Snoop machines */
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+ cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);
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- /* Disable vc dd1 fix */
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- if (cxl_is_power9_dd1())
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- cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0400000000000001ULL);
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+ if (cxl_is_power9_dd1()) {
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+ /* Disabling deadlock counter CAR */
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+ cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);
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+ } else
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+ cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x4000000000000000ULL);
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return 0;
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}
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--
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2.10.2
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