From 8e8a31d7fd54d68fc9c6c1e69f52ccdaf43b01ea Mon Sep 17 00:00:00 2001

From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>

Date: Thu, 11 Oct 2018 11:03:02 +0530

Subject: [PATCH] powerpc: Use cpu_smallcore_sibling_mask at SMT level on

 bigcores

References: bsc#1109695

Patch-mainline: v4.20-rc1

Git-commit: 8e8a31d7fd54d68fc9c6c1e69f52ccdaf43b01ea

POWER9 SMT8 cores consist of two groups of threads, where threads in

each group shares L1-cache. The scheduler is not aware of this

distinction as the current sched-domain hierarchy has all the threads

of the core defined at the SMT domain.

	SMT  [Thread siblings of the SMT8 core]

	DIE  [CPUs in the same die]

	NUMA [All the CPUs in the system]

Due to this, we can observe run-to-run variance when we run a

multi-threaded benchmark bound to a single core based on how the

scheduler spreads the software threads across the two groups in the

core.

We fix this in this patch by defining each group of threads which

share L1-cache to be the SMT level. The group of threads in the SMT8

core is defined to be the CACHE level. The sched-domain hierarchy

after this patch will be :

	SMT	[Thread siblings in the core that share L1 cache]

	CACHE 	[Thread siblings that are in the SMT8 core]

	DIE  	[CPUs in the same die]

	NUMA 	[All the CPUs in the system]

Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

Acked-by: Michal Suchanek <msuchanek@suse.de>

---

 arch/powerpc/kernel/smp.c | 19 ++++++++++++++++++-

 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c

index 8d245ff059c9..8e3a5da24d59 100644

--- a/arch/powerpc/kernel/smp.c

+++ b/arch/powerpc/kernel/smp.c

@@ -1274,6 +1274,7 @@ static bool shared_caches;

 void start_secondary(void *unused)

 {

 	unsigned int cpu = smp_processor_id();

+	struct cpumask *(*sibling_mask)(int) = cpu_sibling_mask;

 	mmgrab(&init_mm);

 	current->active_mm = &init_mm;

@@ -1299,11 +1300,13 @@ void start_secondary(void *unused)

 	/* Update topology CPU masks */

 	add_cpu_to_masks(cpu);

+	if (has_big_cores)

+		sibling_mask = cpu_smallcore_mask;

 	/*

 	 * Check for any shared caches. Note that this must be done on a

 	 * per-core basis because one core in the pair might be disabled.

 	 */

-	if (!cpumask_equal(cpu_l2_cache_mask(cpu), cpu_sibling_mask(cpu)))

+	if (!cpumask_equal(cpu_l2_cache_mask(cpu), sibling_mask(cpu)))

 		shared_caches = true;

 	set_numa_node(numa_cpu_lookup_table[cpu]);

@@ -1370,6 +1373,13 @@ static const struct cpumask *shared_cache_mask(int cpu)

 	return cpu_l2_cache_mask(cpu);

 }

+#ifdef CONFIG_SCHED_SMT

+static const struct cpumask *smallcore_smt_mask(int cpu)

+{

+	return cpu_smallcore_mask(cpu);

+}

+#endif

+

 static struct sched_domain_topology_level power9_topology[] = {

 #ifdef CONFIG_SCHED_SMT

 	{ cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) },

@@ -1397,6 +1407,13 @@ void __init smp_cpus_done(unsigned int max_cpus)

 	shared_proc_topology_init();

 	dump_numa_cpu_topology();

+#ifdef CONFIG_SCHED_SMT

+	if (has_big_cores) {

+		pr_info("Using small cores at SMT level\n");

+		power9_topology[0].mask = smallcore_smt_mask;

+		powerpc_topology[0].mask = smallcore_smt_mask;

+	}

+#endif

 	/*

 	 * If any CPU detects that it's sharing a cache with another CPU then

 	 * use the deeper topology that is aware of this sharing.

-- 

2.13.7