From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>

Date: Wed, 27 Jun 2018 10:31:21 -0500

Subject: iommu/amd: Add support for higher 64-bit IOMMU Control Register

Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git

Git-commit: e881dbd5d4a6950c9e2e7623c79d9578949365c9

Patch-mainline: queued, upstream in v4.19-rc1

References: fate#324429

Currently, the driver only supports lower 32-bit of IOMMU Control register.

However, newer AMD IOMMU specification has extended this register

to 64-bit. Therefore, replace the accessing API with the 64-bit version.

Cc: Joerg Roedel <jroedel@suse.de>

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>

Signed-off-by: Joerg Roedel <jroedel@suse.de>

---

 drivers/iommu/amd_iommu_init.c | 26 +++++++++++++-------------

 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c

index 904c575d1677..7d494f2c28a1 100644

--- a/drivers/iommu/amd_iommu_init.c

+++ b/drivers/iommu/amd_iommu_init.c

@@ -280,9 +280,9 @@ static void clear_translation_pre_enabled(struct amd_iommu *iommu)

 static void init_translation_status(struct amd_iommu *iommu)

 {

-	u32 ctrl;

+	u64 ctrl;

-	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);

+	ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);

 	if (ctrl & (1<

 		iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;

 }

@@ -386,30 +386,30 @@ static void iommu_set_device_table(struct amd_iommu *iommu)

 /* Generic functions to enable/disable certain features of the IOMMU. */

 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)

 {

-	u32 ctrl;

+	u64 ctrl;

-	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);

-	ctrl |= (1 << bit);

-	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);

+	ctrl = readq(iommu->mmio_base +  MMIO_CONTROL_OFFSET);

+	ctrl |= (1ULL << bit);

+	writeq(ctrl, iommu->mmio_base +  MMIO_CONTROL_OFFSET);

 }

 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)

 {

-	u32 ctrl;

+	u64 ctrl;

-	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);

-	ctrl &= ~(1 << bit);

-	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);

+	ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);

+	ctrl &= ~(1ULL << bit);

+	writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);

 }

 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)

 {

-	u32 ctrl;

+	u64 ctrl;

-	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);

+	ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);

 	ctrl &= ~CTRL_INV_TO_MASK;

 	ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;

-	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);

+	writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);

 }

 /* Function to enable the hardware */