From 666db9c0405102aa362c0eb6a588d5772b841220 Mon Sep 17 00:00:00 2001

From: David Wu <david.wu@rock-chips.com>

Date: Fri, 26 May 2017 15:20:23 +0800

Subject: [PATCH 09/86] pinctrl: rockchip: Add iomux-route switching support

 for rk3399

Git-commit: accc1ce7d2ffc6419a8eaf8c0190d9240df0c43f

Patch-mainline: v4.13-rc1

References: fate#323912

There are 2 IP blocks pin routes need to be switched, that are

uart2dbg, pcie_clkreq.

Signed-off-by: David Wu <david.wu@rock-chips.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>

---

 drivers/pinctrl/pinctrl-rockchip.c | 41 ++++++++++++++++++++++++++++++++++++++

 1 file changed, 41 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c

index a0568a2cc125..e831647c56a6 100644

--- a/drivers/pinctrl/pinctrl-rockchip.c

+++ b/drivers/pinctrl/pinctrl-rockchip.c

@@ -811,6 +811,45 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = {

 	},

 };

+static struct rockchip_mux_route_data rk3399_mux_route_data[] = {

+	{

+		/* uart2dbga_rx */

+		.bank_num = 4,

+		.pin = 8,

+		.func = 2,

+		.route_offset = 0xe21c,

+		.route_val = BIT(16 + 10) | BIT(16 + 11),

+	}, {

+		/* uart2dbgb_rx */

+		.bank_num = 4,

+		.pin = 16,

+		.func = 2,

+		.route_offset = 0xe21c,

+		.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),

+	}, {

+		/* uart2dbgc_rx */

+		.bank_num = 4,

+		.pin = 19,

+		.func = 1,

+		.route_offset = 0xe21c,

+		.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),

+	}, {

+		/* pcie_clkreqn */

+		.bank_num = 2,

+		.pin = 26,

+		.func = 2,

+		.route_offset = 0xe21c,

+		.route_val = BIT(16 + 14),

+	}, {

+		/* pcie_clkreqnb */

+		.bank_num = 4,

+		.pin = 24,

+		.func = 1,

+		.route_offset = 0xe21c,

+		.route_val = BIT(16 + 14) | BIT(14),

+	},

+};

+

 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,

 				   int mux, u32 *reg, u32 *value)

 {

@@ -3234,6 +3273,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {

 		.pmu_mux_offset		= 0x0,

 		.grf_drv_offset		= 0xe100,

 		.pmu_drv_offset		= 0x80,

+		.iomux_routes		= rk3399_mux_route_data,

+		.niomux_routes		= ARRAY_SIZE(rk3399_mux_route_data),

 		.pull_calc_reg		= rk3399_calc_pull_reg_and_bit,

 		.drv_calc_reg		= rk3399_calc_drv_reg_and_bit,

 };

-- 

2.11.0