From c955bf3998efa3355790a4d8c82874582f1bc727 Mon Sep 17 00:00:00 2001

From: Chen Zhong <chen.zhong@mediatek.com>

Date: Thu, 5 Oct 2017 11:50:23 +0800

Subject: [PATCH] clk: mediatek: add the option for determining PLL source clock

Git-commit: c955bf3998efa3355790a4d8c82874582f1bc727

Patch-mainline: v4.15-rc1

References: bsc#1051510

Since the previous setup always sets the PLL using crystal 26MHz, this

doesn't always happen in every MediaTek platform. So the patch added

flexibility for assigning extra member for determining the PLL source

clock.

Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>

Signed-off-by: Sean Wang <sean.wang@mediatek.com>

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Acked-by: Takashi Iwai <tiwai@suse.de>

---

 drivers/clk/mediatek/clk-mtk.h | 1 +

 drivers/clk/mediatek/clk-pll.c | 5 ++++-

 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h

index f48df75cc901..f10250dcece4 100644

--- a/drivers/clk/mediatek/clk-mtk.h

+++ b/drivers/clk/mediatek/clk-mtk.h

@@ -218,6 +218,7 @@ struct mtk_pll_data {

 	uint32_t pcw_reg;

 	int pcw_shift;

 	const struct mtk_pll_div_table *div_table;

+	const char *parent_name;

 };

 void mtk_clk_register_plls(struct device_node *node,

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c

index 3c546bae6955..f54e4015b0b1 100644

--- a/drivers/clk/mediatek/clk-pll.c

+++ b/drivers/clk/mediatek/clk-pll.c

@@ -312,7 +312,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,

 	init.name = data->name;

 	init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;

 	init.ops = &mtk_pll_ops;

-	init.parent_names = &parent_name;

+	if (data->parent_name)

+		init.parent_names = &data->parent_name;

+	else

+		init.parent_names = &parent_name;

 	init.num_parents = 1;

 	clk = clk_register(NULL, &pll->hw);

-- 

2.18.0