From c45198b163fb5342290144b770a905f0d83821ad Mon Sep 17 00:00:00 2001

From: Imre Deak <imre.deak@intel.com>

Date: Tue, 6 Nov 2018 18:06:18 +0200

Subject: drm/i915/cnl+: Move the combo PHY init/uninit code to a new file

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Git-commit: c45198b163fb5342290144b770a905f0d83821ad

Patch-mainline: v5.0-rc1

References: fate#326289

Similarly to the GEN9_LP DPIO PHY code keep the CNL+ combo PHY code in a

separate file.

No functional change.

v2:

- Use SPDX license tag instead of boilerplate. (Rodrigo)

v3:

- Use MIT instead of GPL-2.0 license. (Ville)

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Cc: José Roberto de Souza <jose.souza@intel.com>

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

Link: https://patchwork.freedesktop.org/patch/msgid/20181106160621.23057-3-imre.deak@intel.com

Acked-by: Thomas Zimmermann <tzimmermann@suse.de>

---

 drivers/gpu/drm/i915/Makefile           |    1 

 drivers/gpu/drm/i915/i915_drv.h         |    6 +

 drivers/gpu/drm/i915/intel_combo_phy.c  |  141 ++++++++++++++++++++++++++++++++

 drivers/gpu/drm/i915/intel_runtime_pm.c |  125 +---------------------------

 4 files changed, 156 insertions(+), 117 deletions(-)

 create mode 100644 drivers/gpu/drm/i915/intel_combo_phy.c

--- a/drivers/gpu/drm/i915/Makefile

+++ b/drivers/gpu/drm/i915/Makefile

@@ -111,6 +111,7 @@ i915-y += intel_audio.o \

 	  intel_bios.o \

 	  intel_cdclk.o \

 	  intel_color.o \

+	  intel_combo_phy.o \

 	  intel_display.o \

 	  intel_dpio_phy.o \

 	  intel_dpll_mgr.o \

--- a/drivers/gpu/drm/i915/i915_drv.h

+++ b/drivers/gpu/drm/i915/i915_drv.h

@@ -3551,6 +3551,12 @@ void vlv_phy_pre_encoder_enable(struct i

 void vlv_phy_reset_lanes(struct intel_encoder *encoder,

 			 const struct intel_crtc_state *old_crtc_state);

+/* intel_combo_phy.c */

+void icl_combo_phys_init(struct drm_i915_private *dev_priv);

+void icl_combo_phys_uninit(struct drm_i915_private *dev_priv);

+void cnl_combo_phys_init(struct drm_i915_private *dev_priv);

+void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv);

+

 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);

 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);

 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,

--- /dev/null

+++ b/drivers/gpu/drm/i915/intel_combo_phy.c

@@ -0,0 +1,141 @@

+// SPDX-License-Identifier: MIT

+/*

+ * Copyright © 2018 Intel Corporation

+ */

+

+#include "intel_drv.h"

+

+enum {

+	PROCMON_0_85V_DOT_0,

+	PROCMON_0_95V_DOT_0,

+	PROCMON_0_95V_DOT_1,

+	PROCMON_1_05V_DOT_0,

+	PROCMON_1_05V_DOT_1,

+};

+

+static const struct cnl_procmon {

+	u32 dw1, dw9, dw10;

+} cnl_procmon_values[] = {

+	[PROCMON_0_85V_DOT_0] =

+		{ .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },

+	[PROCMON_0_95V_DOT_0] =

+		{ .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },

+	[PROCMON_0_95V_DOT_1] =

+		{ .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },

+	[PROCMON_1_05V_DOT_0] =

+		{ .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },

+	[PROCMON_1_05V_DOT_1] =

+		{ .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },

+};

+

+/*

+ * CNL has just one set of registers, while ICL has two sets: one for port A and

+ * the other for port B. The CNL registers are equivalent to the ICL port A

+ * registers, that's why we call the ICL macros even though the function has CNL

+ * on its name.

+ */

+static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,

+				       enum port port)

+{

+	const struct cnl_procmon *procmon;

+	u32 val;

+

+	val = I915_READ(ICL_PORT_COMP_DW3(port));

+	switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {

+	default:

+		MISSING_CASE(val);

+		/* fall through */

+	case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:

+		procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];

+		break;

+	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:

+		procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];

+		break;

+	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:

+		procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];

+		break;

+	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:

+		procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];

+		break;

+	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:

+		procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];

+		break;

+	}

+

+	val = I915_READ(ICL_PORT_COMP_DW1(port));

+	val &= ~((0xff << 16) | 0xff);

+	val |= procmon->dw1;

+	I915_WRITE(ICL_PORT_COMP_DW1(port), val);

+

+	I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);

+	I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);

+}

+

+void cnl_combo_phys_init(struct drm_i915_private *dev_priv)

+{

+	u32 val;

+

+	val = I915_READ(CHICKEN_MISC_2);

+	val &= ~CNL_COMP_PWR_DOWN;

+	I915_WRITE(CHICKEN_MISC_2, val);

+

+	/* Dummy PORT_A to get the correct CNL register from the ICL macro */

+	cnl_set_procmon_ref_values(dev_priv, PORT_A);

+

+	val = I915_READ(CNL_PORT_COMP_DW0);

+	val |= COMP_INIT;

+	I915_WRITE(CNL_PORT_COMP_DW0, val);

+

+	val = I915_READ(CNL_PORT_CL1CM_DW5);

+	val |= CL_POWER_DOWN_ENABLE;

+	I915_WRITE(CNL_PORT_CL1CM_DW5, val);

+}

+

+void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)

+{

+	u32 val;

+

+	val = I915_READ(CHICKEN_MISC_2);

+	val |= CNL_COMP_PWR_DOWN;

+	I915_WRITE(CHICKEN_MISC_2, val);

+}

+

+void icl_combo_phys_init(struct drm_i915_private *dev_priv)

+{

+	enum port port;

+

+	for (port = PORT_A; port <= PORT_B; port++) {

+		u32 val;

+

+		val = I915_READ(ICL_PHY_MISC(port));

+		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;

+		I915_WRITE(ICL_PHY_MISC(port), val);

+

+		cnl_set_procmon_ref_values(dev_priv, port);

+

+		val = I915_READ(ICL_PORT_COMP_DW0(port));

+		val |= COMP_INIT;

+		I915_WRITE(ICL_PORT_COMP_DW0(port), val);

+

+		val = I915_READ(ICL_PORT_CL_DW5(port));

+		val |= CL_POWER_DOWN_ENABLE;

+		I915_WRITE(ICL_PORT_CL_DW5(port), val);

+	}

+}

+

+void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)

+{

+	enum port port;

+

+	for (port = PORT_A; port <= PORT_B; port++) {

+		u32 val;

+

+		val = I915_READ(ICL_PHY_MISC(port));

+		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;

+		I915_WRITE(ICL_PHY_MISC(port), val);

+

+		val = I915_READ(ICL_PORT_COMP_DW0(port));

+		val &= ~COMP_INIT;

+		I915_WRITE(ICL_PORT_COMP_DW0(port), val);

+	}

+}

--- a/drivers/gpu/drm/i915/intel_runtime_pm.c

+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c

@@ -3464,72 +3464,6 @@ void bxt_display_core_uninit(struct drm_

 	usleep_range(10, 30);		/* 10 us delay per Bspec */

 }

-enum {

-	PROCMON_0_85V_DOT_0,

-	PROCMON_0_95V_DOT_0,

-	PROCMON_0_95V_DOT_1,

-	PROCMON_1_05V_DOT_0,

-	PROCMON_1_05V_DOT_1,

-};

-

-static const struct cnl_procmon {

-	u32 dw1, dw9, dw10;

-} cnl_procmon_values[] = {

-	[PROCMON_0_85V_DOT_0] =

-		{ .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },

-	[PROCMON_0_95V_DOT_0] =

-		{ .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },

-	[PROCMON_0_95V_DOT_1] =

-		{ .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },

-	[PROCMON_1_05V_DOT_0] =

-		{ .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },

-	[PROCMON_1_05V_DOT_1] =

-		{ .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },

-};

-

-/*

- * CNL has just one set of registers, while ICL has two sets: one for port A and

- * the other for port B. The CNL registers are equivalent to the ICL port A

- * registers, that's why we call the ICL macros even though the function has CNL

- * on its name.

- */

-static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,

-				       enum port port)

-{

-	const struct cnl_procmon *procmon;

-	u32 val;

-

-	val = I915_READ(ICL_PORT_COMP_DW3(port));

-	switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {

-	default:

-		MISSING_CASE(val);

-		/* fall through */

-	case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:

-		procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];

-		break;

-	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:

-		procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];

-		break;

-	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:

-		procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];

-		break;

-	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:

-		procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];

-		break;

-	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:

-		procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];

-		break;

-	}

-

-	val = I915_READ(ICL_PORT_COMP_DW1(port));

-	val &= ~((0xff << 16) | 0xff);

-	val |= procmon->dw1;

-	I915_WRITE(ICL_PORT_COMP_DW1(port), val);

-

-	I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);

-	I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);

-}

-

 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)

 {

 	struct i915_power_domains *power_domains = &dev_priv->power_domains;

@@ -3543,22 +3477,8 @@ static void cnl_display_core_init(struct

 	val |= RESET_PCH_HANDSHAKE_ENABLE;

 	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);

-	/* 2. Enable Comp */

-	val = I915_READ(CHICKEN_MISC_2);

-	val &= ~CNL_COMP_PWR_DOWN;

-	I915_WRITE(CHICKEN_MISC_2, val);

-

-	/* Dummy PORT_A to get the correct CNL register from the ICL macro */

-	cnl_set_procmon_ref_values(dev_priv, PORT_A);

-

-	val = I915_READ(CNL_PORT_COMP_DW0);

-	val |= COMP_INIT;

-	I915_WRITE(CNL_PORT_COMP_DW0, val);

-

-	/* 3. */

-	val = I915_READ(CNL_PORT_CL1CM_DW5);

-	val |= CL_POWER_DOWN_ENABLE;

-	I915_WRITE(CNL_PORT_CL1CM_DW5, val);

+	/* 2-3. */

+	cnl_combo_phys_init(dev_priv);

 	/*

 	 * 4. Enable Power Well 1 (PG1).

@@ -3583,7 +3503,6 @@ static void cnl_display_core_uninit(stru

 {

 	struct i915_power_domains *power_domains = &dev_priv->power_domains;

 	struct i915_power_well *well;

-	u32 val;

 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);

@@ -3607,10 +3526,8 @@ static void cnl_display_core_uninit(stru

 	usleep_range(10, 30);		/* 10 us delay per Bspec */

-	/* 5. Disable Comp */

-	val = I915_READ(CHICKEN_MISC_2);

-	val |= CNL_COMP_PWR_DOWN;

-	I915_WRITE(CHICKEN_MISC_2, val);

+	/* 5. */

+	cnl_combo_phys_uninit(dev_priv);

 }

 void icl_display_core_init(struct drm_i915_private *dev_priv,

@@ -3618,7 +3535,6 @@ void icl_display_core_init(struct drm_i9

 {

 	struct i915_power_domains *power_domains = &dev_priv->power_domains;

 	struct i915_power_well *well;

-	enum port port;

 	u32 val;

 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);

@@ -3628,23 +3544,8 @@ void icl_display_core_init(struct drm_i9

 	val |= RESET_PCH_HANDSHAKE_ENABLE;

 	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);

-	for (port = PORT_A; port <= PORT_B; port++) {

-		/* 2. Enable DDI combo PHY comp. */

-		val = I915_READ(ICL_PHY_MISC(port));

-		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;

-		I915_WRITE(ICL_PHY_MISC(port), val);

-

-		cnl_set_procmon_ref_values(dev_priv, port);

-

-		val = I915_READ(ICL_PORT_COMP_DW0(port));

-		val |= COMP_INIT;

-		I915_WRITE(ICL_PORT_COMP_DW0(port), val);

-

-		/* 3. Set power down enable. */

-		val = I915_READ(ICL_PORT_CL_DW5(port));

-		val |= CL_POWER_DOWN_ENABLE;

-		I915_WRITE(ICL_PORT_CL_DW5(port), val);

-	}

+	/* 2-3. */

+	icl_combo_phys_init(dev_priv);

 	/*

 	 * 4. Enable Power Well 1 (PG1).

@@ -3672,8 +3573,6 @@ void icl_display_core_uninit(struct drm_

 {

 	struct i915_power_domains *power_domains = &dev_priv->power_domains;

 	struct i915_power_well *well;

-	enum port port;

-	u32 val;

 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);

@@ -3695,16 +3594,8 @@ void icl_display_core_uninit(struct drm_

 	intel_power_well_disable(dev_priv, well);

 	mutex_unlock(&power_domains->lock);

-	/* 5. Disable Comp */

-	for (port = PORT_A; port <= PORT_B; port++) {

-		val = I915_READ(ICL_PHY_MISC(port));

-		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;

-		I915_WRITE(ICL_PHY_MISC(port), val);

-

-		val = I915_READ(ICL_PORT_COMP_DW0(port));

-		val &= ~COMP_INIT;

-		I915_WRITE(ICL_PORT_COMP_DW0(port), val);

-	}

+	/* 5. */

+	icl_combo_phys_uninit(dev_priv);

 }

 static void chv_phy_control_init(struct drm_i915_private *dev_priv)