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Thomas Zimmermann |
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From bb911536f07e5ed9147e3acf55a2cd72dffff70d Mon Sep 17 00:00:00 2001
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Thomas Zimmermann |
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From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
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Thomas Zimmermann |
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Date: Fri, 27 Oct 2017 22:31:26 +0300
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Thomas Zimmermann |
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Subject: [PATCH] drm/i915: Eliminate pll->state usage from bxt_calc_pll_link()
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Thomas Zimmermann |
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Mime-version: 1.0
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Content-type: text/plain; charset=UTF-8
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Thomas Zimmermann |
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Content-transfer-encoding: 8bit
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Thomas Zimmermann |
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Git-commit: bb911536f07e5ed9147e3acf55a2cd72dffff70d
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Thomas Zimmermann |
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Patch-mainline: v4.16-rc1
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References: FATE#322643 bsc#1055900
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Thomas Zimmermann |
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Thomas Zimmermann |
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We should be using the DPLL hw state we got from the current crtc state
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Thomas Zimmermann |
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to determine the corresponding port clock frequency rather than getting
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Thomas Zimmermann |
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it via the current state programmed into the DPLL.
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Thomas Zimmermann |
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Thomas Zimmermann |
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V2: Rebase due to intel_dpll_id changes
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Thomas Zimmermann |
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Thomas Zimmermann |
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Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Link: https://patchwork.freedesktop.org/patch/msgid/20171027193128.14483-5-ville.syrjala@linux.intel.com
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Thomas Zimmermann |
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Acked-by: Takashi Iwai <tiwai@suse.de>
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Thomas Zimmermann |
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Thomas Zimmermann |
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---
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Thomas Zimmermann |
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drivers/gpu/drm/i915/intel_ddi.c | 17 +++++------------
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1 file changed, 5 insertions(+), 12 deletions(-)
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Thomas Zimmermann |
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--- a/drivers/gpu/drm/i915/intel_ddi.c
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Thomas Zimmermann |
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+++ b/drivers/gpu/drm/i915/intel_ddi.c
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@@ -1423,19 +1423,16 @@ static void hsw_ddi_clock_get(struct int
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ddi_dotclock_get(pipe_config);
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}
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Thomas Zimmermann |
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Thomas Zimmermann |
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-static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
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- enum intel_dpll_id pll_id)
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+static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
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{
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- struct intel_shared_dpll *pll;
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Thomas Zimmermann |
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struct intel_dpll_hw_state *state;
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struct dpll clock;
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Thomas Zimmermann |
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Thomas Zimmermann |
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/* For DDI ports we always use a shared PLL. */
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Thomas Zimmermann |
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- if (WARN_ON(pll_id == DPLL_ID_PRIVATE))
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+ if (WARN_ON(!crtc_state->shared_dpll))
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return 0;
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Thomas Zimmermann |
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Thomas Zimmermann |
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- pll = &dev_priv->shared_dplls[pll_id];
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- state = &pll->state.hw_state;
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+ state = &crtc_state->dpll_hw_state;
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Thomas Zimmermann |
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clock.m1 = 2;
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clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
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@@ -1449,13 +1446,9 @@ static int bxt_calc_pll_link(struct drm_
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}
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static void bxt_ddi_clock_get(struct intel_encoder *encoder,
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- struct intel_crtc_state *pipe_config)
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Thomas Zimmermann |
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+ struct intel_crtc_state *pipe_config)
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{
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- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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- enum port port = encoder->port;
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- enum intel_dpll_id pll_id = port;
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-
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- pipe_config->port_clock = bxt_calc_pll_link(dev_priv, pll_id);
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Thomas Zimmermann |
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+ pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
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Thomas Zimmermann |
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ddi_dotclock_get(pipe_config);
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}
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