From 3164888a40469c102b5d6d1b756c7646e7eb19e7 Mon Sep 17 00:00:00 2001

From: Marta Lofstedt <marta.lofstedt@intel.com>

Date: Fri, 8 Sep 2017 16:28:29 +0300

Subject: [PATCH] drm/i915: Increase poll time for BDW FCLK_DONE

Git-commit: 3164888a40469c102b5d6d1b756c7646e7eb19e7

Patch-mainline: v4.15-rc1

References: FATE#322643 bsc#1055900

During IGT testing it has been shown that the specification

defined polling time of 1 us for FCLK_DONE, is sometimes not

enough. The issue is still reproducible while disabling

C-states through the PM QoS framework and also while disabling

preemtion. From this the most plausible explanation is that the

issue is due to a firmware flaw.

As a workaround, it is better to wait a little bit longer for

the FCLK_DONE to come around, than to leave with an DRM_ERROR

and having FCLK_DONE at a randome time after.

While spinning a list of igt tests prone to reproduce the issue

the FCLK_DONE poll failed at approximately 2% of the invocations

of the bdw_set_cdclk function. The longest poll time during this

testing was measured to ~7us. So, the suggested new poll time of

100us is on the safe side.

V2: Added more documentation about investigations done.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102243

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Signed-off-by: Imre Deak <imre.deak@intel.com>

Link: https://patchwork.freedesktop.org/patch/msgid/20170908132829.6312-1-marta.lofstedt@intel.com

Acked-by: Takashi Iwai <tiwai@suse.de>

---

 drivers/gpu/drm/i915/intel_cdclk.c |    6 +++++-

 1 file changed, 5 insertions(+), 1 deletion(-)

--- a/drivers/gpu/drm/i915/intel_cdclk.c

+++ b/drivers/gpu/drm/i915/intel_cdclk.c

@@ -669,8 +669,12 @@ static void bdw_set_cdclk(struct drm_i91

 	val |= LCPLL_CD_SOURCE_FCLK;

 	I915_WRITE(LCPLL_CTL, val);

+	/*

+	 * According to the spec, it should be enough to poll for this 1 us.

+	 * However, extensive testing shows that this can take longer.

+	 */

 	if (wait_for_us(I915_READ(LCPLL_CTL) &

-			LCPLL_CD_SOURCE_FCLK_DONE, 1))

+			LCPLL_CD_SOURCE_FCLK_DONE, 100))

 		DRM_ERROR("Switching to FCLK failed\n");

 	val = I915_READ(LCPLL_CTL);