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Jiri Slaby |
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From: Kan Liang <kan.liang@linux.intel.com>
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Jiri Slaby |
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Date: Fri, 10 Feb 2023 11:02:38 -0800
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Subject: [PATCH] perf/x86/intel/uncore: Add Meteor Lake support
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References: bsc#1012628
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Patch-mainline: 6.2.3
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Git-commit: c828441f21ddc819a28b5723a72e3c840e9de1c6
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[ Upstream commit c828441f21ddc819a28b5723a72e3c840e9de1c6 ]
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The uncore subsystem for Meteor Lake is similar to the previous Alder
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Lake. The main difference is that MTL provides PMU support for different
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tiles, while ADL only provides PMU support for the whole package. On
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ADL, there are CBOX, ARB, and clockbox uncore PMON units. On MTL, they
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are split into CBOX/HAC_CBOX, ARB/HAC_ARB, and cncu/sncu which provides
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a fixed counter for clockticks. Also, new MSR addresses are introduced
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on MTL.
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The IMC uncore PMON is the same as Alder Lake. Add new PCIIDs of IMC for
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Meteor Lake.
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Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Link: https://lore.kernel.org/r/20230210190238.1726237-1-kan.liang@linux.intel.com
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Signed-off-by: Sasha Levin <sashal@kernel.org>
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Signed-off-by: Jiri Slaby <jslaby@suse.cz>
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---
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arch/x86/events/intel/uncore.c | 7 ++
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arch/x86/events/intel/uncore.h | 1 +
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arch/x86/events/intel/uncore_snb.c | 161 +++++++++++++++++++++++++++++
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3 files changed, 169 insertions(+)
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diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
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index 459b1aaf..27b34f5b 100644
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--- a/arch/x86/events/intel/uncore.c
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+++ b/arch/x86/events/intel/uncore.c
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@@ -1765,6 +1765,11 @@ static const struct intel_uncore_init_fun adl_uncore_init __initconst = {
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.mmio_init = adl_uncore_mmio_init,
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};
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+static const struct intel_uncore_init_fun mtl_uncore_init __initconst = {
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+ .cpu_init = mtl_uncore_cpu_init,
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+ .mmio_init = adl_uncore_mmio_init,
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+};
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+
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static const struct intel_uncore_init_fun icx_uncore_init __initconst = {
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.cpu_init = icx_uncore_cpu_init,
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.pci_init = icx_uncore_pci_init,
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@@ -1832,6 +1837,8 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
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X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &adl_uncore_init),
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X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &adl_uncore_init),
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X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &adl_uncore_init),
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+ X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, &mtl_uncore_init),
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+ X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, &mtl_uncore_init),
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X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &spr_uncore_init),
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X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &spr_uncore_init),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &snr_uncore_init),
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diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
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index e278e2e7..305a54d8 100644
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--- a/arch/x86/events/intel/uncore.h
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+++ b/arch/x86/events/intel/uncore.h
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@@ -602,6 +602,7 @@ void skl_uncore_cpu_init(void);
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void icl_uncore_cpu_init(void);
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void tgl_uncore_cpu_init(void);
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void adl_uncore_cpu_init(void);
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+void mtl_uncore_cpu_init(void);
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void tgl_uncore_mmio_init(void);
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void tgl_l_uncore_mmio_init(void);
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void adl_uncore_mmio_init(void);
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diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
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index 1f486922..7fd4334e 100644
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--- a/arch/x86/events/intel/uncore_snb.c
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+++ b/arch/x86/events/intel/uncore_snb.c
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@@ -109,6 +109,19 @@
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#define PCI_DEVICE_ID_INTEL_RPL_23_IMC 0xA728
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#define PCI_DEVICE_ID_INTEL_RPL_24_IMC 0xA729
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#define PCI_DEVICE_ID_INTEL_RPL_25_IMC 0xA72A
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+#define PCI_DEVICE_ID_INTEL_MTL_1_IMC 0x7d00
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+#define PCI_DEVICE_ID_INTEL_MTL_2_IMC 0x7d01
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+#define PCI_DEVICE_ID_INTEL_MTL_3_IMC 0x7d02
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+#define PCI_DEVICE_ID_INTEL_MTL_4_IMC 0x7d05
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+#define PCI_DEVICE_ID_INTEL_MTL_5_IMC 0x7d10
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+#define PCI_DEVICE_ID_INTEL_MTL_6_IMC 0x7d14
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+#define PCI_DEVICE_ID_INTEL_MTL_7_IMC 0x7d15
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+#define PCI_DEVICE_ID_INTEL_MTL_8_IMC 0x7d16
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+#define PCI_DEVICE_ID_INTEL_MTL_9_IMC 0x7d21
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+#define PCI_DEVICE_ID_INTEL_MTL_10_IMC 0x7d22
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+#define PCI_DEVICE_ID_INTEL_MTL_11_IMC 0x7d23
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+#define PCI_DEVICE_ID_INTEL_MTL_12_IMC 0x7d24
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+#define PCI_DEVICE_ID_INTEL_MTL_13_IMC 0x7d28
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#define IMC_UNCORE_DEV(a) \
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@@ -205,6 +218,32 @@
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#define ADL_UNC_ARB_PERFEVTSEL0 0x2FD0
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#define ADL_UNC_ARB_MSR_OFFSET 0x8
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+/* MTL Cbo register */
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+#define MTL_UNC_CBO_0_PER_CTR0 0x2448
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+#define MTL_UNC_CBO_0_PERFEVTSEL0 0x2442
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+
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+/* MTL HAC_ARB register */
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+#define MTL_UNC_HAC_ARB_CTR 0x2018
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+#define MTL_UNC_HAC_ARB_CTRL 0x2012
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+
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+/* MTL ARB register */
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+#define MTL_UNC_ARB_CTR 0x2418
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+#define MTL_UNC_ARB_CTRL 0x2412
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+
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+/* MTL cNCU register */
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+#define MTL_UNC_CNCU_FIXED_CTR 0x2408
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+#define MTL_UNC_CNCU_FIXED_CTRL 0x2402
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+#define MTL_UNC_CNCU_BOX_CTL 0x240e
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+
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+/* MTL sNCU register */
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+#define MTL_UNC_SNCU_FIXED_CTR 0x2008
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+#define MTL_UNC_SNCU_FIXED_CTRL 0x2002
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+#define MTL_UNC_SNCU_BOX_CTL 0x200e
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+
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+/* MTL HAC_CBO register */
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+#define MTL_UNC_HBO_CTR 0x2048
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+#define MTL_UNC_HBO_CTRL 0x2042
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+
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DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
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DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
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DEFINE_UNCORE_FORMAT_ATTR(chmask, chmask, "config:8-11");
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@@ -598,6 +637,115 @@ void adl_uncore_cpu_init(void)
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uncore_msr_uncores = adl_msr_uncores;
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}
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+static struct intel_uncore_type mtl_uncore_cbox = {
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+ .name = "cbox",
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+ .num_counters = 2,
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+ .perf_ctr_bits = 48,
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+ .perf_ctr = MTL_UNC_CBO_0_PER_CTR0,
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+ .event_ctl = MTL_UNC_CBO_0_PERFEVTSEL0,
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+ .event_mask = ADL_UNC_RAW_EVENT_MASK,
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+ .msr_offset = SNB_UNC_CBO_MSR_OFFSET,
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+ .ops = &icl_uncore_msr_ops,
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+ .format_group = &adl_uncore_format_group,
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+};
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+
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+static struct intel_uncore_type mtl_uncore_hac_arb = {
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+ .name = "hac_arb",
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+ .num_counters = 2,
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+ .num_boxes = 2,
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+ .perf_ctr_bits = 48,
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+ .perf_ctr = MTL_UNC_HAC_ARB_CTR,
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+ .event_ctl = MTL_UNC_HAC_ARB_CTRL,
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+ .event_mask = ADL_UNC_RAW_EVENT_MASK,
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+ .msr_offset = SNB_UNC_CBO_MSR_OFFSET,
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+ .ops = &icl_uncore_msr_ops,
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+ .format_group = &adl_uncore_format_group,
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+};
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+
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+static struct intel_uncore_type mtl_uncore_arb = {
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+ .name = "arb",
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+ .num_counters = 2,
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+ .num_boxes = 2,
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+ .perf_ctr_bits = 48,
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+ .perf_ctr = MTL_UNC_ARB_CTR,
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+ .event_ctl = MTL_UNC_ARB_CTRL,
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+ .event_mask = ADL_UNC_RAW_EVENT_MASK,
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+ .msr_offset = SNB_UNC_CBO_MSR_OFFSET,
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+ .ops = &icl_uncore_msr_ops,
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+ .format_group = &adl_uncore_format_group,
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+};
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+
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+static struct intel_uncore_type mtl_uncore_hac_cbox = {
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+ .name = "hac_cbox",
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+ .num_counters = 2,
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+ .num_boxes = 2,
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+ .perf_ctr_bits = 48,
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+ .perf_ctr = MTL_UNC_HBO_CTR,
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+ .event_ctl = MTL_UNC_HBO_CTRL,
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+ .event_mask = ADL_UNC_RAW_EVENT_MASK,
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+ .msr_offset = SNB_UNC_CBO_MSR_OFFSET,
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+ .ops = &icl_uncore_msr_ops,
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+ .format_group = &adl_uncore_format_group,
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+};
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+
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+static void mtl_uncore_msr_init_box(struct intel_uncore_box *box)
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+{
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+ wrmsrl(uncore_msr_box_ctl(box), SNB_UNC_GLOBAL_CTL_EN);
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+}
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+
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+static struct intel_uncore_ops mtl_uncore_msr_ops = {
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+ .init_box = mtl_uncore_msr_init_box,
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+ .disable_event = snb_uncore_msr_disable_event,
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+ .enable_event = snb_uncore_msr_enable_event,
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+ .read_counter = uncore_msr_read_counter,
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+};
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+
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+static struct intel_uncore_type mtl_uncore_cncu = {
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+ .name = "cncu",
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+ .num_counters = 1,
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+ .num_boxes = 1,
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+ .box_ctl = MTL_UNC_CNCU_BOX_CTL,
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+ .fixed_ctr_bits = 48,
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+ .fixed_ctr = MTL_UNC_CNCU_FIXED_CTR,
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+ .fixed_ctl = MTL_UNC_CNCU_FIXED_CTRL,
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+ .single_fixed = 1,
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+ .event_mask = SNB_UNC_CTL_EV_SEL_MASK,
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+ .format_group = &icl_uncore_clock_format_group,
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+ .ops = &mtl_uncore_msr_ops,
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+ .event_descs = icl_uncore_events,
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+};
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+
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+static struct intel_uncore_type mtl_uncore_sncu = {
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+ .name = "sncu",
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+ .num_counters = 1,
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+ .num_boxes = 1,
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+ .box_ctl = MTL_UNC_SNCU_BOX_CTL,
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+ .fixed_ctr_bits = 48,
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+ .fixed_ctr = MTL_UNC_SNCU_FIXED_CTR,
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+ .fixed_ctl = MTL_UNC_SNCU_FIXED_CTRL,
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+ .single_fixed = 1,
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+ .event_mask = SNB_UNC_CTL_EV_SEL_MASK,
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+ .format_group = &icl_uncore_clock_format_group,
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+ .ops = &mtl_uncore_msr_ops,
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ef7db2 |
+ .event_descs = icl_uncore_events,
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ef7db2 |
+};
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ef7db2 |
+
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ef7db2 |
+static struct intel_uncore_type *mtl_msr_uncores[] = {
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ef7db2 |
+ &mtl_uncore_cbox,
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ef7db2 |
+ &mtl_uncore_hac_arb,
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ef7db2 |
+ &mtl_uncore_arb,
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ef7db2 |
+ &mtl_uncore_hac_cbox,
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ef7db2 |
+ &mtl_uncore_cncu,
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ef7db2 |
+ &mtl_uncore_sncu,
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ef7db2 |
+ NULL
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ef7db2 |
+};
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ef7db2 |
+
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ef7db2 |
+void mtl_uncore_cpu_init(void)
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ef7db2 |
+{
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ef7db2 |
+ mtl_uncore_cbox.num_boxes = icl_get_cbox_num();
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ef7db2 |
+ uncore_msr_uncores = mtl_msr_uncores;
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ef7db2 |
+}
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ef7db2 |
+
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ef7db2 |
enum {
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SNB_PCI_UNCORE_IMC,
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ef7db2 |
};
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ef7db2 |
@@ -1264,6 +1412,19 @@ static const struct pci_device_id tgl_uncore_pci_ids[] = {
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IMC_UNCORE_DEV(RPL_23),
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ef7db2 |
IMC_UNCORE_DEV(RPL_24),
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IMC_UNCORE_DEV(RPL_25),
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ef7db2 |
+ IMC_UNCORE_DEV(MTL_1),
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ef7db2 |
+ IMC_UNCORE_DEV(MTL_2),
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ef7db2 |
+ IMC_UNCORE_DEV(MTL_3),
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ef7db2 |
+ IMC_UNCORE_DEV(MTL_4),
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ef7db2 |
+ IMC_UNCORE_DEV(MTL_5),
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ef7db2 |
+ IMC_UNCORE_DEV(MTL_6),
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ef7db2 |
+ IMC_UNCORE_DEV(MTL_7),
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ef7db2 |
+ IMC_UNCORE_DEV(MTL_8),
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ef7db2 |
+ IMC_UNCORE_DEV(MTL_9),
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ef7db2 |
+ IMC_UNCORE_DEV(MTL_10),
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ef7db2 |
+ IMC_UNCORE_DEV(MTL_11),
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ef7db2 |
+ IMC_UNCORE_DEV(MTL_12),
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ef7db2 |
+ IMC_UNCORE_DEV(MTL_13),
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ef7db2 |
{ /* end: all zeroes */ }
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};
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ef7db2 |
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--
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2.35.3
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ef7db2 |
|