From: Kevin Groeneveld <kgroeneveld@lenbrook.com>

Date: Sat, 18 Mar 2023 18:21:32 -0400

Subject: [PATCH] spi: spi-imx: fix MX51_ECSPI_* macros when cs > 3

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References: bsc#1012628

Patch-mainline: 6.3.4

Git-commit: 87c614175bbf28d3fd076dc2d166bac759e41427

[ Upstream commit 87c614175bbf28d3fd076dc2d166bac759e41427 ]

When using gpio based chip select the cs value can go outside the range

0 – 3. The various MX51_ECSPI_* macros did not take this into consideration

resulting in possible corruption of the configuration.

For example for any cs value over 3 the SCLKPHA bits would not be set and

other values in the register possibly corrupted.

One way to fix this is to just mask the cs bits to 2 bits. This still

allows all 4 native chip selects to work as well as gpio chip selects

(which can use any of the 4 chip select configurations).

Signed-off-by: Kevin Groeneveld <kgroeneveld@lenbrook.com>

Link: https://lore.kernel.org/r/20230318222132.3373-1-kgroeneveld@lenbrook.com

Signed-off-by: Mark Brown <broonie@kernel.org>

Signed-off-by: Sasha Levin <sashal@kernel.org>

Signed-off-by: Jiri Slaby <jslaby@suse.cz>

---

 drivers/spi/spi-imx.c | 24 ++++++++++++++++++------

 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c

index 6c9c87cd..a2a5ada6 100644

--- a/drivers/spi/spi-imx.c

+++ b/drivers/spi/spi-imx.c

@@ -252,6 +252,18 @@ static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device

 	return true;

 }

+/*

+ * Note the number of natively supported chip selects for MX51 is 4. Some

+ * devices may have less actual SS pins but the register map supports 4. When

+ * using gpio chip selects the cs values passed into the macros below can go

+ * outside the range 0 - 3. We therefore need to limit the cs value to avoid

+ * corrupting bits outside the allocated locations.

+ *

+ * The simplest way to do this is to just mask the cs bits to 2 bits. This

+ * still allows all 4 native chip selects to work as well as gpio chip selects

+ * (which can use any of the 4 chip select configurations).

+ */

+

 #define MX51_ECSPI_CTRL		0x08

 #define MX51_ECSPI_CTRL_ENABLE		(1 <<  0)

 #define MX51_ECSPI_CTRL_XCH		(1 <<  2)

@@ -260,16 +272,16 @@ static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device

 #define MX51_ECSPI_CTRL_DRCTL(drctl)	((drctl) << 16)

 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET	8

 #define MX51_ECSPI_CTRL_PREDIV_OFFSET	12

-#define MX51_ECSPI_CTRL_CS(cs)		((cs) << 18)

+#define MX51_ECSPI_CTRL_CS(cs)		((cs & 3) << 18)

 #define MX51_ECSPI_CTRL_BL_OFFSET	20

 #define MX51_ECSPI_CTRL_BL_MASK		(0xfff << 20)

 #define MX51_ECSPI_CONFIG	0x0c

-#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))

-#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))

-#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))

-#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))

-#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs) + 20))

+#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs & 3) +  0))

+#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs & 3) +  4))

+#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs & 3) +  8))

+#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs & 3) + 12))

+#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs & 3) + 20))

 #define MX51_ECSPI_INT		0x10

 #define MX51_ECSPI_INT_TEEN		(1 <<  0)

-- 

2.35.3