From: David Woodhouse <dwmw@amazon.co.uk>

Date: Wed, 7 Oct 2020 13:20:45 +0100

Subject: [PATCH 4/5] x86/apic: Support 15 bits of APIC ID in IOAPIC/MSI where

 available

Patch-mainline: Never, upstream uses different implementation

References: bsc#1181001, jsc#ECO-3191

Some hypervisors can allow the guest to use the Extended Destination ID

field in the IOAPIC RTE and MSI address to address up to 32768 CPUs.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>

Acked-by: Joerg Roedel <jroedel@suse.de>

---

 arch/x86/include/asm/mpspec.h   |    1 +

 arch/x86/include/asm/x86_init.h |    2 ++

 arch/x86/kernel/apic/apic.c     |   15 ++++++++++++++-

 arch/x86/kernel/apic/msi.c      |    9 ++++++++-

 arch/x86/kernel/x86_init.c      |    1 +

 5 files changed, 26 insertions(+), 2 deletions(-)

--- a/arch/x86/include/asm/mpspec.h

+++ b/arch/x86/include/asm/mpspec.h

@@ -41,6 +41,7 @@ extern DECLARE_BITMAP(mp_bus_not_pci, MA

 extern unsigned int boot_cpu_physical_apicid;

 extern u8 boot_cpu_apic_version;

 extern unsigned long mp_lapic_addr;

+extern int msi_ext_dest_id;

 #ifdef CONFIG_X86_LOCAL_APIC

 extern int smp_found_config;

--- a/arch/x86/include/asm/x86_init.h

+++ b/arch/x86/include/asm/x86_init.h

@@ -117,11 +117,13 @@ struct x86_init_pci {

  * struct x86_hyper_init - x86 hypervisor init functions

  * @init_platform:		platform setup

  * @x2apic_available:		X2APIC detection

+ * @msi_ext_dest_id:		MSI and IOAPIC support 15-bit APIC IDs

  * @init_mem_mapping:		setup early mappings during init_mem_mapping()

  */

 struct x86_hyper_init {

 	void (*init_platform)(void);

 	bool (*x2apic_available)(void);

+	bool (*msi_ext_dest_id)(void);

 	void (*init_mem_mapping)(void);

 };

--- a/arch/x86/kernel/apic/apic.c

+++ b/arch/x86/kernel/apic/apic.c

@@ -1576,9 +1576,21 @@ static __init void x2apic_enable(void)

 static __init void try_to_enable_x2apic(int remap_mode)

 {

+	u32 apic_limit = 255;

+

 	if (x2apic_state == X2APIC_DISABLED)

 		return;

+	/*

+	 * If the hypervisor supports extended destination ID in IOAPIC

+	 * and MSI, that increases the maximum APIC ID that can be used

+	 * for non-remapped IRQ domains.

+	 */

+	if (x86_init.hyper.msi_ext_dest_id()) {

+		msi_ext_dest_id = 1;

+		apic_limit = 32767;

+	}

+

 	if (remap_mode != IRQ_REMAP_X2APIC_MODE) {

 		/*

 		 * Using X2APIC without IR is not architecturally supported

@@ -1595,9 +1607,10 @@ static __init void try_to_enable_x2apic(

 		 * in physical mode, and CPUs with an APIC ID that cannnot

 		 * be addressed must not be brought online.

 		 */

-		x2apic_set_max_apicid(255);

+		x2apic_set_max_apicid(apic_limit);

 		x2apic_phys = 1;

 	}

+

 	x2apic_enable();

 }

--- a/arch/x86/kernel/apic/msi.c

+++ b/arch/x86/kernel/apic/msi.c

@@ -25,6 +25,8 @@

 static struct irq_domain *msi_default_domain;

+int msi_ext_dest_id;

+

 static void __irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg,

 				  bool dmar)

 {

@@ -54,10 +56,15 @@ static void __irq_msi_compose_msg(struct

 	 * Only the IOMMU itself can use the trick of putting destination

 	 * APIC ID into the high bits of the address. Anything else would

 	 * just be writing to memory if it tried that, and needs IR to

-	 * address higher APIC IDs.

+	 * address APICs which can't be addressed in the normal 32-bit

+	 * address range at 0xFFExxxxx. That is typically just 8 bits, but

+	 * some hypervisors allow the extended destination ID field in bits

+	 * 11-5 to be used, giving support for 15 bits of APIC IDs in total.

 	 */

 	if (dmar)

 		msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);

+	else if (msi_ext_dest_id && cfg->dest_apicid < 0x8000)

+		msg->address_lo |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid) >> 3;

 	else

 		WARN_ON_ONCE(MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid));

 }

--- a/arch/x86/kernel/x86_init.c

+++ b/arch/x86/kernel/x86_init.c

@@ -87,6 +87,7 @@ struct x86_init_ops x86_init __initdata

 	.hyper = {

 		.init_platform		= x86_init_noop,

 		.x2apic_available	= bool_x86_init_noop,

+		.msi_ext_dest_id	= bool_x86_init_noop,

 		.init_mem_mapping	= x86_init_noop,

 	},

 };