Patrik Jakobsson 2a14e0
From f91ab25847fa52beb6d80a4983078a46caf01a3f Mon Sep 17 00:00:00 2001
Patrik Jakobsson 2a14e0
From: Dillon Varone <Dillon.Varone@amd.com>
Patrik Jakobsson 2a14e0
Date: Mon, 7 Nov 2022 15:18:47 -0500
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Subject: drm/amd/display: Update soc bounding box for dcn32/dcn321
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Git-commit: 5d82c82f1dbee264f7a94587adbbfee607706902
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Patch-mainline: v6.1-rc7
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References: jsc#PED-1166 jsc#PED-1168 jsc#PED-1170 jsc#PED-1218 jsc#PED-1220 jsc#PED-1222 jsc#PED-1223 jsc#PED-1225 jsc#PED-2849
Patrik Jakobsson 2a14e0
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[Description]
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New values for soc bounding box and dummy pstate.
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Reviewed-by: Jun Lei <Jun.Lei@amd.com>
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Acked-by: Brian Chang <Brian.Chang@amd.com>
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Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
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Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Cc: stable@vger.kernel.org # 6.0.x
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Acked-by: Patrik Jakobsson <pjakobsson@suse.de>
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---
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 drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c   | 6 +++---
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 drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 8 ++++----
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 2 files changed, 7 insertions(+), 7 deletions(-)
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diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
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index 12e17bcfca3f..9ca8120461a7 100644
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--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
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+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
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@@ -157,7 +157,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
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 	.dispclk_dppclk_vco_speed_mhz = 4300.0,
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 	.do_urgent_latency_adjustment = true,
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 	.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
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-	.urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
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+	.urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
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 };
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 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
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@@ -211,7 +211,7 @@ void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
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 	/* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
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 	if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
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 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
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-		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 38;
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+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50;
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 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;
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 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
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 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
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@@ -221,7 +221,7 @@ void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
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 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
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 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
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 		clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
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-		clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;
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+		clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50;
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 		clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;
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 		clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
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 		clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
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diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
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index 432b4ecd01a7..f4b176599be7 100644
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--- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
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+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
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@@ -126,9 +126,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
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 	.sr_enter_plus_exit_z8_time_us = 320,
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 	.writeback_latency_us = 12.0,
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 	.round_trip_ping_latency_dcfclk_cycles = 263,
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-	.urgent_latency_pixel_data_only_us = 9.35,
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-	.urgent_latency_pixel_mixed_with_vm_data_us = 9.35,
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-	.urgent_latency_vm_data_only_us = 9.35,
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+	.urgent_latency_pixel_data_only_us = 4,
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+	.urgent_latency_pixel_mixed_with_vm_data_us = 4,
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+	.urgent_latency_vm_data_only_us = 4,
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 	.fclk_change_latency_us = 20,
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 	.usr_retraining_latency_us = 2,
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 	.smn_latency_us = 2,
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@@ -156,7 +156,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
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 	.dispclk_dppclk_vco_speed_mhz = 4300.0,
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 	.do_urgent_latency_adjustment = true,
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 	.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
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-	.urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
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+	.urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
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 };
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 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
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-- 
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2.38.1
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