From 17310440c84ea47c8b6e3ee36b98e73a2cb74d00 Mon Sep 17 00:00:00 2001

From: "Shen, George" <George.Shen@amd.com>

Date: Mon, 15 Nov 2021 22:38:18 -0500

Subject: drm/amd/display: Clear DPCD lane settings after repeater training

Git-commit: ef548afe05f8d8c5af0fc44b035d5283156f8b03

Patch-mainline: v5.16-rc4

References: jsc#PED-1166 jsc#PED-1168 jsc#PED-1170 jsc#PED-1218 jsc#PED-1220 jsc#PED-1222 jsc#PED-1223 jsc#PED-1225

[Why]

VS and PE requested by repeater should not persist for the sink.

[How]

Clear DPCD lane settings after repeater link training finishes.

Reviewed-by: Wesley Chalmers <wesley.chalmers@amd.com>

Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

Signed-off-by: George Shen <George.Shen@amd.com>

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Acked-by: Patrik Jakobsson <pjakobsson@suse.de>

---

 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-

 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

index cb7bf9148904..13bc69d6b679 100644

--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

@@ -2138,7 +2138,7 @@ static enum link_training_result dp_perform_8b_10b_link_training(

 		}

 		for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)

-			lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET = VOLTAGE_SWING_LEVEL0;

+			lt_settings->dpcd_lane_settings[lane].raw = 0;

 	}

 	if (status == LINK_TRAINING_SUCCESS) {

-- 

2.38.1