From 754c4050a00e802e122690112fc2c3a6abafa7e2 Mon Sep 17 00:00:00 2001

From: Florian Fainelli <f.fainelli@gmail.com>

Date: Wed, 27 Oct 2021 12:37:29 -0700

Subject: [PATCH] ARM: dts: BCM5301X: Fix I2C controller interrupt

Git-commit: 754c4050a00e802e122690112fc2c3a6abafa7e2

Patch-mainline: v5.16-rc3

References: git-fixes

The I2C interrupt controller line is off by 32 because the datasheet

describes interrupt inputs into the GIC which are for Shared Peripheral

Interrupts and are starting at offset 32. The ARM GIC binding expects

the SPI interrupts to be numbered from 0 relative to the SPI base.

Fixes: bb097e3e0045 ("ARM: dts: BCM5301X: Add I2C support to the DT")

Tested-by: Christian Lamparter <chunkeey@gmail.com>

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

Acked-by: Takashi Iwai <tiwai@suse.de>

---

 arch/arm/boot/dts/bcm5301x.dtsi | 2 +-

 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi

index d4f355015e3c..437a2b0f68de 100644

--- a/arch/arm/boot/dts/bcm5301x.dtsi

+++ b/arch/arm/boot/dts/bcm5301x.dtsi

@@ -408,7 +408,7 @@ uart2: serial@18008000 {

 	i2c0: i2c@18009000 {

 		compatible = "brcm,iproc-i2c";

 		reg = <0x18009000 0x50>;

-		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

+		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

 		#address-cells = <1>;

 		#size-cells = <0>;

 		clock-frequency = <100000>;

-- 

2.31.1