From: Wanpeng Li <wanpeng.li@hotmail.com>

Date: Fri, 6 Oct 2017 07:38:32 -0700

Subject: KVM: LAPIC: Apply change to TDCR right away to the timer

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Patch-mainline: v4.15-rc1

Git-commit: c301b909e4b94e6395251787e28b335c51309fff

References: bsc#1077761

The description in the Intel SDM of how the divide configuration

register is used: "The APIC timer frequency will be the processor's bus

clock or core crystal clock frequency divided by the value specified in

the divide configuration register."

Observation of baremetal shown that when the TDCR is change, the TMCCT

does not change or make a big jump in value, but the rate at which it

count down change.

The patch update the emulation to APIC timer to so that a change to the

divide configuration would be reflected in the value of the counter and

when the next interrupt is triggered.

Cc: Paolo Bonzini <pbonzini@redhat.com>

Cc: Radim Krčmář <rkrcmar@redhat.com>

Signed-off-by: Wanpeng Li <wanpeng.li@hotmail.com>

[Fixed some whitespace and added a check for negative delta and running

 timer. - Radim]

Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>

Acked-by: Alexander Graf <agraf@suse.de>

---

 arch/x86/kvm/lapic.c |   36 ++++++++++++++++++++++++++++++++++--

 1 file changed, 34 insertions(+), 2 deletions(-)

--- a/arch/x86/kvm/lapic.c

+++ b/arch/x86/kvm/lapic.c

@@ -1456,6 +1456,30 @@

 		HRTIMER_MODE_ABS_PINNED);

 }

+static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)

+{

+	ktime_t now, remaining;

+	u64 ns_remaining_old, ns_remaining_new;

+

+	apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)

+		* APIC_BUS_CYCLE_NS * apic->divide_count;

+	limit_periodic_timer_frequency(apic);

+

+	now = ktime_get();

+	remaining = ktime_sub(apic->lapic_timer.target_expiration, now);

+	if (ktime_to_ns(remaining) < 0)

+		remaining = 0;

+

+	ns_remaining_old = ktime_to_ns(remaining);

+	ns_remaining_new = mul_u64_u32_div(ns_remaining_old,

+	                                   apic->divide_count, old_divisor);

+

+	apic->lapic_timer.tscdeadline +=

+		nsec_to_cycles(apic->vcpu, ns_remaining_new) -

+		nsec_to_cycles(apic->vcpu, ns_remaining_old);

+	apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);

+}

+

 static bool set_target_expiration(struct kvm_lapic *apic)

 {

 	ktime_t now;

@@ -1748,13 +1772,21 @@

 		start_apic_timer(apic);

 		break;

-	case APIC_TDCR:

+	case APIC_TDCR: {

+		uint32_t old_divisor = apic->divide_count;

+

 		if (val & 4)

 			apic_debug("KVM_WRITE:TDCR %x\n", val);

 		kvm_lapic_set_reg(apic, APIC_TDCR, val);

 		update_divide_count(apic);

+		if (apic->divide_count != old_divisor &&

+				apic->lapic_timer.period) {

+			hrtimer_cancel(&apic->lapic_timer.timer);

+			update_target_expiration(apic, old_divisor);

+			restart_apic_timer(apic);

+		}

 		break;

-

+	}

 	case APIC_ESR:

 		if (apic_x2apic_mode(apic) && val != 0) {

 			apic_debug("KVM_WRITE:ESR not zero %x\n", val);