From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>

Date: Thu, 24 Jun 2021 19:14:17 +0200

Subject: PCI: Call Max Payload Size-related fixup quirks early

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Git-commit: b8da302e2955fe4d41eb9d48199242674d77dbe0

Patch-mainline: 5.15-rc1

References: git-fixes

pci_device_add() calls HEADER fixups after pci_configure_device(), which

configures Max Payload Size.

Convert MPS-related fixups to EARLY fixups so pci_configure_mps() takes

them into account.

Fixes: 27d868b5e6cfa ("PCI: Set MPS to match upstream bridge")

Link: https://lore.kernel.org/r/20210624171418.27194-1-kabel@kernel.org

Signed-off-by: Marek Behún <kabel@kernel.org>

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Cc: stable@vger.kernel.org

Signed-off-by: Jiri Slaby <jslaby@suse.cz>

---

 drivers/pci/quirks.c |   12 ++++++------

 1 file changed, 6 insertions(+), 6 deletions(-)

--- a/drivers/pci/quirks.c

+++ b/drivers/pci/quirks.c

@@ -3061,12 +3061,12 @@ static void fixup_mpss_256(struct pci_de

 {

 	dev->pcie_mpss = 1; /* 256 bytes */

 }

-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,

-			 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);

-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,

-			 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);

-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,

-			 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);

+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,

+			PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);

+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,

+			PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);

+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,

+			PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);

 /* Intel 5000 and 5100 Memory controllers have an errata with read completion

  * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.