From 6fe6ece398f7431784847e922a2c8c385dc58a35 Mon Sep 17 00:00:00 2001

From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <mdaenzer@redhat.com>

Date: Wed, 21 Dec 2022 16:24:13 +0100

Subject: Revert "drm/amd/display: Enable Freesync Video Mode by default"

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Git-commit: 6fe6ece398f7431784847e922a2c8c385dc58a35

Patch-mainline: v6.2-rc3

References: git-fixes

This reverts commit de05abe6b9d0fe08f65d744f7f75a4cba4df27ad.

The bug referenced below was bisected to this commit. There has been no

activity toward fixing it in 3 months, so let's revert for now.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2162

Signed-off-by: Michel Dänzer <mdaenzer@redhat.com>

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Cc: stable@vger.kernel.org

Acked-by: Patrik Jakobsson <pjakobsson@suse.de>

---

 drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  1 +

 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c       | 27 +++++++++++++++++++

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +++++----

 3 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

index 6b74df446694..e3e2e6e3b485 100644

--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h

+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

@@ -195,6 +195,7 @@ extern int amdgpu_emu_mode;

 extern uint amdgpu_smu_memory_pool_size;

 extern int amdgpu_smu_pptable_id;

 extern uint amdgpu_dc_feature_mask;

+extern uint amdgpu_freesync_vid_mode;

 extern uint amdgpu_dc_debug_mask;

 extern uint amdgpu_dc_visual_confirm;

 extern uint amdgpu_dm_abm_level;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

index b4f2d61ea0d5..1353ffd08988 100644

--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

@@ -181,6 +181,7 @@ int amdgpu_mes_kiq;

 int amdgpu_noretry = -1;

 int amdgpu_force_asic_type = -1;

 int amdgpu_tmz = -1; /* auto */

+uint amdgpu_freesync_vid_mode;

 int amdgpu_reset_method = -1; /* auto */

 int amdgpu_num_kcq = -1;

 int amdgpu_smartshift_bias;

@@ -879,6 +880,32 @@ module_param_named(backlight, amdgpu_backlight, bint, 0444);

 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");

 module_param_named(tmz, amdgpu_tmz, int, 0444);

+/**

+ * DOC: freesync_video (uint)

+ * Enable the optimization to adjust front porch timing to achieve seamless

+ * mode change experience when setting a freesync supported mode for which full

+ * modeset is not needed.

+ *

+ * The Display Core will add a set of modes derived from the base FreeSync

+ * video mode into the corresponding connector's mode list based on commonly

+ * used refresh rates and VRR range of the connected display, when users enable

+ * this feature. From the userspace perspective, they can see a seamless mode

+ * change experience when the change between different refresh rates under the

+ * same resolution. Additionally, userspace applications such as Video playback

+ * can read this modeset list and change the refresh rate based on the video

+ * frame rate. Finally, the userspace can also derive an appropriate mode for a

+ * particular refresh rate based on the FreeSync Mode and add it to the

+ * connector's mode list.

+ *

+ * Note: This is an experimental feature.

+ *

+ * The default value: 0 (off).

+ */

+MODULE_PARM_DESC(

+	freesync_video,

+	"Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");

+module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);

+

 /**

  * DOC: reset_method (int)

  * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

index 86bc23a67d97..1b7f20a9d4ae 100644

--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

@@ -5835,7 +5835,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,

 		 */

 		DRM_DEBUG_DRIVER("No preferred mode found\n");

 	} else {

-		recalculate_timing = is_freesync_video_mode(&mode, aconnector);

+		recalculate_timing = amdgpu_freesync_vid_mode &&

+				 is_freesync_video_mode(&mode, aconnector);

 		if (recalculate_timing) {

 			freesync_mode = get_highest_refresh_rate_mode(aconnector, false);

 			drm_mode_copy(&saved_mode, &mode);

@@ -6986,7 +6987,7 @@ static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connect

 	struct amdgpu_dm_connector *amdgpu_dm_connector =

 		to_amdgpu_dm_connector(connector);

-	if (!edid)

+	if (!(amdgpu_freesync_vid_mode && edid))

 		return;

 	if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)

@@ -8850,7 +8851,8 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,

 		 * TODO: Refactor this function to allow this check to work

 		 * in all conditions.

 		 */

-		if (dm_new_crtc_state->stream &&

+		if (amdgpu_freesync_vid_mode &&

+		    dm_new_crtc_state->stream &&

 		    is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))

 			goto skip_modeset;

@@ -8885,7 +8887,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,

 		if (!dm_old_crtc_state->stream)

 			goto skip_modeset;

-		if (dm_new_crtc_state->stream &&

+		if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&

 		    is_timing_unchanged_for_freesync(new_crtc_state,

 						     old_crtc_state)) {

 			new_crtc_state->mode_changed = false;

@@ -8897,7 +8899,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,

 			set_freesync_fixed_config(dm_new_crtc_state);

 			goto skip_modeset;

-		} else if (aconnector &&

+		} else if (amdgpu_freesync_vid_mode && aconnector &&

 			   is_freesync_video_mode(&new_crtc_state->mode,

 						  aconnector)) {

 			struct drm_display_mode *high_mode;

-- 

2.39.0