Ivan T. Ivanov 02dab8
From: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Ivan T. Ivanov 02dab8
Date: Mon, 8 Apr 2019 18:17:19 +0100
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Subject: arm64: Save and restore OSDLR_EL1 across suspend/resume
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Git-commit: 827a108e354db633698f0b4a10c1ffd2b1f8d1d0
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Patch-mainline: v5.2-rc1
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References: git-fixes
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When the CPU comes out of suspend, the firmware may have modified the OS
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Double Lock Register. Save it in an unused slot of cpu_suspend_ctx, and
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restore it on resume.
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Cc: <stable@vger.kernel.org>
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Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
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Signed-off-by: Will Deacon <will.deacon@arm.com>
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Acked-by: Ivan T. Ivanov <iivanov@suse.de>
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---
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 arch/arm64/mm/proc.S |   34 ++++++++++++++++++----------------
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 1 file changed, 18 insertions(+), 16 deletions(-)
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--- a/arch/arm64/mm/proc.S
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+++ b/arch/arm64/mm/proc.S
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@@ -64,24 +64,25 @@ ENTRY(cpu_do_suspend)
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 	mrs	x2, tpidr_el0
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 	mrs	x3, tpidrro_el0
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 	mrs	x4, contextidr_el1
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-	mrs	x5, cpacr_el1
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-	mrs	x6, tcr_el1
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-	mrs	x7, vbar_el1
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-	mrs	x8, mdscr_el1
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-	mrs	x9, oslsr_el1
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-	mrs	x10, sctlr_el1
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+	mrs	x5, osdlr_el1
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+	mrs	x6, cpacr_el1
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+	mrs	x7, tcr_el1
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+	mrs	x8, vbar_el1
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+	mrs	x9, mdscr_el1
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+	mrs	x10, oslsr_el1
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+	mrs	x11, sctlr_el1
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 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
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-	mrs	x11, tpidr_el1
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+	mrs	x12, tpidr_el1
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 alternative_else
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-	mrs	x11, tpidr_el2
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+	mrs	x12, tpidr_el2
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 alternative_endif
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-	mrs	x12, sp_el0
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+	mrs	x13, sp_el0
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 	stp	x2, x3, [x0]
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-	stp	x4, xzr, [x0, #16]
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-	stp	x5, x6, [x0, #32]
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-	stp	x7, x8, [x0, #48]
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-	stp	x9, x10, [x0, #64]
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-	stp	x11, x12, [x0, #80]
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+	stp	x4, x5, [x0, #16]
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+	stp	x6, x7, [x0, #32]
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+	stp	x8, x9, [x0, #48]
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+	stp	x10, x11, [x0, #64]
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+	stp	x12, x13, [x0, #80]
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 	ret
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 ENDPROC(cpu_do_suspend)
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@@ -104,8 +105,8 @@ ENTRY(cpu_do_resume)
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 	msr	cpacr_el1, x6
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 	/* Don't change t0sz here, mask those bits when restoring */
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-	mrs	x5, tcr_el1
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-	bfi	x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
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+	mrs	x7, tcr_el1
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+	bfi	x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
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 	msr	tcr_el1, x8
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 	msr	vbar_el1, x9
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@@ -129,6 +130,7 @@ alternative_endif
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 	/*
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 	 * Restore oslsr_el1 by writing oslar_el1
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 	 */
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+	msr	osdlr_el1, x5
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 	ubfx	x11, x11, #1, #1
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 	msr	oslar_el1, x11
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 	reset_pmuserenr_el0 x0			// Disable PMU access from EL0