From 3c742088686ce922704aec5b11d09bcc5a396589 Mon Sep 17 00:00:00 2001

From: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Date: Fri, 30 Sep 2022 01:53:56 +0300

Subject: [PATCH] clk: baikal-t1: Fix invalid xGMAC PTP clock divider

Git-commit: 3c742088686ce922704aec5b11d09bcc5a396589

Patch-mainline: v6.1-rc1

References: git-fixes

Most likely due to copy-paste mistake the divider has been set to 10 while

according to the SoC reference manual it's supposed to be 8 thus having

PTP clock frequency of 156.25 MHz.

Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver")

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>

Link: https://lore.kernel.org/r/20220929225402.9696-3-Sergey.Semin@baikalelectronics.ru

Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Acked-by: Takashi Iwai <tiwai@suse.de>

---

 drivers/clk/baikal-t1/clk-ccu-div.c | 2 +-

 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c

index f141fda12b09..ea77eec40ddd 100644

--- a/drivers/clk/baikal-t1/clk-ccu-div.c

+++ b/drivers/clk/baikal-t1/clk-ccu-div.c

@@ -207,7 +207,7 @@ static const struct ccu_div_info sys_info[] = {

 	CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",

 			  "eth_clk", CCU_SYS_XGMAC_BASE, 8),

 	CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",

-			   "eth_clk", 10),

+			   "eth_clk", 8),

 	CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",

 			  "eth_clk", CCU_SYS_USB_BASE, 10),

 	CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",

-- 

2.35.3