From 4a8a77abf0e2b6468ba0281e33384cbec5fb476a Mon Sep 17 00:00:00 2001

From: Luca Weiss <luca@z3ntu.xyz>

Date: Sun, 30 Jan 2022 12:45:35 +0100

Subject: [PATCH] cpufreq: qcom-cpufreq-nvmem: fix reading of PVS Valid fuse

Git-commit: 4a8a77abf0e2b6468ba0281e33384cbec5fb476a

Patch-mainline: v5.18-rc1

References: git-fixes

The fuse consists of 64 bits, with this statement we're supposed to get

the upper 32 bits but it actually read out of bounds and got 0 instead

of the desired value which lead to the "PVS bin not set." codepath being

run resetting our pvs value.

Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs")

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>

Acked-by: Takashi Iwai <tiwai@suse.de>

---

 drivers/cpufreq/qcom-cpufreq-nvmem.c | 2 +-

 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c

index d1744b5d9619..6dfa86971a75 100644

--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c

+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c

@@ -130,7 +130,7 @@ static void get_krait_bin_format_b(struct device *cpu_dev,

 	}

 	/* Check PVS_BLOW_STATUS */

-	pte_efuse = *(((u32 *)buf) + 4);

+	pte_efuse = *(((u32 *)buf) + 1);

 	pte_efuse &= BIT(21);

 	if (pte_efuse) {

 		dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);

-- 

2.31.1