From 9baf2de7ee4eeaca5cf95d1a399182ab83aa42b8 Mon Sep 17 00:00:00 2001

From: Marco Chiappero <marco.chiappero@intel.com>

Date: Wed, 17 Nov 2021 14:30:48 +0000

Subject: [PATCH] crypto: qat - differentiate between pf2vf and vf2pf offset

Git-commit: 9baf2de7ee4eeaca5cf95d1a399182ab83aa42b8

Patch-mainline: v5.17-rc1

References: jsc#PED-1073

Add the function get_vf2pf_offset() to adf_pfvf_ops to differentiate the

CSRs used for pf2vf and vf2pf.

Offsets may or may not be direction specific depending on QAT

generation. Since in QAT GEN2 the CSR is not direction specific, i.e.

there is a single mailbox register shared for pf2vf and vf2pf, both

get_vf2pf_offset() and get_vf2pf_offset() will return the same offset.

This change is to make the direction explicit, so it is easier to

understand and debug and also in preparation for the introduction of

PFVF support in the qat_4xxx driver since QAT GEN4 devices have a

separate CSR for pf2vf and vf2pf communications.

Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>

Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>

Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>

Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Torsten Duwe <duwe@suse.de>

---

 drivers/crypto/qat/qat_common/adf_accel_devices.h |  1 +

 drivers/crypto/qat/qat_common/adf_gen2_pfvf.c     | 10 ++++++----

 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c     |  6 +++---

 3 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/crypto/qat/qat_common/adf_accel_devices.h b/drivers/crypto/qat/qat_common/adf_accel_devices.h

index a1baa65bd0342..d9b2cc935b616 100644

--- a/drivers/crypto/qat/qat_common/adf_accel_devices.h

+++ b/drivers/crypto/qat/qat_common/adf_accel_devices.h

@@ -150,6 +150,7 @@ struct adf_etr_ring_data;

 struct adf_pfvf_ops {

 	int (*enable_comms)(struct adf_accel_dev *accel_dev);

 	u32 (*get_pf2vf_offset)(u32 i);

+	u32 (*get_vf2pf_offset)(u32 i);

 	u32 (*get_vf2pf_sources)(void __iomem *pmisc_addr);

 	void (*enable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);

 	void (*disable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);

diff --git a/drivers/crypto/qat/qat_common/adf_gen2_pfvf.c b/drivers/crypto/qat/qat_common/adf_gen2_pfvf.c

index 36c8ff0096612..2f27146bb7c6e 100644

--- a/drivers/crypto/qat/qat_common/adf_gen2_pfvf.c

+++ b/drivers/crypto/qat/qat_common/adf_gen2_pfvf.c

@@ -12,12 +12,12 @@

 #define ADF_GEN2_PF_PF2VF_OFFSET(i)	(0x3A000 + 0x280 + ((i) * 0x04))

 #define ADF_GEN2_VF_PF2VF_OFFSET	0x200

-static u32 adf_gen2_pf_get_pf2vf_offset(u32 i)

+static u32 adf_gen2_pf_get_pfvf_offset(u32 i)

 {

 	return ADF_GEN2_PF_PF2VF_OFFSET(i);

 }

-static u32 adf_gen2_vf_get_pf2vf_offset(u32 i)

+static u32 adf_gen2_vf_get_pfvf_offset(u32 i)

 {

 	return ADF_GEN2_VF_PF2VF_OFFSET;

 }

@@ -64,7 +64,8 @@ static void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr,

 void adf_gen2_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops)

 {

 	pfvf_ops->enable_comms = adf_enable_pf2vf_comms;

-	pfvf_ops->get_pf2vf_offset = adf_gen2_pf_get_pf2vf_offset;

+	pfvf_ops->get_pf2vf_offset = adf_gen2_pf_get_pfvf_offset;

+	pfvf_ops->get_vf2pf_offset = adf_gen2_pf_get_pfvf_offset;

 	pfvf_ops->get_vf2pf_sources = adf_gen2_get_vf2pf_sources;

 	pfvf_ops->enable_vf2pf_interrupts = adf_gen2_enable_vf2pf_interrupts;

 	pfvf_ops->disable_vf2pf_interrupts = adf_gen2_disable_vf2pf_interrupts;

@@ -74,6 +75,7 @@ EXPORT_SYMBOL_GPL(adf_gen2_init_pf_pfvf_ops);

 void adf_gen2_init_vf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops)

 {

 	pfvf_ops->enable_comms = adf_enable_vf2pf_comms;

-	pfvf_ops->get_pf2vf_offset = adf_gen2_vf_get_pf2vf_offset;

+	pfvf_ops->get_pf2vf_offset = adf_gen2_vf_get_pfvf_offset;

+	pfvf_ops->get_vf2pf_offset = adf_gen2_vf_get_pfvf_offset;

 }

 EXPORT_SYMBOL_GPL(adf_gen2_init_vf_pfvf_ops);

diff --git a/drivers/crypto/qat/qat_common/adf_pf2vf_msg.c b/drivers/crypto/qat/qat_common/adf_pf2vf_msg.c

index 78dc8aea48667..c420ec03081b4 100644

--- a/drivers/crypto/qat/qat_common/adf_pf2vf_msg.c

+++ b/drivers/crypto/qat/qat_common/adf_pf2vf_msg.c

@@ -29,7 +29,7 @@ static int adf_iov_putmsg(struct adf_accel_dev *accel_dev, u32 msg, u8 vf_nr)

 	int ret;

 	if (accel_dev->is_vf) {

-		pf2vf_offset = hw_data->pfvf_ops.get_pf2vf_offset(0);

+		pf2vf_offset = hw_data->pfvf_ops.get_vf2pf_offset(0);

 		lock = &accel_dev->vf.vf2pf_lock;

 		local_in_use_mask = ADF_VF2PF_IN_USE_BY_VF_MASK;

 		local_in_use_pattern = ADF_VF2PF_IN_USE_BY_VF;

@@ -258,7 +258,7 @@ bool adf_recv_and_handle_vf2pf_msg(struct adf_accel_dev *accel_dev, u32 vf_nr)

 	u32 msg, resp = 0;

 	/* Read message from the VF */

-	msg = ADF_CSR_RD(pmisc_addr, hw_data->pfvf_ops.get_pf2vf_offset(vf_nr));

+	msg = ADF_CSR_RD(pmisc_addr, hw_data->pfvf_ops.get_vf2pf_offset(vf_nr));

 	if (!(msg & ADF_VF2PF_INT)) {

 		dev_info(&GET_DEV(accel_dev),

 			 "Spurious VF2PF interrupt, msg %X. Ignored\n", msg);

@@ -275,7 +275,7 @@ bool adf_recv_and_handle_vf2pf_msg(struct adf_accel_dev *accel_dev, u32 vf_nr)

 	/* To ACK, clear the VF2PFINT bit */

 	msg &= ~ADF_VF2PF_INT;

-	ADF_CSR_WR(pmisc_addr, hw_data->pfvf_ops.get_pf2vf_offset(vf_nr), msg);

+	ADF_CSR_WR(pmisc_addr, hw_data->pfvf_ops.get_vf2pf_offset(vf_nr), msg);

 	if (adf_handle_vf2pf_msg(accel_dev, vf_nr, msg, &resp))

 		return false;

-- 

2.35.3