From 642a7d49c249f04007e68c124a148847471dd476 Mon Sep 17 00:00:00 2001

From: Giovanni Cabiddu <giovanni.cabiddu@intel.com>

Date: Tue, 18 Jan 2022 10:35:15 +0000

Subject: [PATCH] crypto: qat - fix access to PFVF interrupt registers for GEN4

Git-commit: 642a7d49c249f04007e68c124a148847471dd476

Patch-mainline: v5.18-rc1

References: jsc#PED-1073

The logic that detects, enables and disables pfvf interrupts was

expecting a single CSR per VF. Instead, the source and mask register are

two registers with a bit per VF.

Due to this, the driver is reading and setting reserved CSRs and not

masking the correct source of interrupts.

Fix the access to the source and mask register for QAT GEN4 devices by

removing the outer loop in adf_gen4_get_vf2pf_sources(),

adf_gen4_enable_vf2pf_interrupts() and

adf_gen4_disable_vf2pf_interrupts() and changing the helper macros

ADF_4XXX_VM2PF_SOU and ADF_4XXX_VM2PF_MSK.

Fixes: a9dc0d966605 ("crypto: qat - add PFVF support to the GEN4 host driver")

Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>

Co-developed-by: Siming Wan <siming.wan@intel.com>

Signed-off-by: Siming Wan <siming.wan@intel.com>

Reviewed-by: Xin Zeng <xin.zeng@intel.com>

Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com>

Reviewed-by: Marco Chiappero <marco.chiappero@intel.com>

Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Torsten Duwe <duwe@suse.de>

---

 drivers/crypto/qat/qat_common/adf_gen4_pfvf.c | 42 ++++---------------

 1 file changed, 9 insertions(+), 33 deletions(-)

diff --git a/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c b/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c

index 8efbedf63bc80..3b3ea849c5e53 100644

--- a/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c

+++ b/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c

@@ -9,15 +9,12 @@

 #include "adf_pfvf_pf_proto.h"

 #include "adf_pfvf_utils.h"

-#define ADF_4XXX_MAX_NUM_VFS		16

-

 #define ADF_4XXX_PF2VM_OFFSET(i)	(0x40B010 + ((i) * 0x20))

 #define ADF_4XXX_VM2PF_OFFSET(i)	(0x40B014 + ((i) * 0x20))

 /* VF2PF interrupt source registers */

-#define ADF_4XXX_VM2PF_SOU(i)		(0x41A180 + ((i) * 4))

-#define ADF_4XXX_VM2PF_MSK(i)		(0x41A1C0 + ((i) * 4))

-#define ADF_4XXX_VM2PF_INT_EN_MSK	BIT(0)

+#define ADF_4XXX_VM2PF_SOU		0x41A180

+#define ADF_4XXX_VM2PF_MSK		0x41A1C0

 #define ADF_PFVF_GEN4_MSGTYPE_SHIFT	2

 #define ADF_PFVF_GEN4_MSGTYPE_MASK	0x3F

@@ -41,51 +38,30 @@ static u32 adf_gen4_pf_get_vf2pf_offset(u32 i)

 static u32 adf_gen4_get_vf2pf_sources(void __iomem *pmisc_addr)

 {

-	int i;

 	u32 sou, mask;

-	int num_csrs = ADF_4XXX_MAX_NUM_VFS;

-	u32 vf_mask = 0;

-	for (i = 0; i < num_csrs; i++) {

-		sou = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_SOU(i));

-		mask = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK(i));

-		sou &= ~mask;

-		vf_mask |= sou << i;

-	}

+	sou = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_SOU);

+	mask = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK);

-	return vf_mask;

+	return sou &= ~mask;

 }

 static void adf_gen4_enable_vf2pf_interrupts(void __iomem *pmisc_addr,

 					     u32 vf_mask)

 {

-	int num_csrs = ADF_4XXX_MAX_NUM_VFS;

-	unsigned long mask = vf_mask;

 	unsigned int val;

-	int i;

-

-	for_each_set_bit(i, &mask, num_csrs) {

-		unsigned int offset = ADF_4XXX_VM2PF_MSK(i);

-		val = ADF_CSR_RD(pmisc_addr, offset) & ~ADF_4XXX_VM2PF_INT_EN_MSK;

-		ADF_CSR_WR(pmisc_addr, offset, val);

-	}

+	val = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK) & ~vf_mask;

+	ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, val);

 }

 static void adf_gen4_disable_vf2pf_interrupts(void __iomem *pmisc_addr,

 					      u32 vf_mask)

 {

-	int num_csrs = ADF_4XXX_MAX_NUM_VFS;

-	unsigned long mask = vf_mask;

 	unsigned int val;

-	int i;

-

-	for_each_set_bit(i, &mask, num_csrs) {

-		unsigned int offset = ADF_4XXX_VM2PF_MSK(i);

-		val = ADF_CSR_RD(pmisc_addr, offset) | ADF_4XXX_VM2PF_INT_EN_MSK;

-		ADF_CSR_WR(pmisc_addr, offset, val);

-	}

+	val = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK) | vf_mask;

+	ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, val);

 }

 static int adf_gen4_pfvf_send(struct adf_accel_dev *accel_dev,

-- 

2.35.3