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From 993161d36ab5f0f8064751f157482d332a8fcf2c Mon Sep 17 00:00:00 2001
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From: Marco Chiappero <marco.chiappero@intel.com>
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Date: Tue, 28 Sep 2021 12:44:32 +0100
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Subject: [PATCH] crypto: qat - fix handling of VF to PF interrupts
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Git-commit: 993161d36ab5f0f8064751f157482d332a8fcf2c
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Patch-mainline: v5.16-rc1
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References: jsc#PED-1073
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Currently, VF to PF interrupt handling is based on the DH895XCC device
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behavior, which is not entirely common to all devices.
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In order to make interrupt detection and handling correct for all of the
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supported devices, make the interrupt handling device specific by:
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- introducing get_vf2pf_sources() for getting a 32 bits long value
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where each bit represents a vf2pf interrupt;
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- adding the device [enable|disable]_vf2pf_interrupts to hw_data;
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- defining [enable|disable]_vf2pf_interrupts for all the devices that
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are currently supported, using only their required and specific
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ERRSOU|ERRMASK registers (DH895XCC has 32 interrupts spread across
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ERRSOU3 and ERRSOU5, C62X/C3XXX has 16 in ERRSOU3 only, etc).
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Code has been shared by different devices wherever possible.
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This patch is based on earlier work done by Salvatore Benedetto.
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Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
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Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
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Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
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Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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Signed-off-by: Torsten Duwe <duwe@suse.de>
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---
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.../crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c | 3 +
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.../crypto/qat/qat_c62x/adf_c62x_hw_data.c | 3 +
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.../crypto/qat/qat_common/adf_accel_devices.h | 5 ++
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.../crypto/qat/qat_common/adf_gen2_hw_data.c | 40 +++++++++++
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.../crypto/qat/qat_common/adf_gen2_hw_data.h | 12 ++++
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drivers/crypto/qat/qat_common/adf_isr.c | 20 +-----
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drivers/crypto/qat/qat_common/adf_pf2vf_msg.c | 72 +++++--------------
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.../qat/qat_dh895xcc/adf_dh895xcc_hw_data.c | 49 +++++++++++++
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.../qat/qat_dh895xcc/adf_dh895xcc_hw_data.h | 5 +-
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9 files changed, 133 insertions(+), 76 deletions(-)
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diff --git a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
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index 3027c01bc89e2..b9bd52eaa1848 100644
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--- a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
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+++ b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
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@@ -206,6 +206,9 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
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hw_data->reset_device = adf_reset_flr;
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hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
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hw_data->get_pf2vf_offset = get_pf2vf_offset;
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+ hw_data->get_vf2pf_sources = adf_gen2_get_vf2pf_sources;
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+ hw_data->enable_vf2pf_interrupts = adf_gen2_enable_vf2pf_interrupts;
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+ hw_data->disable_vf2pf_interrupts = adf_gen2_disable_vf2pf_interrupts;
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hw_data->enable_pfvf_comms = adf_enable_pf2vf_comms;
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hw_data->disable_iov = adf_disable_sriov;
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hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
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diff --git a/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c b/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
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index b023c80873bb5..f28dae0982bc1 100644
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--- a/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
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+++ b/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
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@@ -208,6 +208,9 @@ void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
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hw_data->reset_device = adf_reset_flr;
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hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
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hw_data->get_pf2vf_offset = get_pf2vf_offset;
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+ hw_data->get_vf2pf_sources = adf_gen2_get_vf2pf_sources;
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+ hw_data->enable_vf2pf_interrupts = adf_gen2_enable_vf2pf_interrupts;
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+ hw_data->disable_vf2pf_interrupts = adf_gen2_disable_vf2pf_interrupts;
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hw_data->enable_pfvf_comms = adf_enable_pf2vf_comms;
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hw_data->disable_iov = adf_disable_sriov;
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hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
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diff --git a/drivers/crypto/qat/qat_common/adf_accel_devices.h b/drivers/crypto/qat/qat_common/adf_accel_devices.h
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index ca8e23f0bcc47..57d9ca08e6115 100644
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--- a/drivers/crypto/qat/qat_common/adf_accel_devices.h
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+++ b/drivers/crypto/qat/qat_common/adf_accel_devices.h
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@@ -177,6 +177,11 @@ struct adf_hw_device_data {
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void (*enable_ints)(struct adf_accel_dev *accel_dev);
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void (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev);
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int (*enable_pfvf_comms)(struct adf_accel_dev *accel_dev);
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+ u32 (*get_vf2pf_sources)(void __iomem *pmisc_addr);
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+ void (*enable_vf2pf_interrupts)(void __iomem *pmisc_bar_addr,
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+ u32 vf_mask);
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+ void (*disable_vf2pf_interrupts)(void __iomem *pmisc_bar_addr,
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+ u32 vf_mask);
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void (*reset_device)(struct adf_accel_dev *accel_dev);
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void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
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char *(*uof_get_name)(u32 obj_num);
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diff --git a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
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index 9e560c7d41630..5669180127782 100644
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--- a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
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+++ b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.c
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@@ -4,6 +4,46 @@
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#include "icp_qat_hw.h"
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#include <linux/pci.h>
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+u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_addr)
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+{
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+ u32 errsou3, errmsk3, vf_int_mask;
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+
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+ /* Get the interrupt sources triggered by VFs */
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+ errsou3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRSOU3);
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+ vf_int_mask = ADF_GEN2_ERR_REG_VF2PF(errsou3);
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+
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+ /* To avoid adding duplicate entries to work queue, clear
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+ * vf_int_mask_sets bits that are already masked in ERRMSK register.
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+ */
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+ errmsk3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3);
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+ vf_int_mask &= ~ADF_GEN2_ERR_REG_VF2PF(errmsk3);
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+
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+ return vf_int_mask;
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+}
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+EXPORT_SYMBOL_GPL(adf_gen2_get_vf2pf_sources);
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+
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+void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
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+{
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+ /* Enable VF2PF Messaging Ints - VFs 0 through 15 per vf_mask[15:0] */
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+ if (vf_mask & 0xFFFF) {
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+ u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)
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+ & ~ADF_GEN2_ERR_MSK_VF2PF(vf_mask);
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+ ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);
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+ }
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+}
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+EXPORT_SYMBOL_GPL(adf_gen2_enable_vf2pf_interrupts);
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+
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+void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
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+{
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+ /* Disable VF2PF interrupts for VFs 0 through 15 per vf_mask[15:0] */
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+ if (vf_mask & 0xFFFF) {
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+ u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)
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+ | ADF_GEN2_ERR_MSK_VF2PF(vf_mask);
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+ ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);
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+ }
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+}
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+EXPORT_SYMBOL_GPL(adf_gen2_disable_vf2pf_interrupts);
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+
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void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,
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int num_a_regs, int num_b_regs)
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{
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diff --git a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
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index 756b0ddfac5e1..3486e51aad75b 100644
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--- a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
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+++ b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
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@@ -125,6 +125,18 @@ do { \
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#define ADF_SSMWDT(i) (ADF_SSMWDT_OFFSET + ((i) * 0x4000))
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#define ADF_SSMWDTPKE(i) (ADF_SSMWDTPKE_OFFSET + ((i) * 0x4000))
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+ /* VF2PF interrupts */
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+#define ADF_GEN2_ERRSOU3 (0x3A000 + 0x0C)
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+#define ADF_GEN2_ERRSOU5 (0x3A000 + 0xD8)
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+#define ADF_GEN2_ERRMSK3 (0x3A000 + 0x1C)
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+#define ADF_GEN2_ERRMSK5 (0x3A000 + 0xDC)
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+#define ADF_GEN2_ERR_REG_VF2PF(vf_src) (((vf_src) & 0x01FFFE00) >> 9)
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+#define ADF_GEN2_ERR_MSK_VF2PF(vf_mask) (((vf_mask) & 0xFFFF) << 9)
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+
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+u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_bar);
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+void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask);
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+void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask);
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+
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void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,
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int num_a_regs, int num_b_regs);
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void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
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diff --git a/drivers/crypto/qat/qat_common/adf_isr.c b/drivers/crypto/qat/qat_common/adf_isr.c
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index c55a9f14b0d23..40593c9449a20 100644
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--- a/drivers/crypto/qat/qat_common/adf_isr.c
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+++ b/drivers/crypto/qat/qat_common/adf_isr.c
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@@ -16,12 +16,6 @@
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#include "adf_transport_internal.h"
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#define ADF_MAX_NUM_VFS 32
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-#define ADF_ERRSOU3 (0x3A000 + 0x0C)
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-#define ADF_ERRSOU5 (0x3A000 + 0xD8)
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-#define ADF_ERRMSK3 (0x3A000 + 0x1C)
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-#define ADF_ERRMSK5 (0x3A000 + 0xDC)
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-#define ADF_ERR_REG_VF2PF_L(vf_src) (((vf_src) & 0x01FFFE00) >> 9)
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-#define ADF_ERR_REG_VF2PF_U(vf_src) (((vf_src) & 0x0000FFFF) << 16)
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static int adf_enable_msix(struct adf_accel_dev *accel_dev)
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{
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@@ -71,22 +65,10 @@ static irqreturn_t adf_msix_isr_ae(int irq, void *dev_ptr)
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struct adf_bar *pmisc =
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&GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];
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void __iomem *pmisc_addr = pmisc->virt_addr;
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- u32 errsou3, errsou5, errmsk3, errmsk5;
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unsigned long vf_mask;
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/* Get the interrupt sources triggered by VFs */
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- errsou3 = ADF_CSR_RD(pmisc_addr, ADF_ERRSOU3);
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- errsou5 = ADF_CSR_RD(pmisc_addr, ADF_ERRSOU5);
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- vf_mask = ADF_ERR_REG_VF2PF_L(errsou3);
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- vf_mask |= ADF_ERR_REG_VF2PF_U(errsou5);
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-
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- /* To avoid adding duplicate entries to work queue, clear
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- * vf_int_mask_sets bits that are already masked in ERRMSK register.
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- */
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- errmsk3 = ADF_CSR_RD(pmisc_addr, ADF_ERRMSK3);
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- errmsk5 = ADF_CSR_RD(pmisc_addr, ADF_ERRMSK5);
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- vf_mask &= ~ADF_ERR_REG_VF2PF_L(errmsk3);
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Torsten Duwe |
ad3f61 |
- vf_mask &= ~ADF_ERR_REG_VF2PF_U(errmsk5);
|
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Torsten Duwe |
ad3f61 |
+ vf_mask = hw_data->get_vf2pf_sources(pmisc_addr);
|
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Torsten Duwe |
ad3f61 |
|
|
Torsten Duwe |
ad3f61 |
if (vf_mask) {
|
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Torsten Duwe |
ad3f61 |
struct adf_accel_vf_info *vf_info;
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Torsten Duwe |
ad3f61 |
diff --git a/drivers/crypto/qat/qat_common/adf_pf2vf_msg.c b/drivers/crypto/qat/qat_common/adf_pf2vf_msg.c
|
|
Torsten Duwe |
ad3f61 |
index d3f6ff68d45d9..cdef6c34524e4 100644
|
|
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ad3f61 |
--- a/drivers/crypto/qat/qat_common/adf_pf2vf_msg.c
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|
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ad3f61 |
+++ b/drivers/crypto/qat/qat_common/adf_pf2vf_msg.c
|
|
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ad3f61 |
@@ -5,82 +5,42 @@
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|
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ad3f61 |
#include "adf_common_drv.h"
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ad3f61 |
#include "adf_pf2vf_msg.h"
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|
Torsten Duwe |
ad3f61 |
|
|
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ad3f61 |
-#define ADF_DH895XCC_EP_OFFSET 0x3A000
|
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ad3f61 |
-#define ADF_DH895XCC_ERRMSK3 (ADF_DH895XCC_EP_OFFSET + 0x1C)
|
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ad3f61 |
-#define ADF_DH895XCC_ERRMSK3_VF2PF_L_MASK(vf_mask) ((vf_mask & 0xFFFF) << 9)
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|
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ad3f61 |
-#define ADF_DH895XCC_ERRMSK5 (ADF_DH895XCC_EP_OFFSET + 0xDC)
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ad3f61 |
-#define ADF_DH895XCC_ERRMSK5_VF2PF_U_MASK(vf_mask) (vf_mask >> 16)
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|
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ad3f61 |
-
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|
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ad3f61 |
-static void __adf_enable_vf2pf_interrupts(struct adf_accel_dev *accel_dev,
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Torsten Duwe |
ad3f61 |
- u32 vf_mask)
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|
Torsten Duwe |
ad3f61 |
+void adf_enable_vf2pf_interrupts(struct adf_accel_dev *accel_dev, u32 vf_mask)
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Torsten Duwe |
ad3f61 |
{
|
|
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ad3f61 |
struct adf_hw_device_data *hw_data = accel_dev->hw_device;
|
|
Torsten Duwe |
ad3f61 |
- struct adf_bar *pmisc =
|
|
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ad3f61 |
- &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];
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ad3f61 |
+ u32 misc_bar_id = hw_data->get_misc_bar_id(hw_data);
|
|
Torsten Duwe |
ad3f61 |
+ struct adf_bar *pmisc = &GET_BARS(accel_dev)[misc_bar_id];
|
|
Torsten Duwe |
ad3f61 |
void __iomem *pmisc_addr = pmisc->virt_addr;
|
|
Torsten Duwe |
ad3f61 |
- u32 reg;
|
|
Torsten Duwe |
ad3f61 |
-
|
|
Torsten Duwe |
ad3f61 |
- /* Enable VF2PF Messaging Ints - VFs 1 through 16 per vf_mask[15:0] */
|
|
Torsten Duwe |
ad3f61 |
- if (vf_mask & 0xFFFF) {
|
|
Torsten Duwe |
ad3f61 |
- reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK3);
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|
Torsten Duwe |
ad3f61 |
- reg &= ~ADF_DH895XCC_ERRMSK3_VF2PF_L_MASK(vf_mask);
|
|
Torsten Duwe |
ad3f61 |
- ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK3, reg);
|
|
Torsten Duwe |
ad3f61 |
- }
|
|
Torsten Duwe |
ad3f61 |
-
|
|
Torsten Duwe |
ad3f61 |
- /* Enable VF2PF Messaging Ints - VFs 17 through 32 per vf_mask[31:16] */
|
|
Torsten Duwe |
ad3f61 |
- if (vf_mask >> 16) {
|
|
Torsten Duwe |
ad3f61 |
- reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK5);
|
|
Torsten Duwe |
ad3f61 |
- reg &= ~ADF_DH895XCC_ERRMSK5_VF2PF_U_MASK(vf_mask);
|
|
Torsten Duwe |
ad3f61 |
- ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK5, reg);
|
|
Torsten Duwe |
ad3f61 |
- }
|
|
Torsten Duwe |
ad3f61 |
-}
|
|
Torsten Duwe |
ad3f61 |
-
|
|
Torsten Duwe |
ad3f61 |
-void adf_enable_vf2pf_interrupts(struct adf_accel_dev *accel_dev, u32 vf_mask)
|
|
Torsten Duwe |
ad3f61 |
-{
|
|
Torsten Duwe |
ad3f61 |
unsigned long flags;
|
|
Torsten Duwe |
ad3f61 |
|
|
Torsten Duwe |
ad3f61 |
spin_lock_irqsave(&accel_dev->pf.vf2pf_ints_lock, flags);
|
|
Torsten Duwe |
ad3f61 |
- __adf_enable_vf2pf_interrupts(accel_dev, vf_mask);
|
|
Torsten Duwe |
ad3f61 |
+ hw_data->enable_vf2pf_interrupts(pmisc_addr, vf_mask);
|
|
Torsten Duwe |
ad3f61 |
spin_unlock_irqrestore(&accel_dev->pf.vf2pf_ints_lock, flags);
|
|
Torsten Duwe |
ad3f61 |
}
|
|
Torsten Duwe |
ad3f61 |
|
|
Torsten Duwe |
ad3f61 |
-static void __adf_disable_vf2pf_interrupts(struct adf_accel_dev *accel_dev,
|
|
Torsten Duwe |
ad3f61 |
- u32 vf_mask)
|
|
Torsten Duwe |
ad3f61 |
+void adf_disable_vf2pf_interrupts(struct adf_accel_dev *accel_dev, u32 vf_mask)
|
|
Torsten Duwe |
ad3f61 |
{
|
|
Torsten Duwe |
ad3f61 |
struct adf_hw_device_data *hw_data = accel_dev->hw_device;
|
|
Torsten Duwe |
ad3f61 |
- struct adf_bar *pmisc =
|
|
Torsten Duwe |
ad3f61 |
- &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];
|
|
Torsten Duwe |
ad3f61 |
+ u32 misc_bar_id = hw_data->get_misc_bar_id(hw_data);
|
|
Torsten Duwe |
ad3f61 |
+ struct adf_bar *pmisc = &GET_BARS(accel_dev)[misc_bar_id];
|
|
Torsten Duwe |
ad3f61 |
void __iomem *pmisc_addr = pmisc->virt_addr;
|
|
Torsten Duwe |
ad3f61 |
- u32 reg;
|
|
Torsten Duwe |
ad3f61 |
-
|
|
Torsten Duwe |
ad3f61 |
- /* Disable VF2PF interrupts for VFs 1 through 16 per vf_mask[15:0] */
|
|
Torsten Duwe |
ad3f61 |
- if (vf_mask & 0xFFFF) {
|
|
Torsten Duwe |
ad3f61 |
- reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK3) |
|
|
Torsten Duwe |
ad3f61 |
- ADF_DH895XCC_ERRMSK3_VF2PF_L_MASK(vf_mask);
|
|
Torsten Duwe |
ad3f61 |
- ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK3, reg);
|
|
Torsten Duwe |
ad3f61 |
- }
|
|
Torsten Duwe |
ad3f61 |
-
|
|
Torsten Duwe |
ad3f61 |
- /* Disable VF2PF interrupts for VFs 17 through 32 per vf_mask[31:16] */
|
|
Torsten Duwe |
ad3f61 |
- if (vf_mask >> 16) {
|
|
Torsten Duwe |
ad3f61 |
- reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK5) |
|
|
Torsten Duwe |
ad3f61 |
- ADF_DH895XCC_ERRMSK5_VF2PF_U_MASK(vf_mask);
|
|
Torsten Duwe |
ad3f61 |
- ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK5, reg);
|
|
Torsten Duwe |
ad3f61 |
- }
|
|
Torsten Duwe |
ad3f61 |
-}
|
|
Torsten Duwe |
ad3f61 |
-
|
|
Torsten Duwe |
ad3f61 |
-void adf_disable_vf2pf_interrupts(struct adf_accel_dev *accel_dev, u32 vf_mask)
|
|
Torsten Duwe |
ad3f61 |
-{
|
|
Torsten Duwe |
ad3f61 |
unsigned long flags;
|
|
Torsten Duwe |
ad3f61 |
|
|
Torsten Duwe |
ad3f61 |
spin_lock_irqsave(&accel_dev->pf.vf2pf_ints_lock, flags);
|
|
Torsten Duwe |
ad3f61 |
- __adf_disable_vf2pf_interrupts(accel_dev, vf_mask);
|
|
Torsten Duwe |
ad3f61 |
+ hw_data->disable_vf2pf_interrupts(pmisc_addr, vf_mask);
|
|
Torsten Duwe |
ad3f61 |
spin_unlock_irqrestore(&accel_dev->pf.vf2pf_ints_lock, flags);
|
|
Torsten Duwe |
ad3f61 |
}
|
|
Torsten Duwe |
ad3f61 |
|
|
Torsten Duwe |
ad3f61 |
-void adf_disable_vf2pf_interrupts_irq(struct adf_accel_dev *accel_dev, u32 vf_mask)
|
|
Torsten Duwe |
ad3f61 |
+void adf_disable_vf2pf_interrupts_irq(struct adf_accel_dev *accel_dev,
|
|
Torsten Duwe |
ad3f61 |
+ u32 vf_mask)
|
|
Torsten Duwe |
ad3f61 |
{
|
|
Torsten Duwe |
ad3f61 |
+ struct adf_hw_device_data *hw_data = accel_dev->hw_device;
|
|
Torsten Duwe |
ad3f61 |
+ u32 misc_bar_id = hw_data->get_misc_bar_id(hw_data);
|
|
Torsten Duwe |
ad3f61 |
+ struct adf_bar *pmisc = &GET_BARS(accel_dev)[misc_bar_id];
|
|
Torsten Duwe |
ad3f61 |
+ void __iomem *pmisc_addr = pmisc->virt_addr;
|
|
Torsten Duwe |
ad3f61 |
+
|
|
Torsten Duwe |
ad3f61 |
spin_lock(&accel_dev->pf.vf2pf_ints_lock);
|
|
Torsten Duwe |
ad3f61 |
- __adf_disable_vf2pf_interrupts(accel_dev, vf_mask);
|
|
Torsten Duwe |
ad3f61 |
+ hw_data->disable_vf2pf_interrupts(pmisc_addr, vf_mask);
|
|
Torsten Duwe |
ad3f61 |
spin_unlock(&accel_dev->pf.vf2pf_ints_lock);
|
|
Torsten Duwe |
ad3f61 |
}
|
|
Torsten Duwe |
ad3f61 |
|
|
Torsten Duwe |
ad3f61 |
diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
|
|
Torsten Duwe |
ad3f61 |
index 0a9ce365a544e..b496032c992b5 100644
|
|
Torsten Duwe |
ad3f61 |
--- a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
|
|
Torsten Duwe |
ad3f61 |
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
|
|
Torsten Duwe |
ad3f61 |
@@ -175,6 +175,52 @@ static void adf_enable_ints(struct adf_accel_dev *accel_dev)
|
|
Torsten Duwe |
ad3f61 |
ADF_DH895XCC_SMIA1_MASK);
|
|
Torsten Duwe |
ad3f61 |
}
|
|
Torsten Duwe |
ad3f61 |
|
|
Torsten Duwe |
ad3f61 |
+static u32 get_vf2pf_sources(void __iomem *pmisc_bar)
|
|
Torsten Duwe |
ad3f61 |
+{
|
|
Torsten Duwe |
ad3f61 |
+ u32 errsou5, errmsk5, vf_int_mask;
|
|
Torsten Duwe |
ad3f61 |
+
|
|
Torsten Duwe |
ad3f61 |
+ vf_int_mask = adf_gen2_get_vf2pf_sources(pmisc_bar);
|
|
Torsten Duwe |
ad3f61 |
+
|
|
Torsten Duwe |
ad3f61 |
+ /* Get the interrupt sources triggered by VFs, but to avoid duplicates
|
|
Torsten Duwe |
ad3f61 |
+ * in the work queue, clear vf_int_mask_sets bits that are already
|
|
Torsten Duwe |
ad3f61 |
+ * masked in ERRMSK register.
|
|
Torsten Duwe |
ad3f61 |
+ */
|
|
Torsten Duwe |
ad3f61 |
+ errsou5 = ADF_CSR_RD(pmisc_bar, ADF_GEN2_ERRSOU5);
|
|
Torsten Duwe |
ad3f61 |
+ errmsk5 = ADF_CSR_RD(pmisc_bar, ADF_GEN2_ERRMSK5);
|
|
Torsten Duwe |
ad3f61 |
+ vf_int_mask |= ADF_DH895XCC_ERR_REG_VF2PF_U(errsou5);
|
|
Torsten Duwe |
ad3f61 |
+ vf_int_mask &= ~ADF_DH895XCC_ERR_REG_VF2PF_U(errmsk5);
|
|
Torsten Duwe |
ad3f61 |
+
|
|
Torsten Duwe |
ad3f61 |
+ return vf_int_mask;
|
|
Torsten Duwe |
ad3f61 |
+}
|
|
Torsten Duwe |
ad3f61 |
+
|
|
Torsten Duwe |
ad3f61 |
+static void enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
|
|
Torsten Duwe |
ad3f61 |
+{
|
|
Torsten Duwe |
ad3f61 |
+ /* Enable VF2PF Messaging Ints - VFs 0 through 15 per vf_mask[15:0] */
|
|
Torsten Duwe |
ad3f61 |
+ adf_gen2_enable_vf2pf_interrupts(pmisc_addr, vf_mask);
|
|
Torsten Duwe |
ad3f61 |
+
|
|
Torsten Duwe |
ad3f61 |
+ /* Enable VF2PF Messaging Ints - VFs 16 through 31 per vf_mask[31:16] */
|
|
Torsten Duwe |
ad3f61 |
+ if (vf_mask >> 16) {
|
|
Torsten Duwe |
ad3f61 |
+ u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5)
|
|
Torsten Duwe |
ad3f61 |
+ & ~ADF_DH895XCC_ERR_MSK_VF2PF_U(vf_mask);
|
|
Torsten Duwe |
ad3f61 |
+
|
|
Torsten Duwe |
ad3f61 |
+ ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val);
|
|
Torsten Duwe |
ad3f61 |
+ }
|
|
Torsten Duwe |
ad3f61 |
+}
|
|
Torsten Duwe |
ad3f61 |
+
|
|
Torsten Duwe |
ad3f61 |
+static void disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask)
|
|
Torsten Duwe |
ad3f61 |
+{
|
|
Torsten Duwe |
ad3f61 |
+ /* Disable VF2PF interrupts for VFs 0 through 15 per vf_mask[15:0] */
|
|
Torsten Duwe |
ad3f61 |
+ adf_gen2_disable_vf2pf_interrupts(pmisc_addr, vf_mask);
|
|
Torsten Duwe |
ad3f61 |
+
|
|
Torsten Duwe |
ad3f61 |
+ /* Disable VF2PF interrupts for VFs 16 through 31 per vf_mask[31:16] */
|
|
Torsten Duwe |
ad3f61 |
+ if (vf_mask >> 16) {
|
|
Torsten Duwe |
ad3f61 |
+ u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5)
|
|
Torsten Duwe |
ad3f61 |
+ | ADF_DH895XCC_ERR_MSK_VF2PF_U(vf_mask);
|
|
Torsten Duwe |
ad3f61 |
+
|
|
Torsten Duwe |
ad3f61 |
+ ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val);
|
|
Torsten Duwe |
ad3f61 |
+ }
|
|
Torsten Duwe |
ad3f61 |
+}
|
|
Torsten Duwe |
ad3f61 |
+
|
|
Torsten Duwe |
ad3f61 |
static int adf_enable_pf2vf_comms(struct adf_accel_dev *accel_dev)
|
|
Torsten Duwe |
ad3f61 |
{
|
|
Torsten Duwe |
ad3f61 |
spin_lock_init(&accel_dev->pf.vf2pf_ints_lock);
|
|
Torsten Duwe |
ad3f61 |
@@ -226,6 +272,9 @@ void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
|
|
Torsten Duwe |
ad3f61 |
hw_data->enable_ints = adf_enable_ints;
|
|
Torsten Duwe |
ad3f61 |
hw_data->reset_device = adf_reset_sbr;
|
|
Torsten Duwe |
ad3f61 |
hw_data->get_pf2vf_offset = get_pf2vf_offset;
|
|
Torsten Duwe |
ad3f61 |
+ hw_data->get_vf2pf_sources = get_vf2pf_sources;
|
|
Torsten Duwe |
ad3f61 |
+ hw_data->enable_vf2pf_interrupts = enable_vf2pf_interrupts;
|
|
Torsten Duwe |
ad3f61 |
+ hw_data->disable_vf2pf_interrupts = disable_vf2pf_interrupts;
|
|
Torsten Duwe |
ad3f61 |
hw_data->enable_pfvf_comms = adf_enable_pf2vf_comms;
|
|
Torsten Duwe |
ad3f61 |
hw_data->disable_iov = adf_disable_sriov;
|
|
Torsten Duwe |
ad3f61 |
hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
|
|
Torsten Duwe |
ad3f61 |
diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h
|
|
Torsten Duwe |
ad3f61 |
index f99319cd45432..0f9f24b446638 100644
|
|
Torsten Duwe |
ad3f61 |
--- a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h
|
|
Torsten Duwe |
ad3f61 |
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h
|
|
Torsten Duwe |
ad3f61 |
@@ -34,7 +34,10 @@
|
|
Torsten Duwe |
ad3f61 |
#define ADF_DH895XCC_CERRSSMSH(i) (i * 0x4000 + 0x10)
|
|
Torsten Duwe |
ad3f61 |
#define ADF_DH895XCC_ERRSSMSH_EN BIT(3)
|
|
Torsten Duwe |
ad3f61 |
|
|
Torsten Duwe |
ad3f61 |
-#define ADF_DH895XCC_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04))
|
|
Torsten Duwe |
ad3f61 |
+/* Masks for VF2PF interrupts */
|
|
Torsten Duwe |
ad3f61 |
+#define ADF_DH895XCC_ERR_REG_VF2PF_U(vf_src) (((vf_src) & 0x0000FFFF) << 16)
|
|
Torsten Duwe |
ad3f61 |
+#define ADF_DH895XCC_ERR_MSK_VF2PF_U(vf_mask) ((vf_mask) >> 16)
|
|
Torsten Duwe |
ad3f61 |
+#define ADF_DH895XCC_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04))
|
|
Torsten Duwe |
ad3f61 |
|
|
Torsten Duwe |
ad3f61 |
/* AE to function mapping */
|
|
Torsten Duwe |
ad3f61 |
#define ADF_DH895XCC_AE2FUNC_MAP_GRP_A_NUM_REGS 96
|
|
Torsten Duwe |
ad3f61 |
--
|
|
Torsten Duwe |
ad3f61 |
2.35.3
|
|
Torsten Duwe |
ad3f61 |
|