From 2ca1e0a7fafa65fc6bd8d0236146f8fb8e8a3f81 Mon Sep 17 00:00:00 2001

From: Marco Chiappero <marco.chiappero@intel.com>

Date: Thu, 7 Apr 2022 17:54:49 +0100

Subject: [PATCH] crypto: qat - fix wording and formatting in code comment

Git-commit: 2ca1e0a7fafa65fc6bd8d0236146f8fb8e8a3f81

Patch-mainline: v5.19-rc1

References: jsc#PED-1073

Remove an unintentional extra space and improve the readability of a

PFVF related code comment.

Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>

Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>

Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Torsten Duwe <duwe@suse.de>

---

 drivers/crypto/qat/qat_common/adf_pfvf_msg.h | 4 ++--

 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/qat/qat_common/adf_pfvf_msg.h b/drivers/crypto/qat/qat_common/adf_pfvf_msg.h

index 9c37a26613920..204a424389926 100644

--- a/drivers/crypto/qat/qat_common/adf_pfvf_msg.h

+++ b/drivers/crypto/qat/qat_common/adf_pfvf_msg.h

@@ -8,8 +8,8 @@

 /*

  * PF<->VF Gen2 Messaging format

  *

- * The PF has an array of 32-bit PF2VF registers, one for each VF.  The

- * PF can access all these registers; each VF can access only the one

+ * The PF has an array of 32-bit PF2VF registers, one for each VF. The

+ * PF can access all these registers while each VF can access only the one

  * register associated with that particular VF.

  *

  * The register functionally is split into two parts:

-- 

2.35.3