From 0eaa51543273fd0f4ba9bea83638f7033436e5eb Mon Sep 17 00:00:00 2001

From: Giovanni Cabiddu <giovanni.cabiddu@intel.com>

Date: Thu, 7 Apr 2022 17:54:41 +0100

Subject: [PATCH] crypto: qat - set COMPRESSION capability for DH895XCC

Git-commit: 0eaa51543273fd0f4ba9bea83638f7033436e5eb

Patch-mainline: v5.19-rc1

References: jsc#PED-1073

The capability detection logic clears bits for the features that are

disabled in a certain SKU. For example, if the bit associate to

compression is not present in the LEGFUSE register, the correspondent

bit is cleared in the capability mask.

This change adds the compression capability to the mask as this was

missing in the commit that enhanced the capability detection logic.

Fixes: cfe4894eccdc ("crypto: qat - set COMPRESSION capability for QAT GEN2")

Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>

Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>

Reviewed-by: Marco Chiappero <marco.chiappero@intel.com>

Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Torsten Duwe <duwe@suse.de>

---

 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c | 3 ++-

 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

index ff13047772e34..61d5467e0d92b 100644

--- a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

+++ b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

@@ -59,7 +59,8 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)

 	capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |

 		       ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |

 		       ICP_ACCEL_CAPABILITIES_AUTHENTICATION |

-		       ICP_ACCEL_CAPABILITIES_CIPHER;

+		       ICP_ACCEL_CAPABILITIES_CIPHER |

+		       ICP_ACCEL_CAPABILITIES_COMPRESSION;

 	/* Read accelerator capabilities mask */

 	pci_read_config_dword(pdev, ADF_DEVICE_LEGFUSE_OFFSET, &legfuses);

-- 

2.35.3