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From 3a5b2a0883288527e71450978c0f5c442aab1218 Mon Sep 17 00:00:00 2001
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From: Marco Chiappero <marco.chiappero@intel.com>
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Date: Thu, 16 Dec 2021 09:13:25 +0000
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Subject: [PATCH] crypto: qat - store the ring-to-service mapping
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Git-commit: 3a5b2a0883288527e71450978c0f5c442aab1218
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Patch-mainline: v5.17-rc1
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References: jsc#PED-1073
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This driver relies on either the FW (on the PF) or the PF (on the VF) to
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know how crypto services and rings map to one another. Store this
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information so that it can be referenced in the future at runtime for
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checks or extensions.
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Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
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Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
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Reviewed-by: Fiona Trahe <fiona.trahe@intel.com>
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Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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Signed-off-by: Torsten Duwe <duwe@suse.de>
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---
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drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c | 1 +
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drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c | 1 +
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.../crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c | 1 +
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drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c | 1 +
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drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c | 1 +
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drivers/crypto/qat/qat_common/adf_accel_devices.h | 8 ++++++++
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drivers/crypto/qat/qat_common/adf_cfg_common.h | 13 +++++++++++++
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drivers/crypto/qat/qat_common/adf_gen2_hw_data.h | 8 ++++++++
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drivers/crypto/qat/qat_common/adf_gen4_hw_data.h | 8 ++++++++
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.../crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c | 1 +
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.../qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c | 1 +
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11 files changed, 44 insertions(+)
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diff --git a/drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c b/drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c
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index 0d1603894af44..67cd20f443ab4 100644
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--- a/drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c
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+++ b/drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c
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@@ -246,6 +246,7 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data)
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hw_data->num_logical_accel = 1;
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hw_data->tx_rx_gap = ADF_4XXX_RX_RINGS_OFFSET;
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hw_data->tx_rings_mask = ADF_4XXX_TX_RINGS_MASK;
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+ hw_data->ring_to_svc_map = ADF_GEN4_DEFAULT_RING_TO_SRV_MAP;
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hw_data->alloc_irq = adf_isr_resource_alloc;
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hw_data->free_irq = adf_isr_resource_free;
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hw_data->enable_error_correction = adf_enable_error_correction;
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diff --git a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
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index 3987a44fa164b..b941fe3713ff1 100644
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--- a/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
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+++ b/drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
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@@ -109,6 +109,7 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
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hw_data->num_engines = ADF_C3XXX_MAX_ACCELENGINES;
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hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;
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hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;
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+ hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
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hw_data->alloc_irq = adf_isr_resource_alloc;
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hw_data->free_irq = adf_isr_resource_free;
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hw_data->enable_error_correction = adf_gen2_enable_error_correction;
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diff --git a/drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c b/drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
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index 85122013534de..a9fbe57b32ae3 100644
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--- a/drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
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+++ b/drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
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@@ -67,6 +67,7 @@ void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)
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hw_data->num_engines = ADF_C3XXXIOV_MAX_ACCELENGINES;
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hw_data->tx_rx_gap = ADF_C3XXXIOV_RX_RINGS_OFFSET;
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hw_data->tx_rings_mask = ADF_C3XXXIOV_TX_RINGS_MASK;
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+ hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
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hw_data->alloc_irq = adf_vf_isr_resource_alloc;
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hw_data->free_irq = adf_vf_isr_resource_free;
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hw_data->enable_error_correction = adf_vf_void_noop;
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diff --git a/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c b/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
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index a76e33d7a215a..b1eac2f81faa7 100644
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--- a/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
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+++ b/drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
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@@ -111,6 +111,7 @@ void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
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hw_data->num_engines = ADF_C62X_MAX_ACCELENGINES;
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hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;
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hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;
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+ hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
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hw_data->alloc_irq = adf_isr_resource_alloc;
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hw_data->free_irq = adf_isr_resource_free;
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hw_data->enable_error_correction = adf_gen2_enable_error_correction;
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diff --git a/drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c b/drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c
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index 99c56405f88fb..0282038fca548 100644
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--- a/drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c
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+++ b/drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c
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@@ -67,6 +67,7 @@ void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data)
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hw_data->num_engines = ADF_C62XIOV_MAX_ACCELENGINES;
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hw_data->tx_rx_gap = ADF_C62XIOV_RX_RINGS_OFFSET;
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hw_data->tx_rings_mask = ADF_C62XIOV_TX_RINGS_MASK;
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+ hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
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hw_data->alloc_irq = adf_vf_isr_resource_alloc;
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hw_data->free_irq = adf_vf_isr_resource_free;
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hw_data->enable_error_correction = adf_vf_void_noop;
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diff --git a/drivers/crypto/qat/qat_common/adf_accel_devices.h b/drivers/crypto/qat/qat_common/adf_accel_devices.h
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index 1fb32f3e78df6..59f06e53d316b 100644
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--- a/drivers/crypto/qat/qat_common/adf_accel_devices.h
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+++ b/drivers/crypto/qat/qat_common/adf_accel_devices.h
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@@ -208,6 +208,7 @@ struct adf_hw_device_data {
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u32 ae_mask;
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u32 admin_ae_mask;
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u16 tx_rings_mask;
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+ u16 ring_to_svc_map;
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u8 tx_rx_gap;
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u8 num_banks;
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u16 num_banks_per_vf;
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@@ -224,12 +225,19 @@ struct adf_hw_device_data {
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/* CSR read macro */
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#define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
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+#define ADF_CFG_NUM_SERVICES 4
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+#define ADF_SRV_TYPE_BIT_LEN 3
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+#define ADF_SRV_TYPE_MASK 0x7
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+
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#define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev)
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#define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)
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#define GET_HW_DATA(accel_dev) (accel_dev->hw_device)
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#define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)
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#define GET_NUM_RINGS_PER_BANK(accel_dev) \
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GET_HW_DATA(accel_dev)->num_rings_per_bank
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+#define GET_SRV_TYPE(accel_dev, idx) \
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+ (((GET_HW_DATA(accel_dev)->ring_to_svc_map) >> (ADF_SRV_TYPE_BIT_LEN * (idx))) \
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+ & ADF_SRV_TYPE_MASK)
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#define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
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#define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops)
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#define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->pfvf_ops)
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diff --git a/drivers/crypto/qat/qat_common/adf_cfg_common.h b/drivers/crypto/qat/qat_common/adf_cfg_common.h
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index 4fabb70b1f180..6e5de1dab97b4 100644
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--- a/drivers/crypto/qat/qat_common/adf_cfg_common.h
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+++ b/drivers/crypto/qat/qat_common/adf_cfg_common.h
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@@ -19,6 +19,19 @@
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#define ADF_MAX_DEVICES (32 * 32)
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#define ADF_DEVS_ARRAY_SIZE BITS_TO_LONGS(ADF_MAX_DEVICES)
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+#define ADF_CFG_SERV_RING_PAIR_0_SHIFT 0
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+#define ADF_CFG_SERV_RING_PAIR_1_SHIFT 3
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+#define ADF_CFG_SERV_RING_PAIR_2_SHIFT 6
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+#define ADF_CFG_SERV_RING_PAIR_3_SHIFT 9
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+enum adf_cfg_service_type {
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+ UNUSED = 0,
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+ CRYPTO,
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+ COMP,
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+ SYM,
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+ ASYM,
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+ USED
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+};
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+
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enum adf_cfg_val_type {
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ADF_DEC,
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ADF_HEX,
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diff --git a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
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index 7c2c173664609..f2e0451b11c08 100644
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--- a/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
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+++ b/drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
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@@ -4,6 +4,7 @@
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#define ADF_GEN2_HW_DATA_H_
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#include "adf_accel_devices.h"
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+#include "adf_cfg_common.h"
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/* Transport access */
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#define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
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@@ -116,6 +117,13 @@ do { \
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#define ADF_POWERGATE_DC BIT(23)
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#define ADF_POWERGATE_PKE BIT(24)
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1dbf5a |
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+/* Default ring mapping */
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+#define ADF_GEN2_DEFAULT_RING_TO_SRV_MAP \
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+ (CRYPTO << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \
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+ CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \
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+ UNUSED << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \
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+ COMP << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
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+
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/* WDT timers
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*
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* Timeout is in cycles. Clock speed may vary across products but this
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diff --git a/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h b/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h
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index 449d6a5976a9d..f0f71ca44ca36 100644
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--- a/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h
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+++ b/drivers/crypto/qat/qat_common/adf_gen4_hw_data.h
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@@ -4,6 +4,7 @@
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#define ADF_GEN4_HW_CSR_DATA_H_
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#include "adf_accel_devices.h"
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+#include "adf_cfg_common.h"
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1dbf5a |
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1dbf5a |
/* Transport access */
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1dbf5a |
#define ADF_BANK_INT_SRC_SEL_MASK 0x44UL
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@@ -94,6 +95,13 @@ do { \
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ADF_RING_BUNDLE_SIZE * (bank) + \
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ADF_RING_CSR_RING_SRV_ARB_EN, (value))
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+/* Default ring mapping */
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+#define ADF_GEN4_DEFAULT_RING_TO_SRV_MAP \
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+ (ASYM << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \
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+ SYM << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \
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+ ASYM << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \
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+ SYM << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
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+
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/* WDT timers
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*
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* Timeout is in cycles. Clock speed may vary across products but this
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diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
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index 2d18279191d7e..09599fe4d2f3f 100644
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--- a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
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+++ b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
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@@ -191,6 +191,7 @@ void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)
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hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES;
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hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;
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hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;
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+ hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
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hw_data->alloc_irq = adf_isr_resource_alloc;
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hw_data->free_irq = adf_isr_resource_free;
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hw_data->enable_error_correction = adf_gen2_enable_error_correction;
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diff --git a/drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c b/drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
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index 5489d6c022561..31c14d7e1c115 100644
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--- a/drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
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+++ b/drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
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@@ -67,6 +67,7 @@ void adf_init_hw_data_dh895xcciov(struct adf_hw_device_data *hw_data)
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hw_data->num_engines = ADF_DH895XCCIOV_MAX_ACCELENGINES;
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hw_data->tx_rx_gap = ADF_DH895XCCIOV_RX_RINGS_OFFSET;
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hw_data->tx_rings_mask = ADF_DH895XCCIOV_TX_RINGS_MASK;
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+ hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
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hw_data->alloc_irq = adf_vf_isr_resource_alloc;
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hw_data->free_irq = adf_vf_isr_resource_free;
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hw_data->enable_error_correction = adf_vf_void_noop;
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--
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2.35.3
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