From 27c0f3a14f9fd16eed4e0167cf58225ca28ab4f8 Mon Sep 17 00:00:00 2001

From: Marco Chiappero <marco.chiappero@intel.com>

Date: Thu, 7 Apr 2022 17:54:48 +0100

Subject: [PATCH] crypto: qat - test PFVF registers for spurious interrupts on

 GEN4

Git-commit: 27c0f3a14f9fd16eed4e0167cf58225ca28ab4f8

Patch-mainline: v5.19-rc1

References: jsc#PED-1073

Spurious PFVF interrupts can happen when either the ISR is invoked

without a valid source being set or, otherwise, when no interrupt bit

is set in the PFVF register containing the message.

The latter test was present for GEN2 devices but missing for GEN4, this

patch fills the gap.

Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>

Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>

Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Torsten Duwe <duwe@suse.de>

---

 drivers/crypto/qat/qat_common/adf_gen4_pfvf.c | 6 ++++++

 1 file changed, 6 insertions(+)

diff --git a/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c b/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c

index d80d493a77568..f7860bf612da9 100644

--- a/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c

+++ b/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c

@@ -96,10 +96,16 @@ static struct pfvf_message adf_gen4_pfvf_recv(struct adf_accel_dev *accel_dev,

 					      u32 pfvf_offset, u8 compat_ver)

 {

 	void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);

+	struct pfvf_message msg = { 0 };

 	u32 csr_val;

 	/* Read message from the CSR */

 	csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset);

+	if (!(csr_val & ADF_PFVF_INT)) {

+		dev_info(&GET_DEV(accel_dev),

+			 "Spurious PFVF interrupt, msg 0x%.8x. Ignored\n", csr_val);

+		return msg;

+	}

 	/* We can now acknowledge the message reception by clearing the

 	 * interrupt bit

-- 

2.35.3