From fa374954836779a08cfb773ff20fe2083cb9d420 Mon Sep 17 00:00:00 2001

From: Marco Chiappero <marco.chiappero@intel.com>

Date: Thu, 7 Apr 2022 17:54:54 +0100

Subject: [PATCH] crypto: qat - use u32 variables in all GEN4 pfvf_ops

Git-commit: fa374954836779a08cfb773ff20fe2083cb9d420

Patch-mainline: v5.19-rc1

References: jsc#PED-1073

Change adf_gen4_enable_vf2pf_interrupts() to use a u32 variable,

consistently with both other GEN4 pfvf_ops and pfvf_ops of other

generations.

Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>

Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>

Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Torsten Duwe <duwe@suse.de>

---

 drivers/crypto/qat/qat_common/adf_gen4_pfvf.c | 2 +-

 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c b/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c

index 8091fc52e13a1..73ec8defb2d33 100644

--- a/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c

+++ b/drivers/crypto/qat/qat_common/adf_gen4_pfvf.c

@@ -40,7 +40,7 @@ static u32 adf_gen4_pf_get_vf2pf_offset(u32 i)

 static void adf_gen4_enable_vf2pf_interrupts(void __iomem *pmisc_addr,

 					     u32 vf_mask)

 {

-	unsigned int val;

+	u32 val;

 	val = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK) & ~vf_mask;

 	ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, val);

-- 

2.35.3