From 1385eb4d14d447cc5d744bc2ac34f43be66c9963 Mon Sep 17 00:00:00 2001

From: Tudor Ambarus <tudor.ambarus@microchip.com>

Date: Wed, 15 Dec 2021 13:01:12 +0200

Subject: [PATCH] dmaengine: at_xdmac: Fix lld view setting

Git-commit: 1385eb4d14d447cc5d744bc2ac34f43be66c9963

Patch-mainline: v5.17-rc1

References: git-fixes

AT_XDMAC_CNDC_NDVIEW_NDV3 was set even for AT_XDMAC_MBR_UBC_NDV2,

because of the wrong bit handling. Fix it.

Fixes: ee0fe35c8dcd ("dmaengine: xdmac: Handle descriptor's view 3 registers")

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

Link: https://lore.kernel.org/r/20211215110115.191749-10-tudor.ambarus@microchip.com

Signed-off-by: Vinod Koul <vkoul@kernel.org>

Acked-by: Takashi Iwai <tiwai@suse.de>

---

 drivers/dma/at_xdmac.c | 4 +++-

 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c

index 0b09ec752db4..6e5bfc9b3825 100644

--- a/drivers/dma/at_xdmac.c

+++ b/drivers/dma/at_xdmac.c

@@ -99,6 +99,7 @@

 #define		AT_XDMAC_CNDC_NDE		(0x1 << 0)		/* Channel x Next Descriptor Enable */

 #define		AT_XDMAC_CNDC_NDSUP		(0x1 << 1)		/* Channel x Next Descriptor Source Update */

 #define		AT_XDMAC_CNDC_NDDUP		(0x1 << 2)		/* Channel x Next Descriptor Destination Update */

+#define		AT_XDMAC_CNDC_NDVIEW_MASK	GENMASK(28, 27)

 #define		AT_XDMAC_CNDC_NDVIEW_NDV0	(0x0 << 3)		/* Channel x Next Descriptor View 0 */

 #define		AT_XDMAC_CNDC_NDVIEW_NDV1	(0x1 << 3)		/* Channel x Next Descriptor View 1 */

 #define		AT_XDMAC_CNDC_NDVIEW_NDV2	(0x2 << 3)		/* Channel x Next Descriptor View 2 */

@@ -402,7 +403,8 @@ static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,

 	 */

 	if (at_xdmac_chan_is_cyclic(atchan))

 		reg = AT_XDMAC_CNDC_NDVIEW_NDV1;

-	else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3)

+	else if ((first->lld.mbr_ubc &

+		  AT_XDMAC_CNDC_NDVIEW_MASK) == AT_XDMAC_MBR_UBC_NDV3)

 		reg = AT_XDMAC_CNDC_NDVIEW_NDV3;

 	else

 		reg = AT_XDMAC_CNDC_NDVIEW_NDV2;

-- 

2.31.1