From e9d9ce5462fecdeefec87953de71df4d025cbc72 Mon Sep 17 00:00:00 2001

From: Marijn Suijten <marijn.suijten@somainline.org>

Date: Thu, 27 Apr 2023 00:37:17 +0200

Subject: [PATCH] drm/msm/dpu: Move non-MDP_TOP INTF_INTR offsets out of hwio header

Git-commit: e9d9ce5462fecdeefec87953de71df4d025cbc72

Patch-mainline: v6.4-rc3

References: git-fixes

These offsets do not fall under the MDP TOP block and do not fit the

comment right above.  Move them to dpu_hw_interrupts.c next to the

repsective MDP_INTF_x_OFF interrupt block offsets.

Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>

Patchwork: https://patchwork.freedesktop.org/patch/534203/

Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-3-27ce1a5ab5c6@somainline.org

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>

Acked-by: Takashi Iwai <tiwai@suse.de>

---

 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c |    5 ++++-

 drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h          |    3 ---

 2 files changed, 4 insertions(+), 4 deletions(-)

--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

@@ -12,7 +12,7 @@

 /**

  * Register offsets in MDSS register file for the interrupt registers

- * w.r.t. to the MDP base

+ * w.r.t. the MDP base

  */

 #define MDP_SSPP_TOP0_OFF		0x0

 #define MDP_INTF_0_OFF			0x6A000

@@ -21,6 +21,9 @@

 #define MDP_INTF_3_OFF			0x6B800

 #define MDP_INTF_4_OFF			0x6C000

 #define MDP_INTF_5_OFF			0x6C800

+#define INTF_INTR_EN			0x1c0

+#define INTF_INTR_STATUS		0x1c4

+#define INTF_INTR_CLEAR			0x1c8

 #define MDP_AD4_0_OFF			0x7C000

 #define MDP_AD4_1_OFF			0x7D000

 #define MDP_AD4_INTR_EN_OFF		0x41c

--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h

+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h

@@ -20,9 +20,6 @@

 #define HIST_INTR_EN                    0x01c

 #define HIST_INTR_STATUS                0x020

 #define HIST_INTR_CLEAR                 0x024

-#define INTF_INTR_EN                    0x1C0

-#define INTF_INTR_STATUS                0x1C4

-#define INTF_INTR_CLEAR                 0x1C8

 #define SPLIT_DISPLAY_EN                0x2F4

 #define SPLIT_DISPLAY_UPPER_PIPE_CTRL   0x2F8

 #define DSPP_IGC_COLOR0_RAM_LUTN        0x300