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Oliver Neukum |
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From cb3c2c47e3b8068e5d46ad829318cd077406fc9d Mon Sep 17 00:00:00 2001
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Oliver Neukum |
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From: Wu Hao <hao.wu@intel.com>
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Oliver Neukum |
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Date: Mon, 12 Aug 2019 10:50:03 +0800
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Oliver Neukum |
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Subject: [PATCH] fpga: dfl: fme: add global error reporting support
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Git-commit: cb3c2c47e3b8068e5d46ad829318cd077406fc9d
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References: jsc#SLE-13441
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Patch-mainline: v5.4-rc1
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This patch adds support for global error reporting for FPGA
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Management Engine (FME), it introduces sysfs interfaces to
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report different error detected by the hardware, and allow
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user to clear errors or inject error for testing purpose.
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Signed-off-by: Luwei Kang <luwei.kang@intel.com>
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Signed-off-by: Ananda Ravuri <ananda.ravuri@intel.com>
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Oliver Neukum |
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Signed-off-by: Xu Yilun <yilun.xu@intel.com>
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Oliver Neukum |
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Signed-off-by: Wu Hao <hao.wu@intel.com>
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Oliver Neukum |
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Acked-by: Alan Tull <atull@kernel.org>
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Oliver Neukum |
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Signed-off-by: Moritz Fischer <mdf@kernel.org>
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Oliver Neukum |
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Signed-off-by: Oliver Neukum <oneukum@suse.com>
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Oliver Neukum |
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---
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Documentation/ABI/testing/sysfs-platform-dfl-fme | 62 +++
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drivers/fpga/Makefile | 2
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drivers/fpga/dfl-fme-error.c | 359 +++++++++++++++++++++++
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drivers/fpga/dfl-fme-main.c | 17 -
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drivers/fpga/dfl-fme.h | 3
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drivers/fpga/dfl.h | 5
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6 files changed, 445 insertions(+), 3 deletions(-)
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create mode 100644 drivers/fpga/dfl-fme-error.c
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Oliver Neukum |
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--- a/Documentation/ABI/testing/sysfs-platform-dfl-fme
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+++ b/Documentation/ABI/testing/sysfs-platform-dfl-fme
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@@ -44,3 +44,65 @@ Description: Read-only. It returns socke
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this FPGA belongs to, only valid for integrated solution.
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Oliver Neukum |
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User only needs this information, in case standard numa node
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can't provide correct information.
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+
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+What: /sys/bus/platform/devices/dfl-fme.0/errors/pcie0_errors
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Oliver Neukum |
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+Date: August 2019
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Oliver Neukum |
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+KernelVersion: 5.4
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+Contact: Wu Hao <hao.wu@intel.com>
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Oliver Neukum |
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+Description: Read-Write. Read this file for errors detected on pcie0 link.
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+ Write this file to clear errors logged in pcie0_errors. Write
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+ fails with -EINVAL if input parsing fails or input error code
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+ doesn't match.
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+
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+What: /sys/bus/platform/devices/dfl-fme.0/errors/pcie1_errors
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+Date: August 2019
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+KernelVersion: 5.4
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+Contact: Wu Hao <hao.wu@intel.com>
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Oliver Neukum |
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+Description: Read-Write. Read this file for errors detected on pcie1 link.
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Oliver Neukum |
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+ Write this file to clear errors logged in pcie1_errors. Write
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Oliver Neukum |
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+ fails with -EINVAL if input parsing fails or input error code
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Oliver Neukum |
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+ doesn't match.
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+
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Oliver Neukum |
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+What: /sys/bus/platform/devices/dfl-fme.0/errors/nonfatal_errors
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Oliver Neukum |
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+Date: August 2019
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Oliver Neukum |
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+KernelVersion: 5.4
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+Contact: Wu Hao <hao.wu@intel.com>
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Oliver Neukum |
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+Description: Read-only. It returns non-fatal errors detected.
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+
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Oliver Neukum |
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+What: /sys/bus/platform/devices/dfl-fme.0/errors/catfatal_errors
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+Date: August 2019
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Oliver Neukum |
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+KernelVersion: 5.4
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+Contact: Wu Hao <hao.wu@intel.com>
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Oliver Neukum |
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+Description: Read-only. It returns catastrophic and fatal errors detected.
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Oliver Neukum |
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+
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Oliver Neukum |
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+What: /sys/bus/platform/devices/dfl-fme.0/errors/inject_errors
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Oliver Neukum |
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+Date: August 2019
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Oliver Neukum |
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+KernelVersion: 5.4
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Oliver Neukum |
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+Contact: Wu Hao <hao.wu@intel.com>
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Oliver Neukum |
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+Description: Read-Write. Read this file to check errors injected. Write this
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Oliver Neukum |
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+ file to inject errors for testing purpose. Write fails with
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+ -EINVAL if input parsing fails or input inject error code isn't
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+ supported.
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+
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Oliver Neukum |
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+What: /sys/bus/platform/devices/dfl-fme.0/errors/fme_errors
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Oliver Neukum |
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+Date: August 2019
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Oliver Neukum |
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+KernelVersion: 5.4
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Oliver Neukum |
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+Contact: Wu Hao <hao.wu@intel.com>
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Oliver Neukum |
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+Description: Read-Write. Read this file to get errors detected on FME.
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Oliver Neukum |
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+ Write this file to clear errors logged in fme_errors. Write
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Oliver Neukum |
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+ fials with -EINVAL if input parsing fails or input error code
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Oliver Neukum |
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+ doesn't match.
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Oliver Neukum |
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+
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Oliver Neukum |
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+What: /sys/bus/platform/devices/dfl-fme.0/errors/first_error
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Oliver Neukum |
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+Date: August 2019
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Oliver Neukum |
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+KernelVersion: 5.4
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Oliver Neukum |
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+Contact: Wu Hao <hao.wu@intel.com>
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Oliver Neukum |
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+Description: Read-only. Read this file to get the first error detected by
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Oliver Neukum |
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+ hardware.
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+
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Oliver Neukum |
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+What: /sys/bus/platform/devices/dfl-fme.0/errors/next_error
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Oliver Neukum |
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+Date: August 2019
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Oliver Neukum |
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+KernelVersion: 5.4
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Oliver Neukum |
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+Contact: Wu Hao <hao.wu@intel.com>
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Oliver Neukum |
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+Description: Read-only. Read this file to get the second error detected by
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Oliver Neukum |
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+ hardware.
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--- a/drivers/fpga/Makefile
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+++ b/drivers/fpga/Makefile
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@@ -39,7 +39,7 @@ obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl
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obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o
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obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o
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-dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
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+dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o
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dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
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dfl-afu-objs += dfl-afu-error.o
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--- /dev/null
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+++ b/drivers/fpga/dfl-fme-error.c
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@@ -0,0 +1,359 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Driver for FPGA Management Engine Error Management
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+ *
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+ * Copyright 2019 Intel Corporation, Inc.
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+ *
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+ * Authors:
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+ * Kang Luwei <luwei.kang@intel.com>
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+ * Xiao Guangrong <guangrong.xiao@linux.intel.com>
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+ * Wu Hao <hao.wu@intel.com>
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Oliver Neukum |
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+ * Joseph Grecco <joe.grecco@intel.com>
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Oliver Neukum |
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+ * Enno Luebbers <enno.luebbers@intel.com>
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+ * Tim Whisonant <tim.whisonant@intel.com>
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+ * Ananda Ravuri <ananda.ravuri@intel.com>
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Oliver Neukum |
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+ * Mitchel, Henry <henry.mitchel@intel.com>
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+ */
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+
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+#include <linux/uaccess.h>
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+
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+#include "dfl.h"
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+#include "dfl-fme.h"
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+
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+#define FME_ERROR_MASK 0x8
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+#define FME_ERROR 0x10
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+#define MBP_ERROR BIT_ULL(6)
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+#define PCIE0_ERROR_MASK 0x18
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+#define PCIE0_ERROR 0x20
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+#define PCIE1_ERROR_MASK 0x28
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+#define PCIE1_ERROR 0x30
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+#define FME_FIRST_ERROR 0x38
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+#define FME_NEXT_ERROR 0x40
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+#define RAS_NONFAT_ERROR_MASK 0x48
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+#define RAS_NONFAT_ERROR 0x50
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+#define RAS_CATFAT_ERROR_MASK 0x58
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Oliver Neukum |
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+#define RAS_CATFAT_ERROR 0x60
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Oliver Neukum |
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+#define RAS_ERROR_INJECT 0x68
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Oliver Neukum |
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+#define INJECT_ERROR_MASK GENMASK_ULL(2, 0)
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+
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+#define ERROR_MASK GENMASK_ULL(63, 0)
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+
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+static ssize_t pcie0_errors_show(struct device *dev,
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+ struct device_attribute *attr, char *buf)
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+{
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+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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+ void __iomem *base;
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+ u64 value;
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+
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+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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+
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+ mutex_lock(&pdata->lock);
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+ value = readq(base + PCIE0_ERROR);
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+ mutex_unlock(&pdata->lock);
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+
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+ return sprintf(buf, "0x%llx\n", (unsigned long long)value);
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+}
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+
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+static ssize_t pcie0_errors_store(struct device *dev,
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+ struct device_attribute *attr,
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+ const char *buf, size_t count)
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+{
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+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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+ void __iomem *base;
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+ int ret = 0;
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+ u64 v, val;
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+
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+ if (kstrtou64(buf, 0, &val))
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+ return -EINVAL;
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+
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+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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+
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+ mutex_lock(&pdata->lock);
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+ writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK);
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+
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+ v = readq(base + PCIE0_ERROR);
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+ if (val == v)
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+ writeq(v, base + PCIE0_ERROR);
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+ else
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+ ret = -EINVAL;
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+
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+ writeq(0ULL, base + PCIE0_ERROR_MASK);
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+ mutex_unlock(&pdata->lock);
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+ return ret ? ret : count;
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Oliver Neukum |
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+}
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Oliver Neukum |
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+static DEVICE_ATTR_RW(pcie0_errors);
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+
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+static ssize_t pcie1_errors_show(struct device *dev,
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+ struct device_attribute *attr, char *buf)
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Oliver Neukum |
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+{
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Oliver Neukum |
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+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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+ void __iomem *base;
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+ u64 value;
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Oliver Neukum |
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+
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+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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+
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+ mutex_lock(&pdata->lock);
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+ value = readq(base + PCIE1_ERROR);
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Oliver Neukum |
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+ mutex_unlock(&pdata->lock);
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+
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Oliver Neukum |
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+ return sprintf(buf, "0x%llx\n", (unsigned long long)value);
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Oliver Neukum |
a46fd7 |
+}
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a46fd7 |
+
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Oliver Neukum |
a46fd7 |
+static ssize_t pcie1_errors_store(struct device *dev,
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Oliver Neukum |
a46fd7 |
+ struct device_attribute *attr,
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Oliver Neukum |
a46fd7 |
+ const char *buf, size_t count)
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Oliver Neukum |
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+{
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Oliver Neukum |
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+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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Oliver Neukum |
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+ void __iomem *base;
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Oliver Neukum |
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+ int ret = 0;
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Oliver Neukum |
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+ u64 v, val;
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Oliver Neukum |
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+
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Oliver Neukum |
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+ if (kstrtou64(buf, 0, &val))
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Oliver Neukum |
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+ return -EINVAL;
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Oliver Neukum |
a46fd7 |
+
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Oliver Neukum |
a46fd7 |
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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a46fd7 |
+
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Oliver Neukum |
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+ mutex_lock(&pdata->lock);
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Oliver Neukum |
a46fd7 |
+ writeq(GENMASK_ULL(63, 0), base + PCIE1_ERROR_MASK);
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Oliver Neukum |
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+
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Oliver Neukum |
a46fd7 |
+ v = readq(base + PCIE1_ERROR);
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Oliver Neukum |
a46fd7 |
+ if (val == v)
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Oliver Neukum |
a46fd7 |
+ writeq(v, base + PCIE1_ERROR);
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Oliver Neukum |
a46fd7 |
+ else
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Oliver Neukum |
a46fd7 |
+ ret = -EINVAL;
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Oliver Neukum |
a46fd7 |
+
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Oliver Neukum |
a46fd7 |
+ writeq(0ULL, base + PCIE1_ERROR_MASK);
|
|
Oliver Neukum |
a46fd7 |
+ mutex_unlock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+ return ret ? ret : count;
|
|
Oliver Neukum |
a46fd7 |
+}
|
|
Oliver Neukum |
a46fd7 |
+static DEVICE_ATTR_RW(pcie1_errors);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static ssize_t nonfatal_errors_show(struct device *dev,
|
|
Oliver Neukum |
a46fd7 |
+ struct device_attribute *attr, char *buf)
|
|
Oliver Neukum |
a46fd7 |
+{
|
|
Oliver Neukum |
a46fd7 |
+ void __iomem *base;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ return sprintf(buf, "0x%llx\n",
|
|
Oliver Neukum |
a46fd7 |
+ (unsigned long long)readq(base + RAS_NONFAT_ERROR));
|
|
Oliver Neukum |
a46fd7 |
+}
|
|
Oliver Neukum |
a46fd7 |
+static DEVICE_ATTR_RO(nonfatal_errors);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static ssize_t catfatal_errors_show(struct device *dev,
|
|
Oliver Neukum |
a46fd7 |
+ struct device_attribute *attr, char *buf)
|
|
Oliver Neukum |
a46fd7 |
+{
|
|
Oliver Neukum |
a46fd7 |
+ void __iomem *base;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ return sprintf(buf, "0x%llx\n",
|
|
Oliver Neukum |
a46fd7 |
+ (unsigned long long)readq(base + RAS_CATFAT_ERROR));
|
|
Oliver Neukum |
a46fd7 |
+}
|
|
Oliver Neukum |
a46fd7 |
+static DEVICE_ATTR_RO(catfatal_errors);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static ssize_t inject_errors_show(struct device *dev,
|
|
Oliver Neukum |
a46fd7 |
+ struct device_attribute *attr, char *buf)
|
|
Oliver Neukum |
a46fd7 |
+{
|
|
Oliver Neukum |
a46fd7 |
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
|
|
Oliver Neukum |
a46fd7 |
+ void __iomem *base;
|
|
Oliver Neukum |
a46fd7 |
+ u64 v;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ mutex_lock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+ v = readq(base + RAS_ERROR_INJECT);
|
|
Oliver Neukum |
a46fd7 |
+ mutex_unlock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ return sprintf(buf, "0x%llx\n",
|
|
Oliver Neukum |
a46fd7 |
+ (unsigned long long)FIELD_GET(INJECT_ERROR_MASK, v));
|
|
Oliver Neukum |
a46fd7 |
+}
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static ssize_t inject_errors_store(struct device *dev,
|
|
Oliver Neukum |
a46fd7 |
+ struct device_attribute *attr,
|
|
Oliver Neukum |
a46fd7 |
+ const char *buf, size_t count)
|
|
Oliver Neukum |
a46fd7 |
+{
|
|
Oliver Neukum |
a46fd7 |
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
|
|
Oliver Neukum |
a46fd7 |
+ void __iomem *base;
|
|
Oliver Neukum |
a46fd7 |
+ u8 inject_error;
|
|
Oliver Neukum |
a46fd7 |
+ u64 v;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ if (kstrtou8(buf, 0, &inject_error))
|
|
Oliver Neukum |
a46fd7 |
+ return -EINVAL;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ if (inject_error & ~INJECT_ERROR_MASK)
|
|
Oliver Neukum |
a46fd7 |
+ return -EINVAL;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ mutex_lock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+ v = readq(base + RAS_ERROR_INJECT);
|
|
Oliver Neukum |
a46fd7 |
+ v &= ~INJECT_ERROR_MASK;
|
|
Oliver Neukum |
a46fd7 |
+ v |= FIELD_PREP(INJECT_ERROR_MASK, inject_error);
|
|
Oliver Neukum |
a46fd7 |
+ writeq(v, base + RAS_ERROR_INJECT);
|
|
Oliver Neukum |
a46fd7 |
+ mutex_unlock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ return count;
|
|
Oliver Neukum |
a46fd7 |
+}
|
|
Oliver Neukum |
a46fd7 |
+static DEVICE_ATTR_RW(inject_errors);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static ssize_t fme_errors_show(struct device *dev,
|
|
Oliver Neukum |
a46fd7 |
+ struct device_attribute *attr, char *buf)
|
|
Oliver Neukum |
a46fd7 |
+{
|
|
Oliver Neukum |
a46fd7 |
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
|
|
Oliver Neukum |
a46fd7 |
+ void __iomem *base;
|
|
Oliver Neukum |
a46fd7 |
+ u64 value;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ mutex_lock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+ value = readq(base + FME_ERROR);
|
|
Oliver Neukum |
a46fd7 |
+ mutex_unlock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ return sprintf(buf, "0x%llx\n", (unsigned long long)value);
|
|
Oliver Neukum |
a46fd7 |
+}
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static ssize_t fme_errors_store(struct device *dev,
|
|
Oliver Neukum |
a46fd7 |
+ struct device_attribute *attr,
|
|
Oliver Neukum |
a46fd7 |
+ const char *buf, size_t count)
|
|
Oliver Neukum |
a46fd7 |
+{
|
|
Oliver Neukum |
a46fd7 |
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
|
|
Oliver Neukum |
a46fd7 |
+ void __iomem *base;
|
|
Oliver Neukum |
a46fd7 |
+ u64 v, val;
|
|
Oliver Neukum |
a46fd7 |
+ int ret = 0;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ if (kstrtou64(buf, 0, &val))
|
|
Oliver Neukum |
a46fd7 |
+ return -EINVAL;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ mutex_lock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+ writeq(GENMASK_ULL(63, 0), base + FME_ERROR_MASK);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ v = readq(base + FME_ERROR);
|
|
Oliver Neukum |
a46fd7 |
+ if (val == v)
|
|
Oliver Neukum |
a46fd7 |
+ writeq(v, base + FME_ERROR);
|
|
Oliver Neukum |
a46fd7 |
+ else
|
|
Oliver Neukum |
a46fd7 |
+ ret = -EINVAL;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ /* Workaround: disable MBP_ERROR if feature revision is 0 */
|
|
Oliver Neukum |
a46fd7 |
+ writeq(dfl_feature_revision(base) ? 0ULL : MBP_ERROR,
|
|
Oliver Neukum |
a46fd7 |
+ base + FME_ERROR_MASK);
|
|
Oliver Neukum |
a46fd7 |
+ mutex_unlock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+ return ret ? ret : count;
|
|
Oliver Neukum |
a46fd7 |
+}
|
|
Oliver Neukum |
a46fd7 |
+static DEVICE_ATTR_RW(fme_errors);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static ssize_t first_error_show(struct device *dev,
|
|
Oliver Neukum |
a46fd7 |
+ struct device_attribute *attr, char *buf)
|
|
Oliver Neukum |
a46fd7 |
+{
|
|
Oliver Neukum |
a46fd7 |
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
|
|
Oliver Neukum |
a46fd7 |
+ void __iomem *base;
|
|
Oliver Neukum |
a46fd7 |
+ u64 value;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ mutex_lock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+ value = readq(base + FME_FIRST_ERROR);
|
|
Oliver Neukum |
a46fd7 |
+ mutex_unlock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ return sprintf(buf, "0x%llx\n", (unsigned long long)value);
|
|
Oliver Neukum |
a46fd7 |
+}
|
|
Oliver Neukum |
a46fd7 |
+static DEVICE_ATTR_RO(first_error);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static ssize_t next_error_show(struct device *dev,
|
|
Oliver Neukum |
a46fd7 |
+ struct device_attribute *attr, char *buf)
|
|
Oliver Neukum |
a46fd7 |
+{
|
|
Oliver Neukum |
a46fd7 |
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
|
|
Oliver Neukum |
a46fd7 |
+ void __iomem *base;
|
|
Oliver Neukum |
a46fd7 |
+ u64 value;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ mutex_lock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+ value = readq(base + FME_NEXT_ERROR);
|
|
Oliver Neukum |
a46fd7 |
+ mutex_unlock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ return sprintf(buf, "0x%llx\n", (unsigned long long)value);
|
|
Oliver Neukum |
a46fd7 |
+}
|
|
Oliver Neukum |
a46fd7 |
+static DEVICE_ATTR_RO(next_error);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static struct attribute *fme_global_err_attrs[] = {
|
|
Oliver Neukum |
a46fd7 |
+ &dev_attr_pcie0_errors.attr,
|
|
Oliver Neukum |
a46fd7 |
+ &dev_attr_pcie1_errors.attr,
|
|
Oliver Neukum |
a46fd7 |
+ &dev_attr_nonfatal_errors.attr,
|
|
Oliver Neukum |
a46fd7 |
+ &dev_attr_catfatal_errors.attr,
|
|
Oliver Neukum |
a46fd7 |
+ &dev_attr_inject_errors.attr,
|
|
Oliver Neukum |
a46fd7 |
+ &dev_attr_fme_errors.attr,
|
|
Oliver Neukum |
a46fd7 |
+ &dev_attr_first_error.attr,
|
|
Oliver Neukum |
a46fd7 |
+ &dev_attr_next_error.attr,
|
|
Oliver Neukum |
a46fd7 |
+ NULL,
|
|
Oliver Neukum |
a46fd7 |
+};
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static umode_t fme_global_err_attrs_visible(struct kobject *kobj,
|
|
Oliver Neukum |
a46fd7 |
+ struct attribute *attr, int n)
|
|
Oliver Neukum |
a46fd7 |
+{
|
|
Oliver Neukum |
a46fd7 |
+ struct device *dev = kobj_to_dev(kobj);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ /*
|
|
Oliver Neukum |
a46fd7 |
+ * sysfs entries are visible only if related private feature is
|
|
Oliver Neukum |
a46fd7 |
+ * enumerated.
|
|
Oliver Neukum |
a46fd7 |
+ */
|
|
Oliver Neukum |
a46fd7 |
+ if (!dfl_get_feature_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR))
|
|
Oliver Neukum |
a46fd7 |
+ return 0;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ return attr->mode;
|
|
Oliver Neukum |
a46fd7 |
+}
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+const struct attribute_group fme_global_err_group = {
|
|
Oliver Neukum |
a46fd7 |
+ .name = "errors",
|
|
Oliver Neukum |
a46fd7 |
+ .attrs = fme_global_err_attrs,
|
|
Oliver Neukum |
a46fd7 |
+ .is_visible = fme_global_err_attrs_visible,
|
|
Oliver Neukum |
a46fd7 |
+};
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static void fme_err_mask(struct device *dev, bool mask)
|
|
Oliver Neukum |
a46fd7 |
+{
|
|
Oliver Neukum |
a46fd7 |
+ struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
|
|
Oliver Neukum |
a46fd7 |
+ void __iomem *base;
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ mutex_lock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ /* Workaround: keep MBP_ERROR always masked if revision is 0 */
|
|
Oliver Neukum |
a46fd7 |
+ if (dfl_feature_revision(base))
|
|
Oliver Neukum |
a46fd7 |
+ writeq(mask ? ERROR_MASK : 0, base + FME_ERROR_MASK);
|
|
Oliver Neukum |
a46fd7 |
+ else
|
|
Oliver Neukum |
a46fd7 |
+ writeq(mask ? ERROR_MASK : MBP_ERROR, base + FME_ERROR_MASK);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ writeq(mask ? ERROR_MASK : 0, base + PCIE0_ERROR_MASK);
|
|
Oliver Neukum |
a46fd7 |
+ writeq(mask ? ERROR_MASK : 0, base + PCIE1_ERROR_MASK);
|
|
Oliver Neukum |
a46fd7 |
+ writeq(mask ? ERROR_MASK : 0, base + RAS_NONFAT_ERROR_MASK);
|
|
Oliver Neukum |
a46fd7 |
+ writeq(mask ? ERROR_MASK : 0, base + RAS_CATFAT_ERROR_MASK);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ mutex_unlock(&pdata->lock);
|
|
Oliver Neukum |
a46fd7 |
+}
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static int fme_global_err_init(struct platform_device *pdev,
|
|
Oliver Neukum |
a46fd7 |
+ struct dfl_feature *feature)
|
|
Oliver Neukum |
a46fd7 |
+{
|
|
Oliver Neukum |
a46fd7 |
+ fme_err_mask(&pdev->dev, false);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+ return 0;
|
|
Oliver Neukum |
a46fd7 |
+}
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static void fme_global_err_uinit(struct platform_device *pdev,
|
|
Oliver Neukum |
a46fd7 |
+ struct dfl_feature *feature)
|
|
Oliver Neukum |
a46fd7 |
+{
|
|
Oliver Neukum |
a46fd7 |
+ fme_err_mask(&pdev->dev, true);
|
|
Oliver Neukum |
a46fd7 |
+}
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+const struct dfl_feature_id fme_global_err_id_table[] = {
|
|
Oliver Neukum |
a46fd7 |
+ {.id = FME_FEATURE_ID_GLOBAL_ERR,},
|
|
Oliver Neukum |
a46fd7 |
+ {0,}
|
|
Oliver Neukum |
a46fd7 |
+};
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+const struct dfl_feature_ops fme_global_err_ops = {
|
|
Oliver Neukum |
a46fd7 |
+ .init = fme_global_err_init,
|
|
Oliver Neukum |
a46fd7 |
+ .uinit = fme_global_err_uinit,
|
|
Oliver Neukum |
a46fd7 |
+};
|
|
Oliver Neukum |
a46fd7 |
--- a/drivers/fpga/dfl-fme-main.c
|
|
Oliver Neukum |
a46fd7 |
+++ b/drivers/fpga/dfl-fme-main.c
|
|
Oliver Neukum |
51e148 |
@@ -127,7 +127,10 @@ static struct attribute *fme_hdr_attrs[]
|
|
Oliver Neukum |
a46fd7 |
&dev_attr_socket_id.attr,
|
|
Oliver Neukum |
a46fd7 |
NULL,
|
|
Oliver Neukum |
a46fd7 |
};
|
|
Oliver Neukum |
a46fd7 |
-ATTRIBUTE_GROUPS(fme_hdr);
|
|
Oliver Neukum |
a46fd7 |
+
|
|
Oliver Neukum |
a46fd7 |
+static const struct attribute_group fme_hdr_group = {
|
|
Oliver Neukum |
a46fd7 |
+ .attrs = fme_hdr_attrs,
|
|
Oliver Neukum |
a46fd7 |
+};
|
|
Oliver Neukum |
a46fd7 |
|
|
Oliver Neukum |
a46fd7 |
static long fme_hdr_ioctl_release_port(struct dfl_feature_platform_data *pdata,
|
|
Oliver Neukum |
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unsigned long arg)
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@@ -188,6 +191,10 @@ static struct dfl_feature_driver fme_fea
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.ops = &fme_pr_mgmt_ops,
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},
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{
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+ .id_table = fme_global_err_id_table,
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+ .ops = &fme_global_err_ops,
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+ },
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+ {
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.ops = NULL,
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},
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};
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51e148 |
@@ -333,10 +340,16 @@ static int fme_remove(struct platform_de
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Oliver Neukum |
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return 0;
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}
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+static const struct attribute_group *fme_dev_groups[] = {
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+ &fme_hdr_group,
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+ &fme_global_err_group,
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+ NULL
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+};
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+
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static struct platform_driver fme_driver = {
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.driver = {
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.name = DFL_FPGA_FEATURE_DEV_FME,
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- .dev_groups = fme_hdr_groups,
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+ .dev_groups = fme_dev_groups,
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},
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.probe = fme_probe,
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.remove = fme_remove,
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--- a/drivers/fpga/dfl-fme.h
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+++ b/drivers/fpga/dfl-fme.h
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@@ -35,5 +35,8 @@ struct dfl_fme {
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extern const struct dfl_feature_ops fme_pr_mgmt_ops;
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extern const struct dfl_feature_id fme_pr_mgmt_id_table[];
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+extern const struct dfl_feature_ops fme_global_err_ops;
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+extern const struct dfl_feature_id fme_global_err_id_table[];
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+extern const struct attribute_group fme_global_err_group;
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#endif /* __DFL_FME_H */
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--- a/drivers/fpga/dfl.h
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+++ b/drivers/fpga/dfl.h
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51e148 |
@@ -355,6 +355,11 @@ static inline bool dfl_feature_is_port(v
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51e148 |
(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
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}
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Oliver Neukum |
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+static inline u8 dfl_feature_revision(void __iomem *base)
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+{
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+ return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));
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+}
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+
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/**
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* struct dfl_fpga_enum_info - DFL FPGA enumeration information
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*
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