From a263456f0e27ec2f00d25119757f4d4bd656b2e9 Mon Sep 17 00:00:00 2001

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Date: Sun, 8 May 2022 18:55:47 +0100

Subject: [PATCH] iio: accel: sca3000: Fix alignment for DMA safety

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Git-commit: a263456f0e27ec2f00d25119757f4d4bd656b2e9

Patch-mainline: v6.0-rc1

References: git-fixes

____cacheline_aligned is insufficient guarantee for non-coherent DMA.

Switch to the updated IIO_DMA_MINALIGN definition.

The second alignment marking is left in place to avoid doing more than

the simple fix in this patch.

Fixes: ced5c03d360ae ("staging:iio:accel:sca3000 merge files into one.")

Fixes: 152a6a884ae13 ("staging:iio:accel:sca3000 move to hybrid hard / soft buffer design.")

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Acked-by: Nuno Sá <nuno.sa@analog.com>

Link: https://lore.kernel.org/r/20220508175712.647246-8-jic23@kernel.org

Acked-by: Takashi Iwai <tiwai@suse.de>

---

 drivers/iio/accel/sca3000.c | 4 ++--

 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/accel/sca3000.c b/drivers/iio/accel/sca3000.c

index 08dedee76e46..87c54e41f6cc 100644

--- a/drivers/iio/accel/sca3000.c

+++ b/drivers/iio/accel/sca3000.c

@@ -167,8 +167,8 @@ struct sca3000_state {

 	int				mo_det_use_count;

 	struct mutex			lock;

 	/* Can these share a cacheline ? */

-	u8				rx[384] ____cacheline_aligned;

-	u8				tx[6] ____cacheline_aligned;

+	u8				rx[384] __aligned(IIO_DMA_MINALIGN);

+	u8				tx[6] __aligned(IIO_DMA_MINALIGN);

 };

 /**

-- 

2.35.3