From e66bf04797f1f95a2402414c00e64d00f63d31ec Mon Sep 17 00:00:00 2001

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Date: Sun, 8 May 2022 18:56:40 +0100

Subject: [PATCH] iio: dac: mcp4922: Fix alignment for DMA safety

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Git-commit: e66bf04797f1f95a2402414c00e64d00f63d31ec

Patch-mainline: v6.0-rc1

References: git-fixes

____cacheline_aligned is an insufficient guarantee for non-coherent DMA

on platforms with 128 byte cachelines above L1.  Switch to the updated

IIO_DMA_MINALIGN definition.

Fixes: 1b791fadf3a1 ("iio: dac: mcp4902/mcp4912/mcp4922 dac driver")

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Acked-by: Nuno Sá <nuno.sa@analog.com>

Acked-by: Michael Welling <mwelling@ieee.org>

Link: https://lore.kernel.org/r/20220508175712.647246-61-jic23@kernel.org

Acked-by: Takashi Iwai <tiwai@suse.de>

---

 drivers/iio/dac/mcp4922.c | 2 +-

 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/dac/mcp4922.c b/drivers/iio/dac/mcp4922.c

index cb9e60e71b91..6c0e31032c57 100644

--- a/drivers/iio/dac/mcp4922.c

+++ b/drivers/iio/dac/mcp4922.c

@@ -29,7 +29,7 @@ struct mcp4922_state {

 	unsigned int value[MCP4922_NUM_CHANNELS];

 	unsigned int vref_mv;

 	struct regulator *vref_reg;

-	u8 mosi[2] ____cacheline_aligned;

+	u8 mosi[2] __aligned(IIO_DMA_MINALIGN);

 };

 #define MCP4922_CHAN(chan, bits) {			\

-- 

2.35.3