From 554232e8d59f3df842fdd9cc68a22e827b286d52 Mon Sep 17 00:00:00 2001

From: Jisheng Zhang <Jisheng.Zhang@synaptics.com>

Date: Wed, 13 May 2020 18:26:02 +0800

Subject: [PATCH] mmc: sdhci-of-dwcmshc: implement specific set_uhs_signaling

Git-commit: 554232e8d59f3df842fdd9cc68a22e827b286d52

References: git-fixes

Patch-mainline: v5.8-rc1

We need a different set_uhs_signaling implementation for

MMC_TIMING_MMC_HS and MMC_TIMING_MMC_HS400.

Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>

Link: https://lore.kernel.org/r/20200513182602.3636a551@xhacker.debian

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

Signed-off-by: Oliver Neukum <oneukum@suse.com>

---

 drivers/mmc/host/sdhci-of-dwcmshc.c | 31 ++++++++++++++++++++++++++++-

 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c

index a5137845a1c7..a9ed0e006e06 100644

--- a/drivers/mmc/host/sdhci-of-dwcmshc.c

+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c

@@ -16,6 +16,9 @@

 #include "sdhci-pltfm.h"

+/* DWCMSHC specific Mode Select value */

+#define DWCMSHC_CTRL_HS400		0x7

+

 #define BOUNDARY_OK(addr, len) \

 	((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))

@@ -46,10 +49,36 @@ static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,

 	sdhci_adma_write_desc(host, desc, addr, len, cmd);

 }

+static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,

+				      unsigned int timing)

+{

+	u16 ctrl_2;

+

+	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);

+	/* Select Bus Speed Mode for host */

+	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;

+	if ((timing == MMC_TIMING_MMC_HS200) ||

+	    (timing == MMC_TIMING_UHS_SDR104))

+		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;

+	else if (timing == MMC_TIMING_UHS_SDR12)

+		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;

+	else if ((timing == MMC_TIMING_UHS_SDR25) ||

+		 (timing == MMC_TIMING_MMC_HS))

+		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;

+	else if (timing == MMC_TIMING_UHS_SDR50)

+		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;

+	else if ((timing == MMC_TIMING_UHS_DDR50) ||

+		 (timing == MMC_TIMING_MMC_DDR52))

+		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;

+	else if (timing == MMC_TIMING_MMC_HS400)

+		ctrl_2 |= DWCMSHC_CTRL_HS400;

+	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);

+}

+

 static const struct sdhci_ops sdhci_dwcmshc_ops = {

 	.set_clock		= sdhci_set_clock,

 	.set_bus_width		= sdhci_set_bus_width,

-	.set_uhs_signaling	= sdhci_set_uhs_signaling,

+	.set_uhs_signaling	= dwcmshc_set_uhs_signaling,

 	.get_max_clock		= sdhci_pltfm_clk_get_max_clock,

 	.reset			= sdhci_reset,

 	.adma_write_desc	= dwcmshc_adma_write_desc,

-- 

2.26.2