From: Hao Chen <chenhao288@hisilicon.com>

Date: Sat, 28 Aug 2021 14:55:21 +0800

Subject: net: hns3: add required space in comment

Patch-mainline: v5.15-rc1

Git-commit: 0cb0704149f0d9d3b7c68ebab932fc27222c740b

References: bsc#1190336

Add some required spaces in comment for cleanup.

Signed-off-by: Hao Chen <chenhao288@hisilicon.com>

Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>

Signed-off-by: David S. Miller <davem@davemloft.net>

Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>

---

 drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h         |    2 +-

 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h         |    2 +-

 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h  |    2 +-

 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c |    2 +-

 4 files changed, 4 insertions(+), 4 deletions(-)

--- a/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h

+++ b/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h

@@ -9,7 +9,7 @@

 enum HCLGE_MBX_OPCODE {

 	HCLGE_MBX_RESET = 0x01,		/* (VF -> PF) assert reset */

-	HCLGE_MBX_ASSERTING_RESET,	/* (PF -> VF) PF is asserting reset*/

+	HCLGE_MBX_ASSERTING_RESET,	/* (PF -> VF) PF is asserting reset */

 	HCLGE_MBX_SET_UNICAST,		/* (VF -> PF) set UC addr */

 	HCLGE_MBX_SET_MULTICAST,	/* (VF -> PF) set MC addr */

 	HCLGE_MBX_SET_VLAN,		/* (VF -> PF) set VLAN */

--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h

+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h

@@ -348,7 +348,7 @@ enum hns3_pkt_l3type {

 	HNS3_L3_TYPE_LLDP,

 	HNS3_L3_TYPE_BPDU,

 	HNS3_L3_TYPE_MAC_PAUSE,

-	HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/

+	HNS3_L3_TYPE_PFC_PAUSE, /* 0x9 */

 	/* reserved for 0xA~0xB */

--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

@@ -453,7 +453,7 @@ struct hclge_tc_thrd {

 };

 struct hclge_priv_buf {

-	struct hclge_waterline wl;	/* Waterline for low and high*/

+	struct hclge_waterline wl;	/* Waterline for low and high */

 	u32 buf_size;	/* TC private buffer size */

 	u32 tx_buf_size;

 	u32 enable;	/* Enable TC private buffer or not */

--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

@@ -3421,7 +3421,7 @@ static irqreturn_t hclge_misc_irq_handle

 	hclge_enable_vector(&hdev->misc_vector, false);

 	event_cause = hclge_check_event_cause(hdev, &clearval);

-	/* vector 0 interrupt is shared with reset and mailbox source events.*/

+	/* vector 0 interrupt is shared with reset and mailbox source events. */

 	switch (event_cause) {

 	case HCLGE_VECTOR0_EVENT_ERR:

 		hclge_errhand_task_schedule(hdev);