d0452d
From 2d6a88d8a4fbabb2b03286a61cbdd66eda38bc04 Mon Sep 17 00:00:00 2001
d0452d
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
d0452d
Date: Sun, 15 Nov 2020 17:57:57 +0100
d0452d
Subject: [PATCH 01/14] net: lantiq: Wait for the GPHY firmware to be ready
d0452d
Git-commit: 2a1828e378c1b5ba1ff283ed8f8c5cc37bb391dc
d0452d
Patch-mainline: v5.10-rc5
d0452d
References: git-fixes
d0452d
d0452d
A user reports (slightly shortened from the original message):
d0452d
  libphy: lantiq,xrx200-mdio: probed
d0452d
  mdio_bus 1e108000.switch-mii: MDIO device at address 17 is missing.
d0452d
  gswip 1e108000.switch lan: no phy at 2
d0452d
  gswip 1e108000.switch lan: failed to connect to port 2: -19
d0452d
  lantiq,xrx200-net 1e10b308.eth eth0: error -19 setting up slave phy
d0452d
d0452d
This is a single-port board using the internal Fast Ethernet PHY. The
d0452d
user reports that switching to PHY scanning instead of configuring the
d0452d
PHY within device-tree works around this issue.
d0452d
d0452d
The documentation for the standalone variant of the PHY11G (which is
d0452d
probably very similar to what is used inside the xRX200 SoCs but having
d0452d
the firmware burnt onto that standalone chip in the factory) states that
d0452d
the PHY needs 300ms to be ready for MDIO communication after releasing
d0452d
the reset.
d0452d
d0452d
Add a 300ms delay after initializing all GPHYs to ensure that the GPHY
d0452d
firmware had enough time to initialize and to appear on the MDIO bus.
d0452d
Unfortunately there is no (known) documentation on what the minimum time
d0452d
to wait after releasing the reset on an internal PHY so play safe and
d0452d
take the one for the external variant. Only wait after the last GPHY
d0452d
firmware is loaded to not slow down the initialization too much (
d0452d
xRX200 has two GPHYs but newer SoCs have at least three GPHYs).
d0452d
d0452d
Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
d0452d
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
d0452d
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
d0452d
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
d0452d
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
d0452d
Link: https://lore.kernel.org/r/20201115165757.552641-1-martin.blumenstingl@googlemail.com
d0452d
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
d0452d
Signed-off-by: Denis Kirjanov <denis.kirjanov@suse.com>
d0452d
---
d0452d
 drivers/net/dsa/lantiq_gswip.c | 11 +++++++++++
d0452d
 1 file changed, 11 insertions(+)
d0452d
d0452d
diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c
d0452d
index ecaa6690f159..4b69f782f8e3 100644
d0452d
--- a/drivers/net/dsa/lantiq_gswip.c
d0452d
+++ b/drivers/net/dsa/lantiq_gswip.c
d0452d
@@ -26,6 +26,7 @@
d0452d
  */
d0452d
 
d0452d
 #include <linux/clk.h>
d0452d
+#include <linux/delay.h>
d0452d
 #include <linux/etherdevice.h>
d0452d
 #include <linux/firmware.h>
d0452d
 #include <linux/if_bridge.h>
d0452d
@@ -1812,6 +1813,16 @@ static int gswip_gphy_fw_list(struct gswip_priv *priv,
d0452d
 		i++;
d0452d
 	}
d0452d
 
d0452d
+	/* The standalone PHY11G requires 300ms to be fully
d0452d
+	 * initialized and ready for any MDIO communication after being
d0452d
+	 * taken out of reset. For the SoC-internal GPHY variant there
d0452d
+	 * is no (known) documentation for the minimum time after a
d0452d
+	 * reset. Use the same value as for the standalone variant as
d0452d
+	 * some users have reported internal PHYs not being detected
d0452d
+	 * without any delay.
d0452d
+	 */
d0452d
+	msleep(300);
d0452d
+
d0452d
 	return 0;
d0452d
 
d0452d
 remove_gphy:
d0452d
-- 
d0452d
2.16.4
d0452d