Blame patches.suse/net-mlx5-Fix-PPLM-register-mapping.patch
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Thomas Bogendoerfer |
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From: Aya Levin <ayal@nvidia.com>
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Thomas Bogendoerfer |
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Date: Sun, 4 Apr 2021 10:50:50 +0300
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Subject: net/mlx5: Fix PPLM register mapping
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Patch-mainline: v5.12-rc7
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Git-commit: ce28f0fd670ddffcd564ce7119bdefbaf08f02d3
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References: jsc#SLE-8464
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Add reserved mapping to cover all the register in order to avoid
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setting arbitrary values to newer FW which implements the reserved
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fields.
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Fixes: a58837f52d43 ("net/mlx5e: Expose FEC feilds and related capability bit")
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Signed-off-by: Aya Levin <ayal@nvidia.com>
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Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
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Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
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---
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include/linux/mlx5/mlx5_ifc.h | 2 ++
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1 file changed, 2 insertions(+)
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--- a/include/linux/mlx5/mlx5_ifc.h
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+++ b/include/linux/mlx5/mlx5_ifc.h
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@@ -8620,6 +8620,8 @@ struct mlx5_ifc_pplm_reg_bits {
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u8 fec_override_admin_100g_2x[0x10];
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u8 fec_override_admin_50g_1x[0x10];
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+
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+ u8 reserved_at_140[0x140];
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};
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struct mlx5_ifc_ppcnt_reg_bits {
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