From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Date: Thu, 3 Oct 2019 13:57:29 +0200

Subject: nvme: retain split access workaround for capability reads

Patch-mainline: v5.4-rc4

Git-commit: 3a8ecc935efabdad106b5e06d07b150c394b4465

References: git-fixes

Commit 7fd8930f26be4

  "nvme: add a common helper to read Identify Controller data"

has re-introduced an issue that we have attempted to work around in the

past, in commit a310acd7a7ea ("NVMe: use split lo_hi_{read,write}q").

The problem is that some PCIe NVMe controllers do not implement 64-bit

outbound accesses correctly, which is why the commit above switched

to using lo_hi_[read|write]q for all 64-bit BAR accesses occuring in

the code.

In the mean time, the NVMe subsystem has been refactored, and now calls

into the PCIe support layer for NVMe via a .reg_read64() method, which

fails to use lo_hi_readq(), and thus reintroduces the problem that the

workaround above aimed to address.

Given that, at the moment, .reg_read64() is only used to read the

capability register [which is known to tolerate split reads], let's

switch .reg_read64() to lo_hi_readq() as well.

This fixes a boot issue on some ARM boxes with NVMe behind a Synopsys

DesignWare PCIe host controller.

Fixes: 7fd8930f26be4 ("nvme: add a common helper to read Identify Controller data")

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Signed-off-by: Sagi Grimberg <sagi@grimberg.me>

Acked-by: Daniel Wagner <dwagner@suse.de>

---

 drivers/nvme/host/pci.c |    2 +-

 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/nvme/host/pci.c

+++ b/drivers/nvme/host/pci.c

@@ -2381,7 +2381,7 @@ static int nvme_pci_reg_write32(struct n

 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)

 {

-	*val = readq(to_nvme_dev(ctrl)->bar + off);

+	*val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);

 	return 0;

 }