From: Naveen Mamindlapalli <naveenm@marvell.com>

Date: Sat, 10 Sep 2022 13:24:13 +0530

Subject: octeontx2-af: return correct ptp timestamp for CN10K silicon

Patch-mainline: v6.1-rc1

Git-commit: a8025e7946a2b18c4ac17b36fde528d2f6262bdd

References: jsc#SLE-24682

The MIO_PTP_TIMESTAMP format has been changed in CN10K silicon

family. The upper 32-bits represents seconds and lower 32-bits

represents nanoseconds. This patch returns nanosecond timestamp

to NIX PF driver.

Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>

Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>

Signed-off-by: David S. Miller <davem@davemloft.net>

Acked-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>

---

 drivers/net/ethernet/marvell/octeontx2/af/ptp.c |   14 +++++++++++++-

 1 file changed, 13 insertions(+), 1 deletion(-)

--- a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c

+++ b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c

@@ -56,6 +56,11 @@

 static struct ptp *first_ptp_block;

 static const struct pci_device_id ptp_id_table[];

+static bool is_ptp_dev_cn10k(struct ptp *ptp)

+{

+	return (ptp->pdev->device == PCI_DEVID_CN10K_PTP) ? true : false;

+}

+

 static bool cn10k_ptp_errata(struct ptp *ptp)

 {

 	if (ptp->pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A_PTP ||

@@ -282,7 +287,14 @@ void ptp_start(struct ptp *ptp, u64 sclk

 static int ptp_get_tstmp(struct ptp *ptp, u64 *clk)

 {

-	*clk = readq(ptp->reg_base + PTP_TIMESTAMP);

+	u64 timestamp;

+

+	if (is_ptp_dev_cn10k(ptp)) {

+		timestamp = readq(ptp->reg_base + PTP_TIMESTAMP);

+		*clk = (timestamp >> 32) * NSEC_PER_SEC + (timestamp & 0xFFFFFFFF);

+	} else {

+		*clk = readq(ptp->reg_base + PTP_TIMESTAMP);

+	}

 	return 0;

 }