From: Kan Liang <kan.liang@linux.intel.com>

Date: Wed, 29 Jun 2022 08:08:40 -0700

Subject: perf/x86/intel: Fix PEBS data source encoding for ADL

Git-commit: ccf170e9d8fdacfe435bbe3749c897c7d86d32f8

Patch-mainline: v6.0-rc1

References: jsc#PED-1063, jsc#PED-1752

The PEBS data source encoding for the e-core is different from the

p-core.

Add the pebs_data_source[] in the struct x86_hybrid_pmu to store the

data source encoding for each type of the core.

Add intel_pmu_pebs_data_source_grt() for the e-core.

There is nothing changed for the data source encoding of the p-core,

which still reuse the intel_pmu_pebs_data_source_skl().

Fixes: f83d2f91d259 ("perf/x86/intel: Add Alder Lake Hybrid support")

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>

Reviewed-by: Andi Kleen <ak@linux.intel.com>

Link: https://lkml.kernel.org/r/20220629150840.2235741-2-kan.liang@linux.intel.com

Signed-off-by: Tony Jones <tonyj@suse.de>

---

 arch/x86/events/intel/core.c |  2 +-

 arch/x86/events/intel/ds.c   | 51 +++++++++++++++++++++++++++++++++-----------

 arch/x86/events/perf_event.h |  6 ++++++

 3 files changed, 45 insertions(+), 14 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c

index 07d4a5f20321..bd8b98857609 100644

--- a/arch/x86/events/intel/core.c

+++ b/arch/x86/events/intel/core.c

@@ -6241,7 +6241,7 @@ __init int intel_pmu_init(void)

 		x86_pmu.flags |= PMU_FL_INSTR_LATENCY;

 		x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;

 		x86_pmu.lbr_pt_coexist = true;

-		intel_pmu_pebs_data_source_skl(false);

+		intel_pmu_pebs_data_source_adl();

 		x86_pmu.pebs_latency_data = adl_latency_data_small;

 		x86_pmu.num_topdown_events = 8;

 		x86_pmu.update_topdown_event = adl_update_topdown_event;

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c

index de84385de414..ba60427caa6d 100644

--- a/arch/x86/events/intel/ds.c

+++ b/arch/x86/events/intel/ds.c

@@ -94,15 +94,40 @@ void __init intel_pmu_pebs_data_source_nhm(void)

 	pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);

 }

-void __init intel_pmu_pebs_data_source_skl(bool pmem)

+static void __init __intel_pmu_pebs_data_source_skl(bool pmem, u64 *data_source)

 {

 	u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4);

-	pebs_data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);

-	pebs_data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);

-	pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);

-	pebs_data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD);

-	pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);

+	data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);

+	data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);

+	data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);

+	data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD);

+	data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);

+}

+

+void __init intel_pmu_pebs_data_source_skl(bool pmem)

+{

+	__intel_pmu_pebs_data_source_skl(pmem, pebs_data_source);

+}

+

+static void __init intel_pmu_pebs_data_source_grt(u64 *data_source)

+{

+	data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);

+	data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);

+	data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);

+}

+

+void __init intel_pmu_pebs_data_source_adl(void)

+{

+	u64 *data_source;

+

+	data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source;

+	memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));

+	__intel_pmu_pebs_data_source_skl(false, data_source);

+

+	data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;

+	memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));

+	intel_pmu_pebs_data_source_grt(data_source);

 }

 static u64 precise_store_data(u64 status)

@@ -198,7 +223,7 @@ u64 adl_latency_data_small(struct perf_event *event, u64 status)

 	dse.val = status;

-	val = pebs_data_source[dse.ld_dse];

+	val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse];

 	/*

 	 * For the atom core on ADL,

@@ -214,7 +239,7 @@ u64 adl_latency_data_small(struct perf_event *event, u64 status)

 	return val;

 }

-static u64 load_latency_data(u64 status)

+static u64 load_latency_data(struct perf_event *event, u64 status)

 {

 	union intel_x86_pebs_dse dse;

 	u64 val;

@@ -224,7 +249,7 @@ static u64 load_latency_data(u64 status)

 	/*

 	 * use the mapping table for bit 0-3

 	 */

-	val = pebs_data_source[dse.ld_dse];

+	val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse];

 	/*

 	 * Nehalem models do not support TLB, Lock infos

@@ -263,7 +288,7 @@ static u64 load_latency_data(u64 status)

 	return val;

 }

-static u64 store_latency_data(u64 status)

+static u64 store_latency_data(struct perf_event *event, u64 status)

 {

 	union intel_x86_pebs_dse dse;

 	u64 val;

@@ -273,7 +298,7 @@ static u64 store_latency_data(u64 status)

 	/*

 	 * use the mapping table for bit 0-3

 	 */

-	val = pebs_data_source[dse.st_lat_dse];

+	val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse];

 	pebs_set_tlb_lock(&val, dse.st_lat_stlb_miss, dse.st_lat_locked);

@@ -1459,9 +1484,9 @@ static u64 get_data_src(struct perf_event *event, u64 aux)

 	bool fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);

 	if (fl & PERF_X86_EVENT_PEBS_LDLAT)

-		val = load_latency_data(aux);

+		val = load_latency_data(event, aux);

 	else if (fl & PERF_X86_EVENT_PEBS_STLAT)

-		val = store_latency_data(aux);

+		val = store_latency_data(event, aux);

 	else if (fl & PERF_X86_EVENT_PEBS_LAT_HYBRID)

 		val = x86_pmu.pebs_latency_data(event, aux);

 	else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h

index 2d11445e158c..ca2f8bfe6ff1 100644

--- a/arch/x86/events/perf_event.h

+++ b/arch/x86/events/perf_event.h

@@ -644,6 +644,8 @@ enum {

 	x86_lbr_exclusive_max,

 };

+#define PERF_PEBS_DATA_SOURCE_MAX	0x10

+

 struct x86_hybrid_pmu {

 	struct pmu			pmu;

 	const char			*name;

@@ -671,6 +673,8 @@ struct x86_hybrid_pmu {

 	unsigned int			late_ack	:1,

 					mid_ack		:1,

 					enabled_ack	:1;

+

+	u64				pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX];

 };

 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu)

@@ -1508,6 +1512,8 @@ void intel_pmu_pebs_data_source_nhm(void);

 void intel_pmu_pebs_data_source_skl(bool pmem);

+void intel_pmu_pebs_data_source_adl(void);

+

 int intel_pmu_setup_lbr_filter(struct perf_event *event);

 void intel_pt_interrupt(void);