From 6989ea4881c8944fbf04378418bb1af63d875ef8 Mon Sep 17 00:00:00 2001

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Date: Fri, 25 Nov 2022 00:29:26 +0200

Subject: [PATCH] pinctrl: intel: Save and restore pins in "direct IRQ" mode

Git-commit: 6989ea4881c8944fbf04378418bb1af63d875ef8

Patch-mainline: v6.1-rc8

References: git-fixes

The firmware on some systems may configure GPIO pins to be

an interrupt source in so called "direct IRQ" mode. In such

cases the GPIO controller driver has no idea if those pins

are being used or not. At the same time, there is a known bug

in the firmwares that don't restore the pin settings correctly

after suspend, i.e. by an unknown reason the Rx value becomes

inverted.

Hence, let's save and restore the pins that are configured

as GPIOs in the input mode with GPIROUTIOXAPIC bit set.

Cc: stable@vger.kernel.org

Reported-and-tested-by: Dale Smith <dalepsmith@gmail.com>

Reported-and-tested-by: John Harris <jmharris@gmail.com>

Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=214749

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>

Link: https://lore.kernel.org/r/20221124222926.72326-1-andriy.shevchenko@linux.intel.com

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Acked-by: Takashi Iwai <tiwai@suse.de>

---

 drivers/pinctrl/intel/pinctrl-intel.c | 27 ++++++++++++++++++++++++++-

 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c

index 52ecd66ce357..047a8374b4fd 100644

--- a/drivers/pinctrl/intel/pinctrl-intel.c

+++ b/drivers/pinctrl/intel/pinctrl-intel.c

@@ -436,9 +436,14 @@ static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)

 	writel(value, padcfg0);

 }

+static int __intel_gpio_get_gpio_mode(u32 value)

+{

+	return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;

+}

+

 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)

 {

-	return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;

+	return __intel_gpio_get_gpio_mode(readl(padcfg0));

 }

 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)

@@ -1674,6 +1679,7 @@ EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data);

 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)

 {

 	const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);

+	u32 value;

 	if (!pd || !intel_pad_usable(pctrl, pin))

 		return false;

@@ -1688,6 +1694,25 @@ static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int

 	    gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))

 		return true;

+	/*

+	 * The firmware on some systems may configure GPIO pins to be

+	 * an interrupt source in so called "direct IRQ" mode. In such

+	 * cases the GPIO controller driver has no idea if those pins

+	 * are being used or not. At the same time, there is a known bug

+	 * in the firmwares that don't restore the pin settings correctly

+	 * after suspend, i.e. by an unknown reason the Rx value becomes

+	 * inverted.

+	 *

+	 * Hence, let's save and restore the pins that are configured

+	 * as GPIOs in the input mode with GPIROUTIOXAPIC bit set.

+	 *

+	 * See https://bugzilla.kernel.org/show_bug.cgi?id=214749.

+	 */

+	value = readl(intel_get_padcfg(pctrl, pin, PADCFG0));

+	if ((value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&

+	    (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO))

+		return true;

+

 	return false;

 }

-- 

2.35.3