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From 87c614175bbf28d3fd076dc2d166bac759e41427 Mon Sep 17 00:00:00 2001
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From: Kevin Groeneveld <kgroeneveld@lenbrook.com>
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Date: Sat, 18 Mar 2023 18:21:32 -0400
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Subject: [PATCH] spi: spi-imx: fix MX51_ECSPI_* macros when cs > 3
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Mime-version: 1.0
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Content-type: text/plain; charset=UTF-8
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Content-transfer-encoding: 8bit
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Git-commit: 87c614175bbf28d3fd076dc2d166bac759e41427
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Patch-mainline: v6.4-rc1
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References: git-fixes
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When using gpio based chip select the cs value can go outside the range
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0 – 3. The various MX51_ECSPI_* macros did not take this into consideration
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resulting in possible corruption of the configuration.
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For example for any cs value over 3 the SCLKPHA bits would not be set and
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other values in the register possibly corrupted.
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One way to fix this is to just mask the cs bits to 2 bits. This still
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allows all 4 native chip selects to work as well as gpio chip selects
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(which can use any of the 4 chip select configurations).
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Signed-off-by: Kevin Groeneveld <kgroeneveld@lenbrook.com>
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Link: https://lore.kernel.org/r/20230318222132.3373-1-kgroeneveld@lenbrook.com
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Signed-off-by: Mark Brown <broonie@kernel.org>
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Acked-by: Takashi Iwai <tiwai@suse.de>
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---
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drivers/spi/spi-imx.c | 24 ++++++++++++++++++------
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1 file changed, 18 insertions(+), 6 deletions(-)
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diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
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index 1f2c7ad65ec8..24390c702c60 100644
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--- a/drivers/spi/spi-imx.c
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+++ b/drivers/spi/spi-imx.c
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@@ -252,6 +252,18 @@ static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device
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return true;
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}
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+/*
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+ * Note the number of natively supported chip selects for MX51 is 4. Some
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+ * devices may have less actual SS pins but the register map supports 4. When
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+ * using gpio chip selects the cs values passed into the macros below can go
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+ * outside the range 0 - 3. We therefore need to limit the cs value to avoid
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+ * corrupting bits outside the allocated locations.
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+ *
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+ * The simplest way to do this is to just mask the cs bits to 2 bits. This
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+ * still allows all 4 native chip selects to work as well as gpio chip selects
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+ * (which can use any of the 4 chip select configurations).
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+ */
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+
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#define MX51_ECSPI_CTRL 0x08
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#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
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#define MX51_ECSPI_CTRL_XCH (1 << 2)
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@@ -260,16 +272,16 @@ static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device
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#define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
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#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
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#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
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-#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
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+#define MX51_ECSPI_CTRL_CS(cs) ((cs & 3) << 18)
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#define MX51_ECSPI_CTRL_BL_OFFSET 20
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#define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
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#define MX51_ECSPI_CONFIG 0x0c
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-#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
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-#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
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-#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
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-#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
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-#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
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+#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs & 3) + 0))
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+#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs & 3) + 4))
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+#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs & 3) + 8))
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+#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs & 3) + 12))
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+#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs & 3) + 20))
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#define MX51_ECSPI_INT 0x10
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#define MX51_ECSPI_INT_TEEN (1 << 0)
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--
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2.35.3
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