From: Tony Luck <tony.luck@intel.com>

Date: Mon, 11 Apr 2022 16:37:03 -0700

Subject: x86/cpu: Add new Alderlake and Raptorlake CPU model numbers

Git-commit: 3ccce9340326df40ba4462d4d2a1692b6387a68e

Patch-mainline: 5.18-rc5

References: jsc#PED-743 jsc#PED-740

Intel is subdividing the mobile segment with additional models

with the same codename. Using the Intel "N" and "P" suffices

for these will be less confusing than trying to map to some

different naming convention.

Signed-off-by: Tony Luck <tony.luck@intel.com>

Signed-off-by: Borislav Petkov <bp@suse.de>

Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>

Link: https://lore.kernel.org/r/YlS7n7Xtso9BXZA2@agluck-desk3.sc.intel.com

Signed-off-by: Jiri Slaby <jslaby@suse.cz>

---

 arch/x86/include/asm/intel-family.h |    3 +++

 1 file changed, 3 insertions(+)

--- a/arch/x86/include/asm/intel-family.h

+++ b/arch/x86/include/asm/intel-family.h

@@ -26,6 +26,7 @@

  *		_G	- parts with extra graphics on

  *		_X	- regular server parts

  *		_D	- micro server parts

+ *		_N,_P	- other mobile parts

  *

  *		Historical OPTDIFFs:

  *

@@ -107,8 +108,10 @@

 #define INTEL_FAM6_ALDERLAKE		0x97	/* Golden Cove / Gracemont */

 #define INTEL_FAM6_ALDERLAKE_L		0x9A	/* Golden Cove / Gracemont */

+#define INTEL_FAM6_ALDERLAKE_N		0xBE

 #define INTEL_FAM6_RAPTORLAKE		0xB7

+#define INTEL_FAM6_RAPTORLAKE_P		0xBA

 /* "Small Core" Processors (Atom) */