From: Peter Zijlstra <peterz@infradead.org>

Date: Tue, 14 Jun 2022 23:16:04 +0200

Subject: x86/cpu/amd: Add Spectral Chicken

Git-commit: d7caac991feeef1b871ee6988fd2c9725df09039

Patch-mainline: v5.19-rc4

References: bsc#1199657 CVE-2022-29900 CVE-2022-29901

Zen2 uarchs have an undocumented, unnamed, MSR that contains a chicken

bit for some speculation behaviour. It needs setting.

Note: very belatedly AMD released naming; it's now officially called

      MSR_AMD64_DE_CFG2 and MSR_AMD64_DE_CFG2_SUPPRESS_NOBR_PRED_BIT

      but shall remain the SPECTRAL CHICKEN.

Suggested-by: Andrew Cooper <Andrew.Cooper3@citrix.com>

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>

Signed-off-by: Borislav Petkov <bp@suse.de>

Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org>

Signed-off-by: Borislav Petkov <bp@suse.de>

---

 arch/x86/include/asm/msr-index.h |    3 +++

 arch/x86/kernel/cpu/amd.c        |   26 +++++++++++++++++++++++++-

 arch/x86/kernel/cpu/cpu.h        |    2 ++

 arch/x86/kernel/cpu/hygon.c      |    6 ++++++

 4 files changed, 36 insertions(+), 1 deletion(-)

--- a/arch/x86/include/asm/msr-index.h

+++ b/arch/x86/include/asm/msr-index.h

@@ -425,6 +425,9 @@

 /* Fam 17h MSRs */

 #define MSR_F17H_IRPERF			0xc00000e9

+#define MSR_ZEN2_SPECTRAL_CHICKEN	0xc00110e3

+#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT	BIT_ULL(1)

+

 /* Fam 16h MSRs */

 #define MSR_F16H_L2I_PERF_CTL		0xc0010230

 #define MSR_F16H_L2I_PERF_CTR		0xc0010231

--- a/arch/x86/kernel/cpu/amd.c

+++ b/arch/x86/kernel/cpu/amd.c

@@ -875,6 +875,26 @@ static void init_amd_bd(struct cpuinfo_x

 	clear_rdrand_cpuid_bit(c);

 }

+void init_spectral_chicken(struct cpuinfo_x86 *c)

+{

+	u64 value;

+

+	/*

+	 * On Zen2 we offer this chicken (bit) on the altar of Speculation.

+	 *

+	 * This suppresses speculation from the middle of a basic block, i.e. it

+	 * suppresses non-branch predictions.

+	 *

+	 * We use STIBP as a heuristic to filter out Zen2 from the rest of F17H

+	 */

+	if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) {

+		if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) {

+			value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT;

+			wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value);

+		}

+	}

+}

+

 static void init_amd_zn(struct cpuinfo_x86 *c)

 {

 	set_cpu_cap(c, X86_FEATURE_ZEN);

@@ -920,7 +940,11 @@ static void init_amd(struct cpuinfo_x86

 	case 0x12: init_amd_ln(c); break;

 	case 0x15: init_amd_bd(c); break;

 	case 0x16: init_amd_jg(c); break;

-	case 0x17: init_amd_zn(c); break;

+	case 0x17:

+		init_spectral_chicken(c);

+		init_amd_zn(c);

+	break;

+

 	}

 	/*

--- a/arch/x86/kernel/cpu/cpu.h

+++ b/arch/x86/kernel/cpu/cpu.h

@@ -60,6 +60,8 @@ extern void tsx_disable(void);

 static inline void tsx_init(void) { }

 #endif /* CONFIG_CPU_SUP_INTEL */

+extern void init_spectral_chicken(struct cpuinfo_x86 *c);

+

 extern void get_cpu_cap(struct cpuinfo_x86 *c);

 extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);

 extern void x86_spec_ctrl_setup_ap(void);

--- a/arch/x86/kernel/cpu/hygon.c

+++ b/arch/x86/kernel/cpu/hygon.c

@@ -318,6 +318,12 @@ static void init_hygon(struct cpuinfo_x8

 	/* get apicid instead of initial apic id from cpuid */

 	c->apicid = hard_smp_processor_id();

+	/*

+	 * XXX someone from Hygon needs to confirm this DTRT

+	 *

+	init_spectral_chicken(c);

+	 */

+

 	set_cpu_cap(c, X86_FEATURE_ZEN);

 	set_cpu_cap(c, X86_FEATURE_CPB);