From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>

Date: Thu, 19 May 2022 20:33:13 -0700

Subject: x86/speculation/srbds: Update SRBDS mitigation selection

Git-commit: 22cac9c677c95f3ac5c9244f8ca0afdc7c8afb19

Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git

Patch-mainline: Queued in tip for v5.19

References: bsc#1199650 CVE-2022-21166 CVE-2022-21127 CVE-2022-21123 CVE-2022-21125 CVE-2022-21180

Currently, Linux disables SRBDS mitigation on CPUs not affected by

MDS and have the TSX feature disabled. On such CPUs, secrets cannot

be extracted from CPU fill buffers using MDS or TAA. Without SRBDS

mitigation, Processor MMIO Stale Data vulnerabilities can be used to

extract RDRAND, RDSEED, and EGETKEY data.

Do not disable SRBDS mitigation by default when CPU is also affected by

Processor MMIO Stale Data vulnerabilities.

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>

Signed-off-by: Borislav Petkov <bp@suse.de>

---

 arch/x86/kernel/cpu/bugs.c | 8 +++++---

 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c

index 38853077ca58..ef4749097f42 100644

--- a/arch/x86/kernel/cpu/bugs.c

+++ b/arch/x86/kernel/cpu/bugs.c

@@ -595,11 +595,13 @@ static void __init srbds_select_mitigation(void)

 		return;

 	/*

-	 * Check to see if this is one of the MDS_NO systems supporting

-	 * TSX that are only exposed to SRBDS when TSX is enabled.

+	 * Check to see if this is one of the MDS_NO systems supporting TSX that

+	 * are only exposed to SRBDS when TSX is enabled or when CPU is affected

+	 * by Processor MMIO Stale Data vulnerability.

 	 */

 	ia32_cap = x86_read_arch_cap_msr();

-	if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM))

+	if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&

+	    !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))

 		srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;

 	else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))

 		srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;