From 25d7e99dadaa53041350a9361bfa66d0e9eed9a4 Mon Sep 17 00:00:00 2001 From: Davidlohr Bueso Date: Nov 30 2021 20:20:08 +0000 Subject: Merge branch 'SLE15-SP3' (4ae6d6f2981c) into 'SLE15-SP3-RT' - Modified -rt config. config/x86_64/rt config/x86_64/rt_debug --- diff --git a/blacklist.conf b/blacklist.conf index 2766875..06885e0 100644 --- a/blacklist.conf +++ b/blacklist.conf @@ -1077,6 +1077,7 @@ c98a76eabbb6e7755f3d4a4c33f8fe869dda6383 # The bug fixed was not backported 8749efc0c0c325bf0c948c0b11d77bd3e497ead5 # printk: just a preparation step for lockless ringbuffer. 0f7636e1654338c34e3c220c02b2ffad78b6ccc0 # printk: cosmetic; documentation 89ccf18f032f26946e2ea6258120472eec6aa745 # printk: not critical; allow to use the full buffer when using log dumpers +57116ce17b04fde2fe30f0859df69d8dbe5809f6 # printk/workqueue: very hard to hit; works well with lockless ringuffer; but it might cause wrong timestamps or even lost messages on 5.3 where using par-CPU buffers 7359608a271ce81803de148befefd309baf88c76 # CONFIG_GDB_SCRIPTS is not enabled for any config 7619517598ad5ba04beb855cde6558e72c73dbb5 # dup of fde9f39ac7f1ffd799a96ffa1e06b2051f0898f1 fd944dc24336922656a48f4608bfb41abdcdc4aa # ksz8795 is not in 5.3 yet @@ -1382,3 +1383,15 @@ c1367ee016e3550745315fb9a2dd1e4ce02cdcf6 # build warning only 6789e4b7593bc656a3e7af3e2f7c6dd9d3f41253 # usb: reverting the above b7a0a792f864583207c593b50fd1b752ed89f4c1 # xhci: reverted by stable-5.4.x 049849492b77aa0df7f7130f1d522f3553c4084b # xhci: reverting the above +5c9d706f61336d9f7f285df64c734af778c70f39 # requires 30897832d8b97e93833fb52c0a02951db3692ed2 "bpf: Allow local storage to be used from LSM programs", which is not backported +c57fe0037a4e3863d9b740f8c14df9c51ac31aa1 # net: mscc: Unmet dependencies +52849bcf0029ccc553be304e4f804938a39112e2 # net: mscc: Unmet dependencies +fba01283d85a09e0e2ef552c6e764b903111d90a # net: mscc: Unmet dependencies +ebb4c6a990f786d7e0e4618a0d3766cd660125d8 # net: mscc: Unmet dependencies +c1a3d4067309451e68c33dbd356032549cc0bd8e # changes device names, kABI massacre +8520e224f547cd070c7c8f97b1fc6d58cff7ccaa # kABI breaker, see also bsc#1191279 +04f8ef5643bcd8bcde25dfdebef998aea480b2ba # irrelevant without 2b0d3d3e4fcf, rare leak +ca605f97dae4bf070b7c584aec23c1c922e4d823 # prerequisites would break the kABI in a manner hard to avoid and this is for support of new hardware +40fdea0284bb20814399da0484a658a96c735d90 # requires 8480ed9c2bbd56 +172f7ba9772cae12f099fc563352e905dc9a1921 # cosmetic fix +70a9ac36ffd807ac506ed0b849f3e8ce3c6623f2 # CONFIG_F2FS_FS is not set anywhere diff --git a/config/x86_64/rt b/config/x86_64/rt index 01c19ef..9a13747 100644 --- a/config/x86_64/rt +++ b/config/x86_64/rt @@ -96,6 +96,21 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_BPF_LSM=y +# end of BPF subsystem + CONFIG_HAVE_PREEMPT_LAZY=y CONFIG_PREEMPT_LAZY=y # CONFIG_PREEMPT_NONE is not set @@ -208,7 +223,6 @@ CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_HAVE_PCSPKR_PLATFORM=y -CONFIG_BPF=y CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -238,11 +252,6 @@ CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_LSM=y -CONFIG_BPF_SYSCALL=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y -CONFIG_BPF_JIT_ALWAYS_ON=y -CONFIG_BPF_JIT_DEFAULT_ON=y CONFIG_USERFAULTFD=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_RSEQ=y @@ -1770,7 +1779,6 @@ CONFIG_XPS=y CONFIG_CGROUP_NET_PRIO=y CONFIG_CGROUP_NET_CLASSID=y CONFIG_BQL=y -CONFIG_BPF_JIT=y CONFIG_BPF_STREAM_PARSER=y CONFIG_NET_FLOW_LIMIT=y @@ -2024,7 +2032,6 @@ CONFIG_NET_DEVLINK=y CONFIG_PAGE_POOL=y CONFIG_FAILOVER=m CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -3280,6 +3287,7 @@ CONFIG_NET_VENDOR_STMICRO=y CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_SELFTESTS is not set # CONFIG_STMMAC_PLATFORM is not set +CONFIG_DWMAC_INTEL=m CONFIG_STMMAC_PCI=m CONFIG_NET_VENDOR_SUN=y CONFIG_HAPPYMEAL=m @@ -4412,6 +4420,7 @@ CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set CONFIG_PINCTRL_AMD=y # CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_ROCKCHIP is not set # CONFIG_PINCTRL_SX150X is not set CONFIG_PINCTRL_BAYTRAIL=y CONFIG_PINCTRL_CHERRYVIEW=m diff --git a/config/x86_64/rt_debug b/config/x86_64/rt_debug index 45d2041..4f935a9 100644 --- a/config/x86_64/rt_debug +++ b/config/x86_64/rt_debug @@ -96,6 +96,21 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_BPF_LSM=y +# end of BPF subsystem + CONFIG_HAVE_PREEMPT_LAZY=y CONFIG_PREEMPT_LAZY=y # CONFIG_PREEMPT_NONE is not set @@ -208,7 +223,6 @@ CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_HAVE_PCSPKR_PLATFORM=y -CONFIG_BPF=y CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -238,11 +252,6 @@ CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_LSM=y -CONFIG_BPF_SYSCALL=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y -CONFIG_BPF_JIT_ALWAYS_ON=y -CONFIG_BPF_JIT_DEFAULT_ON=y CONFIG_USERFAULTFD=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_RSEQ=y @@ -1730,7 +1739,6 @@ CONFIG_XPS=y CONFIG_CGROUP_NET_PRIO=y CONFIG_CGROUP_NET_CLASSID=y CONFIG_BQL=y -CONFIG_BPF_JIT=y CONFIG_BPF_STREAM_PARSER=y CONFIG_NET_FLOW_LIMIT=y @@ -1960,7 +1968,6 @@ CONFIG_NET_DEVLINK=y CONFIG_PAGE_POOL=y CONFIG_FAILOVER=m CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -3172,6 +3179,7 @@ CONFIG_NET_VENDOR_STMICRO=y CONFIG_STMMAC_ETH=m # CONFIG_STMMAC_SELFTESTS is not set # CONFIG_STMMAC_PLATFORM is not set +CONFIG_DWMAC_INTEL=m CONFIG_STMMAC_PCI=m CONFIG_NET_VENDOR_SUN=y # CONFIG_HAPPYMEAL is not set @@ -4195,6 +4203,7 @@ CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set CONFIG_PINCTRL_AMD=y # CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_ROCKCHIP is not set # CONFIG_PINCTRL_SX150X is not set # CONFIG_PINCTRL_BAYTRAIL is not set CONFIG_PINCTRL_CHERRYVIEW=m diff --git a/patches.kabi/kabi-fix-after-kvm-vcpu-id-array-fix.patch b/patches.kabi/kabi-fix-after-kvm-vcpu-id-array-fix.patch deleted file mode 100644 index 9e27c90..0000000 --- a/patches.kabi/kabi-fix-after-kvm-vcpu-id-array-fix.patch +++ /dev/null @@ -1,45 +0,0 @@ -Patch-mainline: Never, kABI fix -References: git-fixes -From: Juergen Gross -Date: Thu, 1 Jul 2021 17:41:00 +0200 -Subject: [PATCH] kABI: Fix kABI after fixing vcpu-id indexed arrays - -Fix kABI after fixing the array sizes of arrays indexed by vcpu-id. -Fortunately the size today being KVM_MAX_VCPU_ID (with an odd value -of that macro) means, that there is always enough padding space in the -arrays for the correct value KVM_MAX_VCPU_ID+1. - -Signed-off-by: Juergen Gross ---- - arch/x86/kvm/ioapic.h | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/x86/kvm/ioapic.h b/arch/x86/kvm/ioapic.h -index 660401700075..11e4065e1617 100644 ---- a/arch/x86/kvm/ioapic.h -+++ b/arch/x86/kvm/ioapic.h -@@ -43,13 +43,21 @@ struct kvm_vcpu; - - struct dest_map { - /* vcpu bitmap where IRQ has been sent */ -+#ifdef __GENKSYMS__ -+ DECLARE_BITMAP(map, KVM_MAX_VCPU_ID); -+#else - DECLARE_BITMAP(map, KVM_MAX_VCPU_ID + 1); -+#endif - - /* - * Vector sent to a given vcpu, only valid when - * the vcpu's bit in map is set - */ -+#ifdef __GENKSYMS__ -+ u8 vectors[KVM_MAX_VCPU_ID]; -+#else - u8 vectors[KVM_MAX_VCPU_ID + 1]; -+#endif - }; - - --- -2.26.2 - diff --git a/patches.suse/ALSA-hda-Free-card-instance-properly-at-probe-errors.patch b/patches.suse/ALSA-hda-Free-card-instance-properly-at-probe-errors.patch new file mode 100644 index 0000000..c51271e --- /dev/null +++ b/patches.suse/ALSA-hda-Free-card-instance-properly-at-probe-errors.patch @@ -0,0 +1,52 @@ +From 39173303c83859723dab32c2abfb97296d6af3bf Mon Sep 17 00:00:00 2001 +From: Takashi Iwai +Date: Wed, 10 Nov 2021 20:46:33 +0100 +Subject: [PATCH] ALSA: hda: Free card instance properly at probe errors +Git-commit: 39173303c83859723dab32c2abfb97296d6af3bf +Patch-mainline: v5.16-rc1 +References: git-fixes + +The recent change in hda-intel driver to allow repeated probes +surfaced a problem that has been hidden until; the probe process in +the work calls azx_free() at the error path, and this skips the card +free process that eventually releases codec instances. As a result, +we get a kernel WARNING like: + + snd_hda_intel 0000:00:1f.3: Cannot probe codecs, giving up + ------------[ cut here ]------------ + WARNING: CPU: 14 PID: 186 at sound/hda/hdac_bus.c:73 + .... + +For fixing this, we need to call snd_card_free() instead of +azx_free(). Additionally, the device drvdata has to be cleared, as +the driver binding itself is still active. Then the PM and other +driver callbacks will ignore the procedure. + +Fixes: c0f1886de7e1 ("ALSA: hda: intel: Allow repeatedly probing on codec configuration errors") +Reported-and-tested-by: Scott Branden +Cc: +Link: https://lore.kernel.org/r/063e2397-7edb-5f48-7b0d-618b938d9dd8@broadcom.com +Link: https://lore.kernel.org/r/20211110194633.19098-1-tiwai@suse.de +Signed-off-by: Takashi Iwai + +--- + sound/pci/hda/hda_intel.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c +index 7762718cf429..90e9263ac0bd 100644 +--- a/sound/pci/hda/hda_intel.c ++++ b/sound/pci/hda/hda_intel.c +@@ -2327,7 +2327,8 @@ static int azx_probe_continue(struct azx *chip) + + out_free: + if (err < 0) { +- azx_free(chip); ++ pci_set_drvdata(pci, NULL); ++ snd_card_free(chip->card); + return err; + } + +-- +2.26.2 + diff --git a/patches.suse/ALSA-hda-fix-general-protection-fault-in-azx_runtime.patch b/patches.suse/ALSA-hda-fix-general-protection-fault-in-azx_runtime.patch new file mode 100644 index 0000000..7804460 --- /dev/null +++ b/patches.suse/ALSA-hda-fix-general-protection-fault-in-azx_runtime.patch @@ -0,0 +1,73 @@ +From e81478bbe7a1a062eeb5cd97cf00152a13ab8652 Mon Sep 17 00:00:00 2001 +From: Kai Vehmanen +Date: Wed, 10 Nov 2021 23:03:07 +0200 +Subject: [PATCH] ALSA: hda: fix general protection fault in azx_runtime_idle +Git-commit: e81478bbe7a1a062eeb5cd97cf00152a13ab8652 +Patch-mainline: v5.16-rc1 +References: git-fixes + +Fix a corner case between PCI device driver remove callback and +runtime PM idle callback. + +Following sequence of events can happen: + - at azx_create, context is allocated with devm_kzalloc() and + stored as pci_set_drvdata() + - user-space requests to unbind audio driver + - dd.c:__device_release_driver() calls PCI remove + - pci-driver.c:pci_device_remove() calls the audio + driver azx_remove() callback and this is completed + - pci-driver.c:pm_runtime_put_sync() leads to a call + to rpm_idle() which again calls azx_runtime_idle() + - the azx context object, as returned by dev_get_drvdata(), + is no longer valid + -> access fault in azx_runtime_idle when executing + struct snd_card *card = dev_get_drvdata(dev); + chip = card->private_data; + if (chip->disabled || hda->init_failed) + +This was discovered by i915_module_load test with 5.15.0 based +linux-next tree. + +Example log caught by i915_module_load test with linux-next +https://intel-gfx-ci.01.org/tree/linux-next/ + +<4> [264.038232] general protection fault, probably for non-canonical address 0x6b6b6b6b6b6b73f0: 0000 [#1] PREEMPT SMP NOPTI +<4> [264.038248] CPU: 0 PID: 5374 Comm: i915_module_loa Not tainted 5.15.0-next-20211109-gc8109c2ba35e-next-20211109 #1 +[...] +<4> [264.038267] RIP: 0010:azx_runtime_idle+0x12/0x60 [snd_hda_intel] +[...] +<4> [264.038355] Call Trace: +<4> [264.038359] +<4> [264.038362] __rpm_callback+0x3d/0x110 +<4> [264.038371] rpm_idle+0x27f/0x380 +<4> [264.038376] __pm_runtime_idle+0x3b/0x100 +<4> [264.038382] pci_device_remove+0x6d/0xa0 +<4> [264.038388] device_release_driver_internal+0xef/0x1e0 +<4> [264.038395] unbind_store+0xeb/0x120 +<4> [264.038400] kernfs_fop_write_iter+0x11a/0x1c0 + +Fix the issue by setting drvdata to NULL at end of azx_remove(). + +Signed-off-by: Kai Vehmanen +Link: https://lore.kernel.org/r/20211110210307.1172004-1-kai.vehmanen@linux.intel.com +Signed-off-by: Takashi Iwai + +--- + sound/pci/hda/hda_intel.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c +index 90e9263ac0bd..fe51163f2d82 100644 +--- a/sound/pci/hda/hda_intel.c ++++ b/sound/pci/hda/hda_intel.c +@@ -2365,6 +2365,7 @@ static void azx_remove(struct pci_dev *pci) + cancel_delayed_work_sync(&hda->probe_work); + device_lock(&pci->dev); + ++ pci_set_drvdata(pci, NULL); + snd_card_free(card); + } + } +-- +2.26.2 + diff --git a/patches.suse/ALSA-hda-intel-Allow-repeatedly-probing-on-codec-con.patch b/patches.suse/ALSA-hda-intel-Allow-repeatedly-probing-on-codec-con.patch index 76c41f8..fc4a683 100644 --- a/patches.suse/ALSA-hda-intel-Allow-repeatedly-probing-on-codec-con.patch +++ b/patches.suse/ALSA-hda-intel-Allow-repeatedly-probing-on-codec-con.patch @@ -5,8 +5,7 @@ Subject: [PATCH] ALSA: hda: intel: Allow repeatedly probing on codec configuration errors References: bsc#1190801 Git-commit: c0f1886de7e173865f1a0fa7680a1c07954a987f -Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git -Patch-mainline: Queued in subsystem maintainer repository +Patch-mainline: v5.15-rc6 It seems that a few recent AMD systems show the codec configuration errors at the early boot, while loading the driver at a later stage diff --git a/patches.suse/ALSA-usb-audio-Add-minimal-mute-notion-in-dB-mapping.patch b/patches.suse/ALSA-usb-audio-Add-minimal-mute-notion-in-dB-mapping.patch new file mode 100644 index 0000000..f0bf8ce --- /dev/null +++ b/patches.suse/ALSA-usb-audio-Add-minimal-mute-notion-in-dB-mapping.patch @@ -0,0 +1,52 @@ +From 85b741c1cb6854478fd1aa13ac231e2c1baf4c4b Mon Sep 17 00:00:00 2001 +From: Takashi Iwai +Date: Tue, 16 Nov 2021 07:54:14 +0100 +Subject: [PATCH] ALSA: usb-audio: Add minimal-mute notion in dB mapping table +Git-commit: 85b741c1cb6854478fd1aa13ac231e2c1baf4c4b +Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git +Patch-mainline: Queued in subsystem maintainer repository +References: bsc#1192375 + +Some devices do mute the volume at the minimal volume, and for such +devices, we need to set SNDRV_CTL_TLVT_DB_MINMAX_MUTE to the TLV +information. It corresponds to setting usb_mixer_elem_info.min_mute +flag in the USB-audio driver. + +This patch adds a new field min_mute in usbmix_dB_map so that the +mixer map entry can pass the flag. + +Link: https://lore.kernel.org/r/20211116065415.11159-3-tiwai@suse.de +Signed-off-by: Takashi Iwai + +--- + sound/usb/mixer.c | 1 + + sound/usb/mixer_maps.c | 1 + + 2 files changed, 2 insertions(+) + +diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c +index 6e7bac8203ba..5b9fd07ce2a2 100644 +--- a/sound/usb/mixer.c ++++ b/sound/usb/mixer.c +@@ -145,6 +145,7 @@ static inline void check_mapped_dB(const struct usbmix_name_map *p, + if (p && p->dB) { + cval->dBmin = p->dB->min; + cval->dBmax = p->dB->max; ++ cval->min_mute = p->dB->min_mute; + cval->initialized = 1; + } + } +diff --git a/sound/usb/mixer_maps.c b/sound/usb/mixer_maps.c +index 92c06b1bb979..9d71c569b148 100644 +--- a/sound/usb/mixer_maps.c ++++ b/sound/usb/mixer_maps.c +@@ -8,6 +8,7 @@ + struct usbmix_dB_map { + int min; + int max; ++ bool min_mute; + }; + + struct usbmix_name_map { +-- +2.26.2 + diff --git a/patches.suse/ALSA-usb-audio-Fix-dB-level-of-Bose-Revolve-SoundLin.patch b/patches.suse/ALSA-usb-audio-Fix-dB-level-of-Bose-Revolve-SoundLin.patch new file mode 100644 index 0000000..3e9e751 --- /dev/null +++ b/patches.suse/ALSA-usb-audio-Fix-dB-level-of-Bose-Revolve-SoundLin.patch @@ -0,0 +1,57 @@ +From 02eb1d098e26f34c8f047b0b1cee6f4433a34bd1 Mon Sep 17 00:00:00 2001 +From: Takashi Iwai +Date: Tue, 16 Nov 2021 07:54:15 +0100 +Subject: [PATCH] ALSA: usb-audio: Fix dB level of Bose Revolve+ SoundLink +Git-commit: 02eb1d098e26f34c8f047b0b1cee6f4433a34bd1 +Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git +Patch-mainline: Queued in subsystem maintainer repository +References: bsc#1192375 + +Bose Revolve+ SoundLink (0a57:40fa) advertises invalid dB level for +the speaker volume. This patch provides the correction in the mixer +map quirk table entry. + +Note that this requires the prerequisite change to add min_mute flag +to the dB map table. + +Buglink: https://bugzilla.suse.com/show_bug.cgi?id=1192375 +Link: https://lore.kernel.org/r/20211116065415.11159-4-tiwai@suse.de +Signed-off-by: Takashi Iwai + +--- + sound/usb/mixer_maps.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/sound/usb/mixer_maps.c b/sound/usb/mixer_maps.c +index 9d71c569b148..5d391f62351b 100644 +--- a/sound/usb/mixer_maps.c ++++ b/sound/usb/mixer_maps.c +@@ -337,6 +337,13 @@ static const struct usbmix_name_map bose_companion5_map[] = { + { 0 } /* terminator */ + }; + ++/* Bose Revolve+ SoundLink, correction of dB maps */ ++static const struct usbmix_dB_map bose_soundlink_dB = {-8283, -0, true}; ++static const struct usbmix_name_map bose_soundlink_map[] = { ++ { 2, NULL, .dB = &bose_soundlink_dB }, ++ { 0 } /* terminator */ ++}; ++ + /* Sennheiser Communications Headset [PC 8], the dB value is reported as -6 negative maximum */ + static const struct usbmix_dB_map sennheiser_pc8_dB = {-9500, 0}; + static const struct usbmix_name_map sennheiser_pc8_map[] = { +@@ -522,6 +529,11 @@ static const struct usbmix_ctl_map usbmix_ctl_maps[] = { + .id = USB_ID(0x05a7, 0x1020), + .map = bose_companion5_map, + }, ++ { ++ /* Bose Revolve+ SoundLink */ ++ .id = USB_ID(0x05a7, 0x40fa), ++ .map = bose_soundlink_map, ++ }, + { + /* Corsair Virtuoso SE (wired mode) */ + .id = USB_ID(0x1b1c, 0x0a3d), +-- +2.26.2 + diff --git a/patches.suse/ALSA-usb-audio-Use-int-for-dB-map-values.patch b/patches.suse/ALSA-usb-audio-Use-int-for-dB-map-values.patch new file mode 100644 index 0000000..13b0792 --- /dev/null +++ b/patches.suse/ALSA-usb-audio-Use-int-for-dB-map-values.patch @@ -0,0 +1,38 @@ +From fd23116d7b8dffa05f42a857eee6ee9cce238d24 Mon Sep 17 00:00:00 2001 +From: Takashi Iwai +Date: Tue, 16 Nov 2021 07:54:13 +0100 +Subject: [PATCH] ALSA: usb-audio: Use int for dB map values +Git-commit: fd23116d7b8dffa05f42a857eee6ee9cce238d24 +Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git +Patch-mainline: Queued in subsystem maintainer repository +References: bsc#1192375 + +The values in usbmix_dB_map should be rather signed while we're using +u32. As the copied target (usb_mixer_elem_info.dBmin and dBmax) is +int, let's make them also int. + +Link: https://lore.kernel.org/r/20211116065415.11159-2-tiwai@suse.de +Signed-off-by: Takashi Iwai + +--- + sound/usb/mixer_maps.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/sound/usb/mixer_maps.c b/sound/usb/mixer_maps.c +index 55eea90ee993..92c06b1bb979 100644 +--- a/sound/usb/mixer_maps.c ++++ b/sound/usb/mixer_maps.c +@@ -6,8 +6,8 @@ + */ + + struct usbmix_dB_map { +- u32 min; +- u32 max; ++ int min; ++ int max; + }; + + struct usbmix_name_map { +-- +2.26.2 + diff --git a/patches.suse/ARM-socfpga-Fix-crash-with-CONFIG_FORTIRY_SOURCE.patch b/patches.suse/ARM-socfpga-Fix-crash-with-CONFIG_FORTIRY_SOURCE.patch new file mode 100644 index 0000000..41f1c6d --- /dev/null +++ b/patches.suse/ARM-socfpga-Fix-crash-with-CONFIG_FORTIRY_SOURCE.patch @@ -0,0 +1,77 @@ +From: Takashi Iwai +Subject: [PATCH v2] ARM: socfpga: Fix crash with CONFIG_FORTIRY_SOURCE +Date: Thu, 18 Nov 2021 15:25:08 +0100 +Message-Id: <20211118142508.19200-1-tiwai@suse.de> +Patch-mainline: Submitted, linux-arm ML +References: bsc#1192473 + +When CONFIG_FORTIFY_SOURCE is set, memcpy() checks the potential +buffer overflow and panics. The code in sofcpga bootstrapping +contains the memcpy() calls are mistakenly translated as the shorter +size, hence it triggers a panic as if it were overflowing. + +This patch changes the secondary_trampoline and *_end definitions +to arrays for avoiding the false-positive crash above. + +Suggested-by: Kees Cook +Buglink: https://bugzilla.suse.com/show_bug.cgi?id=1192473 +Link: https://lore.kernel.org/r/20211117193244.31162-1-tiwai@suse.de +Signed-off-by: Takashi Iwai + +--- + arch/arm/mach-socfpga/core.h | 2 +- + arch/arm/mach-socfpga/platsmp.c | 8 ++++---- + 2 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h +index fc2608b18a0d..18f01190dcfd 100644 +--- a/arch/arm/mach-socfpga/core.h ++++ b/arch/arm/mach-socfpga/core.h +@@ -33,7 +33,7 @@ extern void __iomem *sdr_ctl_base_addr; + u32 socfpga_sdram_self_refresh(u32 sdr_base); + extern unsigned int socfpga_sdram_self_refresh_sz; + +-extern char secondary_trampoline, secondary_trampoline_end; ++extern char secondary_trampoline[], secondary_trampoline_end[]; + + extern unsigned long socfpga_cpu1start_addr; + +diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c +index fbb80b883e5d..201191cf68f3 100644 +--- a/arch/arm/mach-socfpga/platsmp.c ++++ b/arch/arm/mach-socfpga/platsmp.c +@@ -20,14 +20,14 @@ + + static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) + { +- int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; ++ int trampoline_size = secondary_trampoline_end - secondary_trampoline; + + if (socfpga_cpu1start_addr) { + /* This will put CPU #1 into reset. */ + writel(RSTMGR_MPUMODRST_CPU1, + rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST); + +- memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); ++ memcpy(phys_to_virt(0), secondary_trampoline, trampoline_size); + + writel(__pa_symbol(secondary_startup), + sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)); +@@ -45,12 +45,12 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) + + static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle) + { +- int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; ++ int trampoline_size = secondary_trampoline_end - secondary_trampoline; + + if (socfpga_cpu1start_addr) { + writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr + + SOCFPGA_A10_RSTMGR_MODMPURST); +- memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); ++ memcpy(phys_to_virt(0), secondary_trampoline, trampoline_size); + + writel(__pa_symbol(secondary_startup), + sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff)); +-- +2.26.2 + diff --git a/patches.suse/Bluetooth-sco-Fix-lock_sock-blockage-by-memcpy_from_.patch b/patches.suse/Bluetooth-sco-Fix-lock_sock-blockage-by-memcpy_from_.patch index b96c3e9..64010e5 100644 --- a/patches.suse/Bluetooth-sco-Fix-lock_sock-blockage-by-memcpy_from_.patch +++ b/patches.suse/Bluetooth-sco-Fix-lock_sock-blockage-by-memcpy_from_.patch @@ -3,8 +3,7 @@ From: Takashi Iwai Date: Sat, 28 Aug 2021 18:18:18 +0200 Subject: [PATCH] Bluetooth: sco: Fix lock_sock() blockage by memcpy_from_msg() Git-commit: 99c23da0eed4fd20cae8243f2b51e10e66aa0951 -Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next.git -Patch-mainline: Queued in subsystem maintainer repo +Patch-mainline: v5.16-rc1 References: CVE-2021-3640 bsc#1188172 The sco_send_frame() also takes lock_sock() during memcpy_from_msg() diff --git a/patches.suse/Input-Fix-memory-leak-in-psxpad_spi_probe.patch b/patches.suse/Input-Fix-memory-leak-in-psxpad_spi_probe.patch index 0e66711..445580d 100644 --- a/patches.suse/Input-Fix-memory-leak-in-psxpad_spi_probe.patch +++ b/patches.suse/Input-Fix-memory-leak-in-psxpad_spi_probe.patch @@ -1,8 +1,7 @@ From: Navid Emamdoost Date: Thu, 21 Nov 2019 14:01:11 -0600 Subject: Input: Fix memory leak in psxpad_spi_probe -Git-commit: 96a992ff50a1f2a0016dd8845025585961f12d05 -Patch-mainline: 5.3.16 +Patch-mainline: Never, addressed in rework (commit 055070a7d0d3), patch from stable commit 96a992ff50a1 References: bnc#1151927 5.3.16 In the implementation of psxpad_spi_probe() the allocated memory for diff --git a/patches.suse/Input-elantench-fix-misreporting-trackpoint-coordina.patch b/patches.suse/Input-elantench-fix-misreporting-trackpoint-coordina.patch new file mode 100644 index 0000000..86a2247 --- /dev/null +++ b/patches.suse/Input-elantench-fix-misreporting-trackpoint-coordina.patch @@ -0,0 +1,50 @@ +From be896bd3b72b44126c55768f14c22a8729b0992e Mon Sep 17 00:00:00 2001 +From: Phoenix Huang +Date: Sun, 7 Nov 2021 22:00:03 -0800 +Subject: [PATCH] Input: elantench - fix misreporting trackpoint coordinates +Git-commit: be896bd3b72b44126c55768f14c22a8729b0992e +Patch-mainline: v5.16-rc1 +References: bsc#1192918 + +Some firmwares occasionally report bogus data from trackpoint, with X or Y +displacement being too large (outside of [-127, 127] range). Let's drop such +packets so that we do not generate jumps. + +Signed-off-by: Phoenix Huang +Tested-by: Yufei Du +Link: https://lore.kernel.org/r/20210729010940.5752-1-phoenix@emc.com.tw +Cc: stable@vger.kernel.org +Signed-off-by: Dmitry Torokhov +Acked-by: Takashi Iwai + +--- + drivers/input/mouse/elantech.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/input/mouse/elantech.c b/drivers/input/mouse/elantech.c +index 2d0bc029619f..956d9cd34796 100644 +--- a/drivers/input/mouse/elantech.c ++++ b/drivers/input/mouse/elantech.c +@@ -517,6 +517,19 @@ static void elantech_report_trackpoint(struct psmouse *psmouse, + case 0x16008020U: + case 0x26800010U: + case 0x36808000U: ++ ++ /* ++ * This firmware misreport coordinates for trackpoint ++ * occasionally. Discard packets outside of [-127, 127] range ++ * to prevent cursor jumps. ++ */ ++ if (packet[4] == 0x80 || packet[5] == 0x80 || ++ packet[1] >> 7 == packet[4] >> 7 || ++ packet[2] >> 7 == packet[5] >> 7) { ++ elantech_debug("discarding packet [%6ph]\n", packet); ++ break; ++ ++ } + x = packet[4] - (int)((packet[1]^0x80) << 1); + y = (int)((packet[2]^0x80) << 1) - packet[5]; + +-- +2.26.2 + diff --git a/patches.suse/Revert-r8152-adjust-the-settings-about-MAC-clock-spe.patch b/patches.suse/Revert-r8152-adjust-the-settings-about-MAC-clock-spe.patch new file mode 100644 index 0000000..de64ac5 --- /dev/null +++ b/patches.suse/Revert-r8152-adjust-the-settings-about-MAC-clock-spe.patch @@ -0,0 +1,106 @@ +From 4b5dc1a94d4f92b5845e98bd9ae344b26d933aad Mon Sep 17 00:00:00 2001 +From: Hayes Wang +Date: Wed, 3 Mar 2021 16:39:47 +0800 +Subject: [PATCH] Revert "r8152: adjust the settings about MAC clock speed down + for RTL8153" +Git-commit: 4b5dc1a94d4f92b5845e98bd9ae344b26d933aad +References: git-fixes +Patch-mainline: v5.12-rc3 + +This reverts commit 134f98bcf1b898fb9d6f2b91bc85dd2e5478b4b8. + +The r8153_mac_clk_spd() is used for RTL8153A only, because the register +table of RTL8153B is different from RTL8153A. However, this function would +be called when RTL8153B calls r8153_first_init() and r8153_enter_oob(). +That causes RTL8153B becomes unstable when suspending and resuming. The +worst case may let the device stop working. + +Besides, revert this commit to disable MAC clock speed down for RTL8153A. +It would avoid the known issue when enabling U1. The data of the first +control transfer may be wrong when exiting U1. + +Signed-off-by: Hayes Wang +Signed-off-by: David S. Miller +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/r8152.c | 35 ++++++----------------------------- + 1 file changed, 6 insertions(+), 29 deletions(-) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -2746,29 +2746,6 @@ static void __rtl_set_wol(struct r8152 * + device_set_wakeup_enable(&tp->udev->dev, false); + } + +-static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) +-{ +- /* MAC clock speed down */ +- if (enable) { +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, +- ALDPS_SPDWN_RATIO); +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, +- EEE_SPDWN_RATIO); +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, +- PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | +- U1U2_SPDWN_EN | L1_SPDWN_EN); +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, +- PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | +- TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | +- TP1000_SPDWN_EN); +- } else { +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); +- } +-} +- + static void r8153_u1u2en(struct r8152 *tp, bool enable) + { + u8 u1u2[8]; +@@ -3004,11 +2981,9 @@ static void rtl8153_runtime_enable(struc + if (enable) { + r8153_u1u2en(tp, false); + r8153_u2p3en(tp, false); +- r8153_mac_clk_spd(tp, true); + rtl_runtime_suspend_enable(tp, true); + } else { + rtl_runtime_suspend_enable(tp, false); +- r8153_mac_clk_spd(tp, false); + + switch (tp->version) { + case RTL_VER_03: +@@ -3603,7 +3578,6 @@ static void r8153_first_init(struct r815 + u32 ocp_data; + int i; + +- r8153_mac_clk_spd(tp, false); + rxdy_gated_en(tp, true); + r8153_teredo_off(tp); + +@@ -3665,8 +3639,6 @@ static void r8153_enter_oob(struct r8152 + u32 ocp_data; + int i; + +- r8153_mac_clk_spd(tp, true); +- + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); + ocp_data &= ~NOW_IS_OOB; + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); +@@ -4378,10 +4350,15 @@ static void r8153_init(struct r8152 *tp) + + ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); + ++ /* MAC clock speed down */ ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); ++ + r8153_power_cut_en(tp, false); + rtl_runtime_suspend_enable(tp, false); + r8153_u1u2en(tp, true); +- r8153_mac_clk_spd(tp, false); + usb_enable_lpm(tp->udev); + + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); diff --git a/patches.suse/Revert-scsi-ufs-fix-a-missing-check-of-devm_reset_control_get b/patches.suse/Revert-scsi-ufs-fix-a-missing-check-of-devm_reset_control_get new file mode 100644 index 0000000..52746ad --- /dev/null +++ b/patches.suse/Revert-scsi-ufs-fix-a-missing-check-of-devm_reset_control_get @@ -0,0 +1,49 @@ +From: Greg Kroah-Hartman +Date: Mon, 3 May 2021 13:56:57 +0200 +Subject: Revert "scsi: ufs: fix a missing check of devm_reset_control_get" +Git-commit: 4d427b408c4c2ff1676966c72119a3a559f8e39b +Patch-mainline: v5.13-rc3 +References: git-fixes + +This reverts commit 63a06181d7ce169d09843645c50fea1901bc9f0a. + +Because of recent interactions with developers from @umn.edu, all +commits from them have been recently re-reviewed to ensure if they were +correct or not. + +Upon review, this commit was found to be incorrect for the reasons +below, so it must be reverted. It will be fixed up "correctly" in a +later kernel change. + +The original commit is incorrect, it does not properly clean up on the +error path, so I'll keep the revert and fix it up properly with a +follow-on patch. + +Cc: Kangjie Lu +Cc: Avri Altman +Cc: Martin K. Petersen +Fixes: 63a06181d7ce ("scsi: ufs: fix a missing check of devm_reset_control_get") +Cc: stable +Link: https://lore.kernel.org/r/20210503115736.2104747-31-gregkh@linuxfoundation.org +Signed-off-by: Greg Kroah-Hartman +Acked-by: Lee Duncan +--- + drivers/scsi/ufs/ufs-hisi.c | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/drivers/scsi/ufs/ufs-hisi.c b/drivers/scsi/ufs/ufs-hisi.c +index 0aa58131e791..7d1e07a9d9dd 100644 +--- a/drivers/scsi/ufs/ufs-hisi.c ++++ b/drivers/scsi/ufs/ufs-hisi.c +@@ -468,10 +468,6 @@ static int ufs_hisi_init_common(struct ufs_hba *hba) + ufshcd_set_variant(hba, host); + + host->rst = devm_reset_control_get(dev, "rst"); +- if (IS_ERR(host->rst)) { +- dev_err(dev, "%s: failed to get reset control\n", __func__); +- return PTR_ERR(host->rst); +- } + + ufs_hisi_set_pm_lvl(hba); + + diff --git a/patches.suse/Revert-x86-kvm-fix-vcpu-id-indexed-array-sizes.patch b/patches.suse/Revert-x86-kvm-fix-vcpu-id-indexed-array-sizes.patch new file mode 100644 index 0000000..6638668 --- /dev/null +++ b/patches.suse/Revert-x86-kvm-fix-vcpu-id-indexed-array-sizes.patch @@ -0,0 +1,59 @@ +Patch-mainline: v5.16-rc1 +Git-commit: 1e254d0d86a0f2efd4190a89d5204b37c18c6381 +References: git-fixes +From: Juergen Gross +Date: Mon, 13 Sep 2021 15:57:43 +0200 +Subject: [PATCH] Revert "x86/kvm: fix vcpu-id indexed array sizes" + +This reverts commit 76b4f357d0e7d8f6f0013c733e6cba1773c266d3. + +The commit has the wrong reasoning, as KVM_MAX_VCPU_ID is not defining the +maximum allowed vcpu-id as its name suggests, but the number of vcpu-ids. +So revert this patch again. + +Suggested-by: Eduardo Habkost +Signed-off-by: Juergen Gross +Signed-off-by: Paolo Bonzini +Message-Id: <20210913135745.13944-2-jgross@suse.com> +Signed-off-by: Paolo Bonzini +--- + arch/x86/kvm/ioapic.c | 2 +- + arch/x86/kvm/ioapic.h | 4 ++-- + 2 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c +index 8c065da73f8e..4e0f52660842 100644 +--- a/arch/x86/kvm/ioapic.c ++++ b/arch/x86/kvm/ioapic.c +@@ -96,7 +96,7 @@ static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, + static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic) + { + ioapic->rtc_status.pending_eoi = 0; +- bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPU_ID + 1); ++ bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPU_ID); + } + + static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic); +diff --git a/arch/x86/kvm/ioapic.h b/arch/x86/kvm/ioapic.h +index bbd4a5d18b5d..27e61ff3ac3e 100644 +--- a/arch/x86/kvm/ioapic.h ++++ b/arch/x86/kvm/ioapic.h +@@ -39,13 +39,13 @@ struct kvm_vcpu; + + struct dest_map { + /* vcpu bitmap where IRQ has been sent */ +- DECLARE_BITMAP(map, KVM_MAX_VCPU_ID + 1); ++ DECLARE_BITMAP(map, KVM_MAX_VCPU_ID); + + /* + * Vector sent to a given vcpu, only valid when + * the vcpu's bit in map is set + */ +- u8 vectors[KVM_MAX_VCPU_ID + 1]; ++ u8 vectors[KVM_MAX_VCPU_ID]; + }; + + +-- +2.26.2 + diff --git a/patches.suse/acpi_thinkpad_introduce_acpi_root_table_boot_param.patch b/patches.suse/acpi_thinkpad_introduce_acpi_root_table_boot_param.patch index 86fb2f9..cff99d1 100644 --- a/patches.suse/acpi_thinkpad_introduce_acpi_root_table_boot_param.patch +++ b/patches.suse/acpi_thinkpad_introduce_acpi_root_table_boot_param.patch @@ -1,6 +1,6 @@ From: Thomas Renninger Subject: Introduce acpi_root_table=rsdt boot param and dmi list to force rsdt -Patch-mainline: No, +Patch-mainline: Not yet, References: http://bugzilla.kernel.org/show_bug.cgi?id=8246 This one is part of a patch series: diff --git a/patches.suse/bpf-Add-kconfig-knob-for-disabling-unpriv-bpf-by-def.patch b/patches.suse/bpf-Add-kconfig-knob-for-disabling-unpriv-bpf-by-def.patch new file mode 100644 index 0000000..cb3521d --- /dev/null +++ b/patches.suse/bpf-Add-kconfig-knob-for-disabling-unpriv-bpf-by-def.patch @@ -0,0 +1,118 @@ +From: Daniel Borkmann +Date: Tue, 11 May 2021 22:35:17 +0200 +Subject: bpf: Add kconfig knob for disabling unpriv bpf by default +Patch-mainline: v5.13-rc4 +Git-commit: 08389d888287c3823f80b0216766b71e17f0aba5 +References: jsc#SLE-22574 + +Add a kconfig knob which allows for unprivileged bpf to be disabled by default. +If set, the knob sets /proc/sys/kernel/unprivileged_bpf_disabled to value of 2. + +This still allows a transition of 2 -> {0,1} through an admin. Similarly, +this also still keeps 1 -> {1} behavior intact, so that once set to permanently +disabled, it cannot be undone aside from a reboot. + +We've also added extra2 with max of 2 for the procfs handler, so that an admin +still has a chance to toggle between 0 <-> 2. + +Either way, as an additional alternative, applications can make use of CAP_BPF +that we added a while ago. + +Signed-off-by: Daniel Borkmann +Signed-off-by: Alexei Starovoitov +Link: https://lore.kernel.org/bpf/74ec548079189e4e4dffaeb42b8987bb3c852eee.1620765074.git.daniel@iogearbox.net +Acked-by: Shung-Hsi Yu +--- +syu: Drop documentation and add forward declaration for bpf_unpriv_handler() +since f461d2dcd511 ("sysctl: avoid forward declarations") is not backported. +--- + kernel/bpf/Kconfig | 10 ++++++++++ + kernel/bpf/syscall.c | 3 ++- + kernel/sysctl.c | 31 ++++++++++++++++++++++++++----- + 3 files changed, 38 insertions(+), 6 deletions(-) + +--- a/kernel/bpf/Kconfig ++++ b/kernel/bpf/Kconfig +@@ -58,6 +58,16 @@ config BPF_JIT_DEFAULT_ON + def_bool ARCH_WANT_DEFAULT_BPF_JIT || BPF_JIT_ALWAYS_ON + depends on HAVE_EBPF_JIT && BPF_JIT + ++config BPF_UNPRIV_DEFAULT_OFF ++ bool "Disable unprivileged BPF by default" ++ depends on BPF_SYSCALL ++ help ++ Disables unprivileged BPF by default by setting the corresponding ++ /proc/sys/kernel/unprivileged_bpf_disabled knob to 2. An admin can ++ still reenable it by setting it to 0 later on, or permanently ++ disable it by setting it to 1 (from which no other transition to ++ 0 is possible anymore). ++ + config BPF_LSM + bool "Enable BPF LSM Instrumentation" + depends on BPF_EVENTS +--- a/kernel/bpf/syscall.c ++++ b/kernel/bpf/syscall.c +@@ -47,7 +47,8 @@ static DEFINE_SPINLOCK(map_idr_lock); + static DEFINE_IDR(link_idr); + static DEFINE_SPINLOCK(link_idr_lock); + +-int sysctl_unprivileged_bpf_disabled __read_mostly; ++int sysctl_unprivileged_bpf_disabled __read_mostly = ++ IS_BUILTIN(CONFIG_BPF_UNPRIV_DEFAULT_OFF) ? 2 : 0; + + static const struct bpf_map_ops * const bpf_map_types[] = { + #define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) +--- a/kernel/sysctl.c ++++ b/kernel/sysctl.c +@@ -210,6 +210,8 @@ enum sysctl_writes_mode { + static int bpf_stats_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); ++static int bpf_unpriv_handler(struct ctl_table *table, int write, ++ void *buffer, size_t *lenp, loff_t *ppos); + #endif + + static enum sysctl_writes_mode sysctl_writes_strict = SYSCTL_WRITES_STRICT; +@@ -1260,10 +1262,9 @@ static struct ctl_table kern_table[] = { + .data = &sysctl_unprivileged_bpf_disabled, + .maxlen = sizeof(sysctl_unprivileged_bpf_disabled), + .mode = 0644, +- /* only handle a transition from default "0" to "1" */ +- .proc_handler = proc_dointvec_minmax, +- .extra1 = SYSCTL_ONE, +- .extra2 = SYSCTL_ONE, ++ .proc_handler = bpf_unpriv_handler, ++ .extra1 = SYSCTL_ZERO, ++ .extra2 = &two, + }, + { + .procname = "bpf_stats_enabled", +@@ -2027,7 +2028,27 @@ static int bpf_stats_handler(struct ctl_ + mutex_unlock(&bpf_stats_enabled_mutex); + return ret; + } +-#endif ++ ++static int bpf_unpriv_handler(struct ctl_table *table, int write, ++ void *buffer, size_t *lenp, loff_t *ppos) ++{ ++ int ret, unpriv_enable = *(int *)table->data; ++ bool locked_state = unpriv_enable == 1; ++ struct ctl_table tmp = *table; ++ ++ if (write && !capable(CAP_SYS_ADMIN)) ++ return -EPERM; ++ ++ tmp.data = &unpriv_enable; ++ ret = proc_dointvec_minmax(&tmp, write, buffer, lenp, ppos); ++ if (write && !ret) { ++ if (locked_state && unpriv_enable != 1) ++ return -EPERM; ++ *(int *)table->data = unpriv_enable; ++ } ++ return ret; ++} ++#endif /* CONFIG_BPF_SYSCALL && CONFIG_SYSCTL */ + + /* + * /proc/sys support diff --git a/patches.suse/bpf-Disallow-unprivileged-bpf-by-default.patch b/patches.suse/bpf-Disallow-unprivileged-bpf-by-default.patch new file mode 100644 index 0000000..1cf303b --- /dev/null +++ b/patches.suse/bpf-Disallow-unprivileged-bpf-by-default.patch @@ -0,0 +1,54 @@ +From: Pawan Gupta +Date: Fri, 29 Oct 2021 12:43:54 -0700 +Subject: bpf: Disallow unprivileged bpf by default +Patch-mainline: v5.16-rc1 +Git-commit: 8a03e56b253e9691c90bc52ca199323d71b96204 +References: jsc#SLE-22574 + +Disabling unprivileged BPF would help prevent unprivileged users from +creating certain conditions required for potential speculative execution +side-channel attacks on unmitigated affected hardware. + +A deep dive on such attacks and current mitigations is available here [0]. + +Sync with what many distros are currently applying already, and disable +unprivileged BPF by default. An admin can enable this at runtime, if +necessary, as described in 08389d888287 ("bpf: Add kconfig knob for +disabling unpriv bpf by default"). + + [0] "BPF and Spectre: Mitigating transient execution attacks", Daniel Borkmann, eBPF Summit '21 + https://ebpf.io/summit-2021-slides/eBPF_Summit_2021-Keynote-Daniel_Borkmann-BPF_and_Spectre.pdf + +Signed-off-by: Pawan Gupta +Signed-off-by: Daniel Borkmann +Acked-by: Daniel Borkmann +Acked-by: Mark Rutland +Link: https://lore.kernel.org/bpf/0ace9ce3f97656d5f62d11093ad7ee81190c3c25.1635535215.git.pawan.kumar.gupta@linux.intel.com +Acked-by: Shung-Hsi Yu +--- + kernel/bpf/Kconfig | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/kernel/bpf/Kconfig ++++ b/kernel/bpf/Kconfig +@@ -61,6 +61,7 @@ config BPF_JIT_DEFAULT_ON + + config BPF_UNPRIV_DEFAULT_OFF + bool "Disable unprivileged BPF by default" ++ default y + depends on BPF_SYSCALL + help + Disables unprivileged BPF by default by setting the corresponding +@@ -69,6 +70,12 @@ config BPF_UNPRIV_DEFAULT_OFF + disable it by setting it to 1 (from which no other transition to + 0 is possible anymore). + ++ Unprivileged BPF could be used to exploit certain potential ++ speculative execution side-channel vulnerabilities on unmitigated ++ affected hardware. ++ ++ If you are unsure how to answer this question, answer Y. ++ + config BPF_LSM + bool "Enable BPF LSM Instrumentation" + depends on BPF_EVENTS diff --git a/patches.suse/bpf-Fix-BPF_JIT-kconfig-symbol-dependency.patch b/patches.suse/bpf-Fix-BPF_JIT-kconfig-symbol-dependency.patch new file mode 100644 index 0000000..c7c7df8 --- /dev/null +++ b/patches.suse/bpf-Fix-BPF_JIT-kconfig-symbol-dependency.patch @@ -0,0 +1,64 @@ +From: Daniel Borkmann +Date: Wed, 12 May 2021 20:57:14 +0200 +Subject: bpf: Fix BPF_JIT kconfig symbol dependency +Patch-mainline: v5.13-rc4 +Git-commit: 6bdacdb48e94ff26c03c6eeeef48c03c5e2f7dd4 +References: git-fixes jsc#SLE-22574 + +Randy reported a randconfig build error recently on i386: + + ld: arch/x86/net/bpf_jit_comp32.o: in function `do_jit': + bpf_jit_comp32.c:(.text+0x28c9): undefined reference to `__bpf_call_base' + ld: arch/x86/net/bpf_jit_comp32.o: in function `bpf_int_jit_compile': + bpf_jit_comp32.c:(.text+0x3694): undefined reference to `bpf_jit_blind_constants' + ld: bpf_jit_comp32.c:(.text+0x3719): undefined reference to `bpf_jit_binary_free' + ld: bpf_jit_comp32.c:(.text+0x3745): undefined reference to `bpf_jit_binary_alloc' + ld: bpf_jit_comp32.c:(.text+0x37d3): undefined reference to `bpf_jit_prog_release_other' + [...] + +The cause was that b24abcff918a ("bpf, kconfig: Add consolidated menu entry for +bpf with core options") moved BPF_JIT from net/Kconfig into kernel/bpf/Kconfig +and previously BPF_JIT was guarded by a 'if NET'. However, there is no actual +dependency on NET, it's just that menuconfig NET selects BPF. And the latter in +turn causes kernel/bpf/core.o to be built which contains above symbols. Randy's +randconfig didn't have NET set, and BPF wasn't either, but BPF_JIT otoh was. +Detangle this by making BPF_JIT depend on BPF instead. arm64 was the only arch +that pulled in its JIT in net/ via obj-$(CONFIG_NET), all others unconditionally +pull this dir in via obj-y. Do the same since CONFIG_NET guard there is really +useless as we compiled the JIT via obj-$(CONFIG_BPF_JIT) += bpf_jit_comp.o anyway. + +Fixes: b24abcff918a ("bpf, kconfig: Add consolidated menu entry for bpf with core options") +Reported-by: Randy Dunlap +Signed-off-by: Daniel Borkmann +Acked-by: Randy Dunlap +Tested-by: Randy Dunlap +Acked-by: Shung-Hsi Yu +--- +syu: arch/arm64/Kbuild doesn't exists, patch Makefile instead +--- + arch/arm64/Makefile | 3 +-- + kernel/bpf/Kconfig | 1 + + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/Makefile ++++ b/arch/arm64/Makefile +@@ -138,8 +138,7 @@ KBUILD_AFLAGS += -DKASAN_SHADOW_SCALE_SH + + export TEXT_OFFSET GZFLAGS + +-core-y += arch/arm64/kernel/ arch/arm64/mm/ +-core-$(CONFIG_NET) += arch/arm64/net/ ++core-y += arch/arm64/kernel/ arch/arm64/mm/ arch/arm64/net/ + core-$(CONFIG_KVM) += arch/arm64/kvm/ + core-$(CONFIG_XEN) += arch/arm64/xen/ + core-$(CONFIG_CRYPTO) += arch/arm64/crypto/ +--- a/kernel/bpf/Kconfig ++++ b/kernel/bpf/Kconfig +@@ -34,6 +34,7 @@ config BPF_SYSCALL + + config BPF_JIT + bool "Enable BPF Just In Time compiler" ++ depends on BPF + depends on HAVE_CBPF_JIT || HAVE_EBPF_JIT + depends on MODULES + help diff --git a/patches.suse/bpf-Remove-MTU-check-in-__bpf_skb_max_len.patch b/patches.suse/bpf-Remove-MTU-check-in-__bpf_skb_max_len.patch index 4920353..3de3d25 100644 --- a/patches.suse/bpf-Remove-MTU-check-in-__bpf_skb_max_len.patch +++ b/patches.suse/bpf-Remove-MTU-check-in-__bpf_skb_max_len.patch @@ -3,7 +3,7 @@ Date: Tue, 9 Feb 2021 14:38:09 +0100 Subject: bpf: Remove MTU check in __bpf_skb_max_len Patch-mainline: v5.12-rc1 Git-commit: 6306c1189e77a513bf02720450bb43bd4ba5d8ae -References: bsc#1155518 +References: bsc#1155518 bsc#1192045 CVE-2021-0941 Multiple BPF-helpers that can manipulate/increase the size of the SKB uses __bpf_skb_max_len() as the max-length. This function limit size against diff --git a/patches.suse/bpf-kconfig-Add-consolidated-menu-entry-for-bpf-with.patch b/patches.suse/bpf-kconfig-Add-consolidated-menu-entry-for-bpf-with.patch new file mode 100644 index 0000000..a540a9c --- /dev/null +++ b/patches.suse/bpf-kconfig-Add-consolidated-menu-entry-for-bpf-with.patch @@ -0,0 +1,197 @@ +From: Daniel Borkmann +Date: Tue, 11 May 2021 22:35:16 +0200 +Subject: bpf, kconfig: Add consolidated menu entry for bpf with core options +Patch-mainline: v5.13-rc4 +Git-commit: b24abcff918a5cbf44b0c982bd3477a93e8e4911 +References: jsc#SLE-22574 + +Right now, all core BPF related options are scattered in different Kconfig +locations mainly due to historic reasons. Moving forward, lets add a proper +subsystem entry under ... + + General setup ---> + BPF subsystem ---> + +... in order to have all knobs in a single location and thus ease BPF related +configuration. Networking related bits such as sockmap are out of scope for +the general setup and therefore better suited to remain in net/Kconfig. + +Signed-off-by: Daniel Borkmann +Signed-off-by: Alexei Starovoitov +Link: https://lore.kernel.org/bpf/f23f58765a4d59244ebd8037da7b6a6b2fb58446.1620765074.git.daniel@iogearbox.net +Acked-by: Shung-Hsi Yu +--- + init/Kconfig | 36 -------------------------- + kernel/bpf/Kconfig | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++++ + net/Kconfig | 27 ------------------- + 3 files changed, 74 insertions(+), 62 deletions(-) + create mode 100644 kernel/bpf/Kconfig + +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -361,6 +361,7 @@ config AUDITSYSCALL + + source "kernel/irq/Kconfig" + source "kernel/time/Kconfig" ++source "kernel/bpf/Kconfig" + source "kernel/Kconfig.preempt" + + menu "CPU/Task time and stats accounting" +@@ -1571,41 +1572,6 @@ config KALLSYMS_BASE_RELATIVE + + # syscall, maps, verifier + +-config BPF_LSM +- bool "LSM Instrumentation with BPF" +- depends on BPF_EVENTS +- depends on BPF_SYSCALL +- depends on SECURITY +- depends on BPF_JIT +- help +- Enables instrumentation of the security hooks with eBPF programs for +- implementing dynamic MAC and Audit Policies. +- +- If you are unsure how to answer this question, answer N. +- +-config BPF_SYSCALL +- bool "Enable bpf() system call" +- select BPF +- select IRQ_WORK +- default n +- help +- Enable the bpf() system call that allows to manipulate eBPF +- programs and maps via file descriptors. +- +-config ARCH_WANT_DEFAULT_BPF_JIT +- bool +- +-config BPF_JIT_ALWAYS_ON +- bool "Permanently enable BPF JIT and remove BPF interpreter" +- depends on BPF_SYSCALL && HAVE_EBPF_JIT && BPF_JIT +- help +- Enables BPF JIT and removes BPF interpreter to avoid +- speculative execution of BPF instructions by the interpreter +- +-config BPF_JIT_DEFAULT_ON +- def_bool ARCH_WANT_DEFAULT_BPF_JIT || BPF_JIT_ALWAYS_ON +- depends on HAVE_EBPF_JIT && BPF_JIT +- + config USERFAULTFD + bool "Enable userfaultfd() system call" + depends on MMU +--- /dev/null ++++ b/kernel/bpf/Kconfig +@@ -0,0 +1,73 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++# BPF interpreter that, for example, classic socket filters depend on. ++config BPF ++ bool ++ ++# Used by archs to tell that they support BPF JIT compiler plus which ++# flavour. Only one of the two can be selected for a specific arch since ++# eBPF JIT supersedes the cBPF JIT. ++ ++# Classic BPF JIT (cBPF) ++config HAVE_CBPF_JIT ++ bool ++ ++# Extended BPF JIT (eBPF) ++config HAVE_EBPF_JIT ++ bool ++ ++# Used by archs to tell that they want the BPF JIT compiler enabled by ++# default for kernels that were compiled with BPF JIT support. ++config ARCH_WANT_DEFAULT_BPF_JIT ++ bool ++ ++menu "BPF subsystem" ++ ++config BPF_SYSCALL ++ bool "Enable bpf() system call" ++ select BPF ++ select IRQ_WORK ++ default n ++ help ++ Enable the bpf() system call that allows to manipulate BPF programs ++ and maps via file descriptors. ++ ++config BPF_JIT ++ bool "Enable BPF Just In Time compiler" ++ depends on HAVE_CBPF_JIT || HAVE_EBPF_JIT ++ depends on MODULES ++ help ++ BPF programs are normally handled by a BPF interpreter. This option ++ allows the kernel to generate native code when a program is loaded ++ into the kernel. This will significantly speed-up processing of BPF ++ programs. ++ ++ Note, an admin should enable this feature changing: ++ /proc/sys/net/core/bpf_jit_enable ++ /proc/sys/net/core/bpf_jit_harden (optional) ++ /proc/sys/net/core/bpf_jit_kallsyms (optional) ++ ++config BPF_JIT_ALWAYS_ON ++ bool "Permanently enable BPF JIT and remove BPF interpreter" ++ depends on BPF_SYSCALL && HAVE_EBPF_JIT && BPF_JIT ++ help ++ Enables BPF JIT and removes BPF interpreter to avoid speculative ++ execution of BPF instructions by the interpreter. ++ ++config BPF_JIT_DEFAULT_ON ++ def_bool ARCH_WANT_DEFAULT_BPF_JIT || BPF_JIT_ALWAYS_ON ++ depends on HAVE_EBPF_JIT && BPF_JIT ++ ++config BPF_LSM ++ bool "Enable BPF LSM Instrumentation" ++ depends on BPF_EVENTS ++ depends on BPF_SYSCALL ++ depends on SECURITY ++ depends on BPF_JIT ++ help ++ Enables instrumentation of the security hooks with BPF programs for ++ implementing dynamic MAC and Audit Policies. ++ ++ If you are unsure how to answer this question, answer N. ++ ++endmenu # "BPF subsystem" +--- a/net/Kconfig ++++ b/net/Kconfig +@@ -290,21 +290,6 @@ config BQL + select DQL + default y + +-config BPF_JIT +- bool "enable BPF Just In Time compiler" +- depends on HAVE_CBPF_JIT || HAVE_EBPF_JIT +- depends on MODULES +- ---help--- +- Berkeley Packet Filter filtering capabilities are normally handled +- by an interpreter. This option allows kernel to generate a native +- code when filter is loaded in memory. This should speedup +- packet sniffing (libpcap/tcpdump). +- +- Note, admin should enable this feature changing: +- /proc/sys/net/core/bpf_jit_enable +- /proc/sys/net/core/bpf_jit_harden (optional) +- /proc/sys/net/core/bpf_jit_kallsyms (optional) +- + config BPF_STREAM_PARSER + bool "enable BPF STREAM_PARSER" + depends on INET +@@ -461,15 +446,3 @@ config ETHTOOL_NETLINK + e.g. notification messages. + + endif # if NET +- +-# Used by archs to tell that they support BPF JIT compiler plus which flavour. +-# Only one of the two can be selected for a specific arch since eBPF JIT supersedes +-# the cBPF JIT. +- +-# Classic BPF JIT (cBPF) +-config HAVE_CBPF_JIT +- bool +- +-# Extended BPF JIT (eBPF) +-config HAVE_EBPF_JIT +- bool diff --git a/patches.suse/btrfs-block-group-Rework-documentation-of-check_syst.patch b/patches.suse/btrfs-block-group-Rework-documentation-of-check_syst.patch new file mode 100644 index 0000000..c91bed9 --- /dev/null +++ b/patches.suse/btrfs-block-group-Rework-documentation-of-check_syst.patch @@ -0,0 +1,42 @@ +From: Marcos Paulo de Souza +Date: Mon, 7 Oct 2019 21:50:38 -0300 +Git-commit: a9143bd31c6ab52f6a320a1a4254f2a2934610b1 +Patch-mainline: v5.5-rc1 +References: bsc#1192896 +Subject: [PATCH] btrfs: block-group: Rework documentation of + check_system_chunk function + +Commit 4617ea3a52cf (" Btrfs: fix necessary chunk tree space calculation +when allocating a chunk") removed the is_allocation argument from +check_system_chunk, since the formula for reserving the necessary space +for allocation or removing a chunk would be the same. + +So, rework the comment by removing the mention of is_allocation +argument. + +Signed-off-by: Marcos Paulo de Souza +Reviewed-by: Nikolay Borisov +Signed-off-by: David Sterba +Signed-off-by: Filipe Manana +--- + fs/btrfs/block-group.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/fs/btrfs/block-group.c b/fs/btrfs/block-group.c +index 53e08f925260..384659dc7818 100644 +--- a/fs/btrfs/block-group.c ++++ b/fs/btrfs/block-group.c +@@ -2987,9 +2987,7 @@ static u64 get_profile_num_devs(struct btrfs_fs_info *fs_info, u64 type) + } + + /* +- * If @is_allocation is true, reserve space in the system space info necessary +- * for allocating a chunk, otherwise if it's false, reserve space necessary for +- * removing a chunk. ++ * Reserve space in the system space for allocating or removing a chunk + */ + void check_system_chunk(struct btrfs_trans_handle *trans, u64 type) + { +-- +2.26.2 + diff --git a/patches.suse/btrfs-btrfs-use-the-new-VFS-super_block_dev.patch b/patches.suse/btrfs-btrfs-use-the-new-VFS-super_block_dev.patch index 84e25dd..0b0dc32 100644 --- a/patches.suse/btrfs-btrfs-use-the-new-VFS-super_block_dev.patch +++ b/patches.suse/btrfs-btrfs-use-the-new-VFS-super_block_dev.patch @@ -1,7 +1,7 @@ From: "Luis R. Rodriguez" Date: Wed, 13 Aug 2014 16:05:22 -0400 Subject: btrfs: use the new VFS super_block_dev -Patch-mainline: submitted, but not accepted +Patch-mainline: Never, submitted but not accepted References: bsc#865869 Use the new VFS layer struct super_block_dev instead of carrying diff --git a/patches.suse/btrfs-fix-deadlock-between-chunk-allocation-and-chun.patch b/patches.suse/btrfs-fix-deadlock-between-chunk-allocation-and-chun.patch new file mode 100644 index 0000000..51b66b8 --- /dev/null +++ b/patches.suse/btrfs-fix-deadlock-between-chunk-allocation-and-chun.patch @@ -0,0 +1,454 @@ +From: Filipe Manana +Date: Wed, 13 Oct 2021 10:12:49 +0100 +Git-commit: 2bb2e00ed9787e52580bb651264b8d6a2b7a9dd2 +Patch-mainline: v5.16-rc1 +References: bsc#1192896 +Subject: [PATCH] btrfs: fix deadlock between chunk allocation and chunk btree + modifications + +When a task is doing some modification to the chunk btree and it is not in +the context of a chunk allocation or a chunk removal, it can deadlock with +another task that is currently allocating a new data or metadata chunk. + +These contexts are the following: + +* When relocating a system chunk, when we need to COW the extent buffers + that belong to the chunk btree; + +* When adding a new device (ioctl), where we need to add a new device item + to the chunk btree; + +* When removing a device (ioctl), where we need to remove a device item + from the chunk btree; + +* When resizing a device (ioctl), where we need to update a device item in + the chunk btree and may need to relocate a system chunk that lies beyond + the new device size when shrinking a device. + +The problem happens due to a sequence of steps like the following: + +1) Task A starts a data or metadata chunk allocation and it locks the + chunk mutex; + +2) Task B is relocating a system chunk, and when it needs to COW an extent + buffer of the chunk btree, it has locked both that extent buffer as + well as its parent extent buffer; + +3) Since there is not enough available system space, either because none + of the existing system block groups have enough free space or because + the only one with enough free space is in RO mode due to the relocation, + task B triggers a new system chunk allocation. It blocks when trying to + acquire the chunk mutex, currently held by task A; + +4) Task A enters btrfs_chunk_alloc_add_chunk_item(), in order to insert + the new chunk item into the chunk btree and update the existing device + items there. But in order to do that, it has to lock the extent buffer + that task B locked at step 2, or its parent extent buffer, but task B + is waiting on the chunk mutex, which is currently locked by task A, + therefore resulting in a deadlock. + +One example report when the deadlock happens with system chunk relocation: + + INFO: task kworker/u9:5:546 blocked for more than 143 seconds. + Not tainted 5.15.0-rc3+ #1 + "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. + task:kworker/u9:5 state:D stack:25936 pid: 546 ppid: 2 flags:0x00004000 + Workqueue: events_unbound btrfs_async_reclaim_metadata_space + Call Trace: + context_switch kernel/sched/core.c:4940 [inline] + __schedule+0xcd9/0x2530 kernel/sched/core.c:6287 + schedule+0xd3/0x270 kernel/sched/core.c:6366 + rwsem_down_read_slowpath+0x4ee/0x9d0 kernel/locking/rwsem.c:993 + __down_read_common kernel/locking/rwsem.c:1214 [inline] + __down_read kernel/locking/rwsem.c:1223 [inline] + down_read_nested+0xe6/0x440 kernel/locking/rwsem.c:1590 + __btrfs_tree_read_lock+0x31/0x350 fs/btrfs/locking.c:47 + btrfs_tree_read_lock fs/btrfs/locking.c:54 [inline] + btrfs_read_lock_root_node+0x8a/0x320 fs/btrfs/locking.c:191 + btrfs_search_slot_get_root fs/btrfs/ctree.c:1623 [inline] + btrfs_search_slot+0x13b4/0x2140 fs/btrfs/ctree.c:1728 + btrfs_update_device+0x11f/0x500 fs/btrfs/volumes.c:2794 + btrfs_chunk_alloc_add_chunk_item+0x34d/0xea0 fs/btrfs/volumes.c:5504 + do_chunk_alloc fs/btrfs/block-group.c:3408 [inline] + btrfs_chunk_alloc+0x84d/0xf50 fs/btrfs/block-group.c:3653 + flush_space+0x54e/0xd80 fs/btrfs/space-info.c:670 + btrfs_async_reclaim_metadata_space+0x396/0xa90 fs/btrfs/space-info.c:953 + process_one_work+0x9df/0x16d0 kernel/workqueue.c:2297 + worker_thread+0x90/0xed0 kernel/workqueue.c:2444 + kthread+0x3e5/0x4d0 kernel/kthread.c:319 + ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:295 + INFO: task syz-executor:9107 blocked for more than 143 seconds. + Not tainted 5.15.0-rc3+ #1 + "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. + task:syz-executor state:D stack:23200 pid: 9107 ppid: 7792 flags:0x00004004 + Call Trace: + context_switch kernel/sched/core.c:4940 [inline] + __schedule+0xcd9/0x2530 kernel/sched/core.c:6287 + schedule+0xd3/0x270 kernel/sched/core.c:6366 + schedule_preempt_disabled+0xf/0x20 kernel/sched/core.c:6425 + __mutex_lock_common kernel/locking/mutex.c:669 [inline] + __mutex_lock+0xc96/0x1680 kernel/locking/mutex.c:729 + btrfs_chunk_alloc+0x31a/0xf50 fs/btrfs/block-group.c:3631 + find_free_extent_update_loop fs/btrfs/extent-tree.c:3986 [inline] + find_free_extent+0x25cb/0x3a30 fs/btrfs/extent-tree.c:4335 + btrfs_reserve_extent+0x1f1/0x500 fs/btrfs/extent-tree.c:4415 + btrfs_alloc_tree_block+0x203/0x1120 fs/btrfs/extent-tree.c:4813 + __btrfs_cow_block+0x412/0x1620 fs/btrfs/ctree.c:415 + btrfs_cow_block+0x2f6/0x8c0 fs/btrfs/ctree.c:570 + btrfs_search_slot+0x1094/0x2140 fs/btrfs/ctree.c:1768 + relocate_tree_block fs/btrfs/relocation.c:2694 [inline] + relocate_tree_blocks+0xf73/0x1770 fs/btrfs/relocation.c:2757 + relocate_block_group+0x47e/0xc70 fs/btrfs/relocation.c:3673 + btrfs_relocate_block_group+0x48a/0xc60 fs/btrfs/relocation.c:4070 + btrfs_relocate_chunk+0x96/0x280 fs/btrfs/volumes.c:3181 + __btrfs_balance fs/btrfs/volumes.c:3911 [inline] + btrfs_balance+0x1f03/0x3cd0 fs/btrfs/volumes.c:4301 + btrfs_ioctl_balance+0x61e/0x800 fs/btrfs/ioctl.c:4137 + btrfs_ioctl+0x39ea/0x7b70 fs/btrfs/ioctl.c:4949 + vfs_ioctl fs/ioctl.c:51 [inline] + __do_sys_ioctl fs/ioctl.c:874 [inline] + __se_sys_ioctl fs/ioctl.c:860 [inline] + __x64_sys_ioctl+0x193/0x200 fs/ioctl.c:860 + do_syscall_x64 arch/x86/entry/common.c:50 [inline] + do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80 + entry_SYSCALL_64_after_hwframe+0x44/0xae + +So fix this by making sure that whenever we try to modify the chunk btree +and we are neither in a chunk allocation context nor in a chunk remove +context, we reserve system space before modifying the chunk btree. + +Reported-by: Hao Sun +Link: https://lore.kernel.org/linux-btrfs/CACkBjsax51i4mu6C0C3vJqQN3NR_iVuucoeG3U1HXjrgzn5FFQ@mail.gmail.com/ +Fixes: 79bd37120b1495 ("btrfs: rework chunk allocation to avoid exhaustion of the system chunk array") +CC: stable@vger.kernel.org # 5.14+ +Reviewed-by: Josef Bacik +Signed-off-by: Filipe Manana +Signed-off-by: David Sterba +--- + fs/btrfs/block-group.c | 146 +++++++++++++++++++++++++---------------- + fs/btrfs/block-group.h | 2 + + fs/btrfs/relocation.c | 4 ++ + fs/btrfs/volumes.c | 15 ++++- + 4 files changed, 111 insertions(+), 56 deletions(-) + +diff --git a/fs/btrfs/block-group.c b/fs/btrfs/block-group.c +index c9dee3189..bb2c34743 100644 +--- a/fs/btrfs/block-group.c ++++ b/fs/btrfs/block-group.c +@@ -2992,25 +2992,6 @@ static int do_chunk_alloc(struct btrfs_trans_handle *trans, u64 flags) + goto out; + } + +- /* +- * If this is a system chunk allocation then stop right here and do not +- * add the chunk item to the chunk btree. This is to prevent a deadlock +- * because this system chunk allocation can be triggered while COWing +- * some extent buffer of the chunk btree and while holding a lock on a +- * parent extent buffer, in which case attempting to insert the chunk +- * item (or update the device item) would result in a deadlock on that +- * parent extent buffer. In this case defer the chunk btree updates to +- * the second phase of chunk allocation and keep our reservation until +- * the second phase completes. +- * +- * This is a rare case and can only be triggered by the very few cases +- * we have where we need to touch the chunk btree outside chunk allocation +- * and chunk removal. These cases are basically adding a device, removing +- * a device or resizing a device. +- */ +- if (flags & BTRFS_BLOCK_GROUP_SYSTEM) +- return 0; +- + ret = btrfs_chunk_alloc_add_chunk_item(trans, bg); + /* + * Normally we are not expected to fail with -ENOSPC here, since we have +@@ -3143,14 +3124,14 @@ static int do_chunk_alloc(struct btrfs_trans_handle *trans, u64 flags) + * This has happened before and commit eafa4fd0ad0607 ("btrfs: fix exhaustion of + * the system chunk array due to concurrent allocations") provides more details. + * +- * For allocation of system chunks, we defer the updates and insertions into the +- * chunk btree to phase 2. This is to prevent deadlocks on extent buffers because +- * if the chunk allocation is triggered while COWing an extent buffer of the +- * chunk btree, we are holding a lock on the parent of that extent buffer and +- * doing the chunk btree updates and insertions can require locking that parent. +- * This is for the very few and rare cases where we update the chunk btree that +- * are not chunk allocation or chunk removal: adding a device, removing a device +- * or resizing a device. ++ * Allocation of system chunks does not happen through this function. A task that ++ * needs to update the chunk btree (the only btree that uses system chunks), must ++ * preallocate chunk space by calling either check_system_chunk() or ++ * btrfs_reserve_chunk_metadata() - the former is used when allocating a data or ++ * metadata chunk or when removing a chunk, while the later is used before doing ++ * a modification to the chunk btree - use cases for the later are adding, ++ * removing and resizing a device as well as relocation of a system chunk. ++ * See the comment below for more details. + * + * The reservation of system space, done through check_system_chunk(), as well + * as all the updates and insertions into the chunk btree must be done while +@@ -3187,11 +3168,27 @@ int btrfs_chunk_alloc(struct btrfs_trans_handle *trans, u64 flags, + if (trans->allocating_chunk) + return -ENOSPC; + /* +- * If we are removing a chunk, don't re-enter or we would deadlock. +- * System space reservation and system chunk allocation is done by the +- * chunk remove operation (btrfs_remove_chunk()). ++ * Allocation of system chunks can not happen through this path, as we ++ * could end up in a deadlock if we are allocating a data or metadata ++ * chunk and there is another task modifying the chunk btree. ++ * ++ * This is because while we are holding the chunk mutex, we will attempt ++ * to add the new chunk item to the chunk btree or update an existing ++ * device item in the chunk btree, while the other task that is modifying ++ * the chunk btree is attempting to COW an extent buffer while holding a ++ * lock on it and on its parent - if the COW operation triggers a system ++ * chunk allocation, then we can deadlock because we are holding the ++ * chunk mutex and we may need to access that extent buffer or its parent ++ * in order to add the chunk item or update a device item. ++ * ++ * Tasks that want to modify the chunk tree should reserve system space ++ * before updating the chunk btree, by calling either ++ * btrfs_reserve_chunk_metadata() or check_system_chunk(). ++ * It's possible that after a task reserves the space, it still ends up ++ * here - this happens in the cases described above at do_chunk_alloc(). ++ * The task will have to either retry or fail. + */ +- if (trans->removing_chunk) ++ if (flags & BTRFS_BLOCK_GROUP_SYSTEM) + return -ENOSPC; + + space_info = btrfs_find_space_info(fs_info, flags); +@@ -3290,17 +3287,14 @@ static u64 get_profile_num_devs(struct btrfs_fs_info *fs_info, u64 type) + return num_dev; + } + +-/* +- * Reserve space in the system space for allocating or removing a chunk +- */ +-void check_system_chunk(struct btrfs_trans_handle *trans, u64 type) ++static void reserve_chunk_space(struct btrfs_trans_handle *trans, ++ u64 bytes, ++ u64 type) + { + struct btrfs_fs_info *fs_info = trans->fs_info; + struct btrfs_space_info *info; + u64 left; +- u64 thresh; + int ret = 0; +- u64 num_devs; + + /* + * Needed because we can end up allocating a system chunk and for an +@@ -3313,19 +3307,13 @@ void check_system_chunk(struct btrfs_trans_handle *trans, u64 type) + left = info->total_bytes - btrfs_space_info_used(info, true); + spin_unlock(&info->lock); + +- num_devs = get_profile_num_devs(fs_info, type); +- +- /* num_devs device items to update and 1 chunk item to add or remove */ +- thresh = btrfs_calc_metadata_size(fs_info, num_devs) + +- btrfs_calc_insert_metadata_size(fs_info, 1); +- +- if (left < thresh && btrfs_test_opt(fs_info, ENOSPC_DEBUG)) { ++ if (left < bytes && btrfs_test_opt(fs_info, ENOSPC_DEBUG)) { + btrfs_info(fs_info, "left=%llu, need=%llu, flags=%llu", +- left, thresh, type); ++ left, bytes, type); + btrfs_dump_space_info(fs_info, info, 0, 0); + } + +- if (left < thresh) { ++ if (left < bytes) { + u64 flags = btrfs_system_alloc_profile(fs_info); + struct btrfs_block_group *bg; + +@@ -3334,21 +3322,20 @@ void check_system_chunk(struct btrfs_trans_handle *trans, u64 type) + * needing it, as we might not need to COW all nodes/leafs from + * the paths we visit in the chunk tree (they were already COWed + * or created in the current transaction for example). +- * +- * Also, if our caller is allocating a system chunk, do not +- * attempt to insert the chunk item in the chunk btree, as we +- * could deadlock on an extent buffer since our caller may be +- * COWing an extent buffer from the chunk btree. + */ + bg = btrfs_alloc_chunk(trans, flags); + if (IS_ERR(bg)) { + ret = PTR_ERR(bg); +- } else if (!(type & BTRFS_BLOCK_GROUP_SYSTEM)) { ++ } else { + /* + * If we fail to add the chunk item here, we end up + * trying again at phase 2 of chunk allocation, at + * btrfs_create_pending_block_groups(). So ignore +- * any error here. ++ * any error here. An ENOSPC here could happen, due to ++ * the cases described at do_chunk_alloc() - the system ++ * block group we just created was just turned into RO ++ * mode by a scrub for example, or a running discard ++ * temporarily removed its free space entries, etc. + */ + btrfs_chunk_alloc_add_chunk_item(trans, bg); + } +@@ -3357,12 +3344,61 @@ void check_system_chunk(struct btrfs_trans_handle *trans, u64 type) + if (!ret) { + ret = btrfs_block_rsv_add(fs_info->chunk_root, + &fs_info->chunk_block_rsv, +- thresh, BTRFS_RESERVE_NO_FLUSH); ++ bytes, BTRFS_RESERVE_NO_FLUSH); + if (!ret) +- trans->chunk_bytes_reserved += thresh; ++ trans->chunk_bytes_reserved += bytes; + } + } + ++/* ++ * Reserve space in the system space for allocating or removing a chunk. ++ * The caller must be holding fs_info->chunk_mutex. ++ */ ++void check_system_chunk(struct btrfs_trans_handle *trans, u64 type) ++{ ++ struct btrfs_fs_info *fs_info = trans->fs_info; ++ const u64 num_devs = get_profile_num_devs(fs_info, type); ++ u64 bytes; ++ ++ /* num_devs device items to update and 1 chunk item to add or remove. */ ++ bytes = btrfs_calc_metadata_size(fs_info, num_devs) + ++ btrfs_calc_insert_metadata_size(fs_info, 1); ++ ++ reserve_chunk_space(trans, bytes, type); ++} ++ ++/* ++ * Reserve space in the system space, if needed, for doing a modification to the ++ * chunk btree. ++ * ++ * @trans: A transaction handle. ++ * @is_item_insertion: Indicate if the modification is for inserting a new item ++ * in the chunk btree or if it's for the deletion or update ++ * of an existing item. ++ * ++ * This is used in a context where we need to update the chunk btree outside ++ * block group allocation and removal, to avoid a deadlock with a concurrent ++ * task that is allocating a metadata or data block group and therefore needs to ++ * update the chunk btree while holding the chunk mutex. After the update to the ++ * chunk btree is done, btrfs_trans_release_chunk_metadata() should be called. ++ * ++ */ ++void btrfs_reserve_chunk_metadata(struct btrfs_trans_handle *trans, ++ bool is_item_insertion) ++{ ++ struct btrfs_fs_info *fs_info = trans->fs_info; ++ u64 bytes; ++ ++ if (is_item_insertion) ++ bytes = btrfs_calc_insert_metadata_size(fs_info, 1); ++ else ++ bytes = btrfs_calc_metadata_size(fs_info, 1); ++ ++ mutex_lock(&fs_info->chunk_mutex); ++ reserve_chunk_space(trans, bytes, BTRFS_BLOCK_GROUP_SYSTEM); ++ mutex_unlock(&fs_info->chunk_mutex); ++} ++ + void btrfs_put_block_group_cache(struct btrfs_fs_info *info) + { + struct btrfs_block_group *block_group; +diff --git a/fs/btrfs/block-group.h b/fs/btrfs/block-group.h +index fb10eea11..970c79577 100644 +--- a/fs/btrfs/block-group.h ++++ b/fs/btrfs/block-group.h +@@ -237,6 +237,8 @@ int btrfs_chunk_alloc(struct btrfs_trans_handle *trans, u64 flags, + enum btrfs_chunk_alloc_enum force); + int btrfs_force_chunk_alloc(struct btrfs_trans_handle *trans, u64 type); + void check_system_chunk(struct btrfs_trans_handle *trans, const u64 type); ++void btrfs_reserve_chunk_metadata(struct btrfs_trans_handle *trans, ++ bool is_item_insertion); + u64 btrfs_get_alloc_profile(struct btrfs_fs_info *fs_info, u64 orig_flags); + void btrfs_put_block_group_cache(struct btrfs_fs_info *info); + int btrfs_free_block_groups(struct btrfs_fs_info *info); +diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c +index c16181c76..1a50b8071 100644 +--- a/fs/btrfs/relocation.c ++++ b/fs/btrfs/relocation.c +@@ -3199,8 +3199,12 @@ static int relocate_tree_block(struct btrfs_trans_handle *trans, + list_add_tail(&node->list, &rc->backref_cache.changed); + } else { + path->lowest_level = node->level; ++ if (root == root->fs_info->chunk_root) ++ btrfs_reserve_chunk_metadata(trans, false); + ret = btrfs_search_slot(trans, root, key, path, 0, 1); + btrfs_release_path(path); ++ if (root == root->fs_info->chunk_root) ++ btrfs_trans_release_chunk_metadata(trans); + if (ret > 0) + ret = 0; + } +diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c +index 71e993d94..c5849db6e 100644 +--- a/fs/btrfs/volumes.c ++++ b/fs/btrfs/volumes.c +@@ -1992,8 +1992,10 @@ static int btrfs_add_dev_item(struct btrfs_trans_handle *trans, + key.type = BTRFS_DEV_ITEM_KEY; + key.offset = device->devid; + ++ btrfs_reserve_chunk_metadata(trans, true); + ret = btrfs_insert_empty_item(trans, trans->fs_info->chunk_root, path, + &key, sizeof(*dev_item)); ++ btrfs_trans_release_chunk_metadata(trans); + if (ret) + goto out; + +@@ -2064,7 +2066,9 @@ static int btrfs_rm_dev_item(struct btrfs_device *device) + key.type = BTRFS_DEV_ITEM_KEY; + key.offset = device->devid; + ++ btrfs_reserve_chunk_metadata(trans, false); + ret = btrfs_search_slot(trans, root, &key, path, -1, 1); ++ btrfs_trans_release_chunk_metadata(trans); + if (ret) { + if (ret > 0) + ret = -ENOENT; +@@ -2590,7 +2594,9 @@ static int btrfs_finish_sprout(struct btrfs_trans_handle *trans) + key.type = BTRFS_DEV_ITEM_KEY; + + while (1) { ++ btrfs_reserve_chunk_metadata(trans, false); + ret = btrfs_search_slot(trans, root, &key, path, 0, 1); ++ btrfs_trans_release_chunk_metadata(trans); + if (ret < 0) + goto error; + +@@ -2918,6 +2924,7 @@ int btrfs_grow_device(struct btrfs_trans_handle *trans, + struct btrfs_super_block *super_copy = fs_info->super_copy; + u64 old_total; + u64 diff; ++ int ret; + + if (!test_bit(BTRFS_DEV_STATE_WRITEABLE, &device->dev_state)) + return -EACCES; +@@ -2946,7 +2953,11 @@ int btrfs_grow_device(struct btrfs_trans_handle *trans, + &trans->transaction->dev_update_list); + mutex_unlock(&fs_info->chunk_mutex); + +- return btrfs_update_device(trans, device); ++ btrfs_reserve_chunk_metadata(trans, false); ++ ret = btrfs_update_device(trans, device); ++ btrfs_trans_release_chunk_metadata(trans); ++ ++ return ret; + } + + static int btrfs_free_chunk(struct btrfs_trans_handle *trans, u64 chunk_offset) +@@ -5032,8 +5043,10 @@ int btrfs_shrink_device(struct btrfs_device *device, u64 new_size) + round_down(old_total - diff, fs_info->sectorsize)); + mutex_unlock(&fs_info->chunk_mutex); + ++ btrfs_reserve_chunk_metadata(trans, false); + /* Now btrfs_update_device() will change the on-disk size. */ + ret = btrfs_update_device(trans, device); ++ btrfs_trans_release_chunk_metadata(trans); + if (ret < 0) { + btrfs_abort_transaction(trans, ret); + btrfs_end_transaction(trans); +-- +2.26.2 + diff --git a/patches.suse/btrfs-fix-memory-ordering-between-normal-and-ordered-work-functions.patch b/patches.suse/btrfs-fix-memory-ordering-between-normal-and-ordered-work-functions.patch new file mode 100644 index 0000000..46c2d5e --- /dev/null +++ b/patches.suse/btrfs-fix-memory-ordering-between-normal-and-ordered-work-functions.patch @@ -0,0 +1,83 @@ +From: Nikolay Borisov +Date: Tue, 2 Nov 2021 14:49:16 +0200 +Subject: btrfs: fix memory ordering between normal and ordered work functions +Git-commit: 45da9c1767ac31857df572f0a909fbe88fd5a7e9 +Patch-mainline: v5.16-rc2 +References: git-fixes + +Ordered work functions aren't guaranteed to be handled by the same thread +which executed the normal work functions. The only way execution between +normal/ordered functions is synchronized is via the WORK_DONE_BIT, +unfortunately the used bitops don't guarantee any ordering whatsoever. + +This manifested as seemingly inexplicable crashes on ARM64, where +async_chunk::inode is seen as non-null in async_cow_submit which causes +submit_compressed_extents to be called and crash occurs because +async_chunk::inode suddenly became NULL. The call trace was similar to: + + pc : submit_compressed_extents+0x38/0x3d0 + lr : async_cow_submit+0x50/0xd0 + sp : ffff800015d4bc20 + + + + Call trace: + submit_compressed_extents+0x38/0x3d0 + async_cow_submit+0x50/0xd0 + run_ordered_work+0xc8/0x280 + btrfs_work_helper+0x98/0x250 + process_one_work+0x1f0/0x4ac + worker_thread+0x188/0x504 + kthread+0x110/0x114 + ret_from_fork+0x10/0x18 + +Fix this by adding respective barrier calls which ensure that all +accesses preceding setting of WORK_DONE_BIT are strictly ordered before +setting the flag. At the same time add a read barrier after reading of +WORK_DONE_BIT in run_ordered_work which ensures all subsequent loads +would be strictly ordered after reading the bit. This in turn ensures +are all accesses before WORK_DONE_BIT are going to be strictly ordered +before any access that can occur in ordered_func. + +Reported-by: Chris Murphy +Fixes: 08a9ff326418 ("btrfs: Added btrfs_workqueue_struct implemented ordered execution based on kernel workqueue") +CC: stable@vger.kernel.org # 4.4+ +Link: https://bugzilla.redhat.com/show_bug.cgi?id=2011928 +Reviewed-by: Josef Bacik +Tested-by: Chris Murphy +Signed-off-by: Nikolay Borisov +Signed-off-by: David Sterba +--- + fs/btrfs/async-thread.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/fs/btrfs/async-thread.c ++++ b/fs/btrfs/async-thread.c +@@ -267,6 +267,13 @@ static void run_ordered_work(struct __bt + ordered_list); + if (!test_bit(WORK_DONE_BIT, &work->flags)) + break; ++ /* ++ * Orders all subsequent loads after reading WORK_DONE_BIT, ++ * paired with the smp_mb__before_atomic in btrfs_work_helper ++ * this guarantees that the ordered function will see all ++ * updates from ordinary work function. ++ */ ++ smp_rmb(); + + /* + * we are going to call the ordered done function, but +@@ -321,6 +328,13 @@ static void normal_work_helper(struct bt + thresh_exec_hook(wq); + work->func(work); + if (need_order) { ++ /* ++ * Ensures all memory accesses done in the work function are ++ * ordered before setting the WORK_DONE_BIT. Ensuring the thread ++ * which is going to executed the ordered work sees them. ++ * Pairs with the smp_rmb in run_ordered_work. ++ */ ++ smp_mb__before_atomic(); + set_bit(WORK_DONE_BIT, &work->flags); + run_ordered_work(wq); + } diff --git a/patches.suse/btrfs-fs-super.c-add-new-super-block-devices-super_block_d.patch b/patches.suse/btrfs-fs-super.c-add-new-super-block-devices-super_block_d.patch index c393c88..6f2c2a1 100644 --- a/patches.suse/btrfs-fs-super.c-add-new-super-block-devices-super_block_d.patch +++ b/patches.suse/btrfs-fs-super.c-add-new-super-block-devices-super_block_d.patch @@ -1,7 +1,7 @@ From: "Luis R. Rodriguez" Date: Wed, 16 Jul 2014 14:16:29 -0700 Subject: fs/super.c: add new super block sub devices super_block_dev -Patch-mainline: submitted, but not accepted +Patch-mainline: Never, submitted but not accepted References: bsc#865869, bsc#1178418 Modern filesystems are using the get_anon_bdev() for internal diff --git a/patches.suse/btrfs-provide-super_operations-get_inode_dev b/patches.suse/btrfs-provide-super_operations-get_inode_dev index 17e856e..ae4e67a 100644 --- a/patches.suse/btrfs-provide-super_operations-get_inode_dev +++ b/patches.suse/btrfs-provide-super_operations-get_inode_dev @@ -1,7 +1,7 @@ From: Jeff Mahoney Subject: btrfs: provide super_operations->inode_get_dev References: bsc#927455 -Patch-mainline: No, upstream wants a super_block per anon dev +Patch-mainline: Never, upstream wants a super_block per anon dev In order to ensure that the per-subvolume anonymous dev_t gets published to userspace, we need to provide the super_operations->get_inode_dev diff --git a/patches.suse/btrfs-update-comments-for-chunk-allocation-ENOSPC-ca.patch b/patches.suse/btrfs-update-comments-for-chunk-allocation-ENOSPC-ca.patch new file mode 100644 index 0000000..a90e8c1 --- /dev/null +++ b/patches.suse/btrfs-update-comments-for-chunk-allocation-ENOSPC-ca.patch @@ -0,0 +1,68 @@ +From: Filipe Manana +Date: Wed, 13 Oct 2021 10:12:50 +0100 +Git-commit: ecd84d54674a06e64613eae33999db8e180f4450 +Patch-mainline: v5.16-rc1 +References: bsc#1192896 +Subject: [PATCH] btrfs: update comments for chunk allocation -ENOSPC cases + +Update the comments at btrfs_chunk_alloc() and do_chunk_alloc() that +describe which cases can lead to a failure to allocate metadata and system +space despite having previously reserved space. This adds one more reason +that I previously forgot to mention. + +Reviewed-by: Josef Bacik +Signed-off-by: Filipe Manana +Signed-off-by: David Sterba +--- + fs/btrfs/block-group.c | 21 ++++++++++++++++++--- + 1 file changed, 18 insertions(+), 3 deletions(-) + +diff --git a/fs/btrfs/block-group.c b/fs/btrfs/block-group.c +index f971d043469c..444e9c89ff3e 100644 +--- a/fs/btrfs/block-group.c ++++ b/fs/btrfs/block-group.c +@@ -3429,7 +3429,7 @@ static int do_chunk_alloc(struct btrfs_trans_handle *trans, u64 flags) + /* + * Normally we are not expected to fail with -ENOSPC here, since we have + * previously reserved space in the system space_info and allocated one +- * new system chunk if necessary. However there are two exceptions: ++ * new system chunk if necessary. However there are three exceptions: + * + * 1) We may have enough free space in the system space_info but all the + * existing system block groups have a profile which can not be used +@@ -3455,7 +3455,14 @@ static int do_chunk_alloc(struct btrfs_trans_handle *trans, u64 flags) + * with enough free space got turned into RO mode by a running scrub, + * and in this case we have to allocate a new one and retry. We only + * need do this allocate and retry once, since we have a transaction +- * handle and scrub uses the commit root to search for block groups. ++ * handle and scrub uses the commit root to search for block groups; ++ * ++ * 3) We had one system block group with enough free space when we called ++ * check_system_chunk(), but after that, right before we tried to ++ * allocate the last extent buffer we needed, a discard operation came ++ * in and it temporarily removed the last free space entry from the ++ * block group (discard removes a free space entry, discards it, and ++ * then adds back the entry to the block group cache). + */ + if (ret == -ENOSPC) { + const u64 sys_flags = btrfs_system_alloc_profile(trans->fs_info); +@@ -3539,7 +3546,15 @@ static int do_chunk_alloc(struct btrfs_trans_handle *trans, u64 flags) + * properly, either intentionally or as a bug. One example where this is + * done intentionally is fsync, as it does not reserve any transaction units + * and ends up allocating a variable number of metadata extents for log +- * tree extent buffers. ++ * tree extent buffers; ++ * ++ * 4) The task has reserved enough transaction units / metadata space, but right ++ * before it tries to allocate the last extent buffer it needs, a discard ++ * operation comes in and, temporarily, removes the last free space entry from ++ * the only metadata block group that had free space (discard starts by ++ * removing a free space entry from a block group, then does the discard ++ * operation and, once it's done, it adds back the free space entry to the ++ * block group). + * + * We also need this 2 phases setup when adding a device to a filesystem with + * a seed device - we must create new metadata and system chunks without adding +-- +2.26.2 + diff --git a/patches.suse/cdrom-turn-off-autoclose-by-default.patch b/patches.suse/cdrom-turn-off-autoclose-by-default.patch index 845f2c5..ed9685d 100644 --- a/patches.suse/cdrom-turn-off-autoclose-by-default.patch +++ b/patches.suse/cdrom-turn-off-autoclose-by-default.patch @@ -4,7 +4,7 @@ Date: Wed, 28 Feb 2018 14:28:00 +0100 Subject: [PATCH] cdrom: turn off autoclose by default. References: bsc#1080813 -Patch-mainline: no, SUSE-specific +Patch-mainline: Never, SUSE-specific We ship system settings that turn off autoclose but before they are applied a program might access the cdrom and lock up if the drive diff --git a/patches.suse/crypto-pcrypt-Delay-write-to-padata-info.patch b/patches.suse/crypto-pcrypt-Delay-write-to-padata-info.patch new file mode 100644 index 0000000..28a8412 --- /dev/null +++ b/patches.suse/crypto-pcrypt-Delay-write-to-padata-info.patch @@ -0,0 +1,84 @@ +From 68b6dea802cea0dbdd8bd7ccc60716b5a32a5d8a Mon Sep 17 00:00:00 2001 +From: Daniel Jordan +Date: Thu, 21 Oct 2021 14:30:28 -0400 +Subject: [PATCH] crypto: pcrypt - Delay write to padata->info +Git-commit: 68b6dea802cea0dbdd8bd7ccc60716b5a32a5d8a +References: git-fixes +Patch-mainline: v5.16-rc1 + +These three events can race when pcrypt is used multiple times in a +template ("pcrypt(pcrypt(...))"): + + 1. [taskA] The caller makes the crypto request via crypto_aead_encrypt() + 2. [kworkerB] padata serializes the inner pcrypt request + 3. [kworkerC] padata serializes the outer pcrypt request + +3 might finish before the call to crypto_aead_encrypt() returns in 1, +resulting in two possible issues. + +First, a use-after-free of the crypto request's memory when, for +example, taskA writes to the outer pcrypt request's padata->info in +pcrypt_aead_enc() after kworkerC completes the request. + +Second, the outer pcrypt request overwrites the inner pcrypt request's +return code with -EINPROGRESS, making a successful request appear to +fail. For instance, kworkerB writes the outer pcrypt request's +padata->info in pcrypt_aead_done() and then taskA overwrites it +in pcrypt_aead_enc(). + +Avoid both situations by delaying the write of padata->info until after +the inner crypto request's return code is checked. This prevents the +use-after-free by not touching the crypto request's memory after the +next-inner crypto request is made, and stops padata->info from being +overwritten. + +Fixes: 5068c7a883d16 ("crypto: pcrypt - Add pcrypt crypto parallelization wrapper") +Reported-by: syzbot+b187b77c8474f9648fae@syzkaller.appspotmail.com +Signed-off-by: Daniel Jordan +Signed-off-by: Herbert Xu +Signed-off-by: Oliver Neukum +--- + crypto/pcrypt.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/crypto/pcrypt.c b/crypto/pcrypt.c +index d569c7ed6c80..9d10b846ccf7 100644 +--- a/crypto/pcrypt.c ++++ b/crypto/pcrypt.c +@@ -78,12 +78,14 @@ static void pcrypt_aead_enc(struct padata_priv *padata) + { + struct pcrypt_request *preq = pcrypt_padata_request(padata); + struct aead_request *req = pcrypt_request_ctx(preq); ++ int ret; + +- padata->info = crypto_aead_encrypt(req); ++ ret = crypto_aead_encrypt(req); + +- if (padata->info == -EINPROGRESS) ++ if (ret == -EINPROGRESS) + return; + ++ padata->info = ret; + padata_do_serial(padata); + } + +@@ -123,12 +125,14 @@ static void pcrypt_aead_dec(struct padata_priv *padata) + { + struct pcrypt_request *preq = pcrypt_padata_request(padata); + struct aead_request *req = pcrypt_request_ctx(preq); ++ int ret; + +- padata->info = crypto_aead_decrypt(req); ++ ret = crypto_aead_decrypt(req); + +- if (padata->info == -EINPROGRESS) ++ if (ret == -EINPROGRESS) + return; + ++ padata->info = ret; + padata_do_serial(padata); + } + +-- +2.26.2 + diff --git a/patches.suse/crypto_ccp-fix_resource_leaks_in_ccp_run_aes_gcm_cmd.patch b/patches.suse/crypto_ccp-fix_resource_leaks_in_ccp_run_aes_gcm_cmd.patch index 8b3cfb5..08ac20d 100644 --- a/patches.suse/crypto_ccp-fix_resource_leaks_in_ccp_run_aes_gcm_cmd.patch +++ b/patches.suse/crypto_ccp-fix_resource_leaks_in_ccp_run_aes_gcm_cmd.patch @@ -1,7 +1,8 @@ From: Dan Carpenter Date: Thu, 26 Aug 2021 16:04:27 +0300 Subject: crypto: ccp - fix resource leaks in ccp_run_aes_gcm_cmd() -Patch-mainline: not yet, will be queued in a subsystem tree soon +Patch-mainline: v5.15-rc4 +Git-commit: 505d9dcb0f7ddf9d075e729523a33d38642ae680 References: bsc#1189884 CVE-2021-3744 bsc#1190534 CVE-2021-3764 There are three bugs in this code: diff --git a/patches.suse/dm-ioctl-fix-out-of-bounds-array-access-when-no-devi.patch b/patches.suse/dm-ioctl-fix-out-of-bounds-array-access-when-no-devi.patch new file mode 100644 index 0000000..1611df5 --- /dev/null +++ b/patches.suse/dm-ioctl-fix-out-of-bounds-array-access-when-no-devi.patch @@ -0,0 +1,42 @@ +From 4edbe1d7bcffcd6269f3b5eb63f710393ff2ec7a Mon Sep 17 00:00:00 2001 +From: Mikulas Patocka +Date: Fri, 26 Mar 2021 14:32:32 -0400 +Subject: [PATCH] dm ioctl: fix out of bounds array access when no devices +Git-commit: 4edbe1d7bcffcd6269f3b5eb63f710393ff2ec7a +Patch-mainline: v5.12-rc5 +References: CVE-2021-31916 bsc#1192781 + +If there are not any dm devices, we need to zero the "dev" argument in +the first structure dm_name_list. However, this can cause out of +bounds write, because the "needed" variable is zero and len may be +less than eight. + +Fix this bug by reporting DM_BUFFER_FULL_FLAG if the result buffer is +too small to hold the "nl->dev" value. + +Signed-off-by: Mikulas Patocka +Reported-by: Dan Carpenter +Cc: stable@vger.kernel.org +Signed-off-by: Mike Snitzer +Acked-by: Takashi Iwai + +--- + drivers/md/dm-ioctl.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/md/dm-ioctl.c b/drivers/md/dm-ioctl.c +index 5e306bba4375..1ca65b434f1f 100644 +--- a/drivers/md/dm-ioctl.c ++++ b/drivers/md/dm-ioctl.c +@@ -529,7 +529,7 @@ static int list_devices(struct file *filp, struct dm_ioctl *param, size_t param_ + * Grab our output buffer. + */ + nl = orig_nl = get_result_buffer(param, param_size, &len); +- if (len < needed) { ++ if (len < needed || len < sizeof(nl->dev)) { + param->flags |= DM_BUFFER_FULL_FLAG; + goto out; + } +-- +2.26.2 + diff --git a/patches.suse/drm-i915-Introduce-intel_hpd_hotplug_irqs.patch b/patches.suse/drm-i915-Introduce-intel_hpd_hotplug_irqs.patch new file mode 100644 index 0000000..b9a872b --- /dev/null +++ b/patches.suse/drm-i915-Introduce-intel_hpd_hotplug_irqs.patch @@ -0,0 +1,164 @@ +From 6d3144eb367063df630248e0564b75701f63423b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Wed, 1 Jul 2020 00:56:00 +0300 +Subject: [PATCH] drm/i915: Introduce intel_hpd_hotplug_irqs() +Mime-version: 1.0 +Content-type: text/plain; charset=UTF-8 +Content-transfer-encoding: 8bit +Git-commit: 6d3144eb367063df630248e0564b75701f63423b +Patch-mainline: v5.10-rc1 +References: bsc#1192758 + +Introduce intel_hpd_hotplug_irqs() as a partner to +intel_hpd_enabled_irqs(). There's no need to care about the +encoders which we're not exposing, so we can avoid hardcoding +the masks in various places. + +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20200630215601.28557-12-ville.syrjala@linux.intel.com +Reviewed-by: José Roberto de Souza +Acked-by: Takashi Iwai + +--- + drivers/gpu/drm/i915/i915_irq.c | 50 +++++++++++++++------------------ + 1 file changed, 23 insertions(+), 27 deletions(-) + +diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c +index f5297bacf793..759f523c6a6b 100644 +--- a/drivers/gpu/drm/i915/i915_irq.c ++++ b/drivers/gpu/drm/i915/i915_irq.c +@@ -2987,6 +2987,18 @@ static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, + return enabled_irqs; + } + ++static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv, ++ const u32 hpd[HPD_NUM_PINS]) ++{ ++ struct intel_encoder *encoder; ++ u32 hotplug_irqs = 0; ++ ++ for_each_intel_encoder(&dev_priv->drm, encoder) ++ hotplug_irqs |= hpd[encoder->hpd_pin]; ++ ++ return hotplug_irqs; ++} ++ + static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) + { + u32 hotplug; +@@ -3016,12 +3028,8 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) + { + u32 hotplug_irqs, enabled_irqs; + +- if (HAS_PCH_IBX(dev_priv)) +- hotplug_irqs = SDE_HOTPLUG_MASK; +- else +- hotplug_irqs = SDE_HOTPLUG_MASK_CPT; +- + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); ++ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); + + ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); + +@@ -3049,13 +3057,12 @@ static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv, + } + + static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, +- u32 sde_ddi_mask, u32 sde_tc_mask, + u32 ddi_enable_mask, u32 tc_enable_mask) + { + u32 hotplug_irqs, enabled_irqs; + +- hotplug_irqs = sde_ddi_mask | sde_tc_mask; + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); ++ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); + + if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP) + I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); +@@ -3074,7 +3081,6 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, + static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) + { + icp_hpd_irq_setup(dev_priv, +- SDE_DDI_MASK_ICP, SDE_TC_HOTPLUG_ICP(PORT_TC1), + ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1)); + } + +@@ -3086,7 +3092,6 @@ static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) + static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) + { + icp_hpd_irq_setup(dev_priv, +- SDE_DDI_MASK_TGP, 0, + TGP_DDI_HPD_ENABLE_MASK, 0); + } + +@@ -3119,7 +3124,7 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) + u32 val; + + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); +- hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK; ++ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); + + val = I915_READ(GEN11_DE_HPD_IMR); + val &= ~hotplug_irqs; +@@ -3130,10 +3135,10 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) + gen11_hpd_detection_setup(dev_priv); + + if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP) +- icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_TGP, SDE_TC_MASK_TGP, ++ icp_hpd_irq_setup(dev_priv, + TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK); + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) +- icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_ICP, SDE_TC_MASK_ICP, ++ icp_hpd_irq_setup(dev_priv, + ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK); + } + +@@ -3169,8 +3174,8 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) + if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) + I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); + +- hotplug_irqs = SDE_HOTPLUG_MASK_SPT; + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); ++ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); + + ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); + +@@ -3197,22 +3202,13 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) + { + u32 hotplug_irqs, enabled_irqs; + +- if (INTEL_GEN(dev_priv) >= 8) { +- hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; +- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); ++ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); ++ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); + ++ if (INTEL_GEN(dev_priv) >= 8) + bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); +- } else if (INTEL_GEN(dev_priv) >= 7) { +- hotplug_irqs = DE_DP_A_HOTPLUG_IVB; +- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); +- +- ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); +- } else { +- hotplug_irqs = DE_DP_A_HOTPLUG; +- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); +- ++ else + ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); +- } + + ilk_hpd_detection_setup(dev_priv); + +@@ -3261,7 +3257,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) + u32 hotplug_irqs, enabled_irqs; + + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); +- hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; ++ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); + + bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); + +-- +2.26.2 + diff --git a/patches.suse/e1000e-Separate-TGP-board-type-from-SPT.patch b/patches.suse/e1000e-Separate-TGP-board-type-from-SPT.patch new file mode 100644 index 0000000..e92dc69 --- /dev/null +++ b/patches.suse/e1000e-Separate-TGP-board-type-from-SPT.patch @@ -0,0 +1,119 @@ +From 280db5d420090a24e4e41f9ddcbf37920a598572 Mon Sep 17 00:00:00 2001 +From: Sasha Neftin +Date: Wed, 22 Sep 2021 09:54:49 +0300 +Subject: [PATCH] e1000e: Separate TGP board type from SPT +Git-commit: 280db5d420090a24e4e41f9ddcbf37920a598572 +Patch-mainline: v5.15-rc7 +References: bsc#1192874 + +[ backport note: drop the non-existing entries for LM20..LM23 -- tiwai ] + +We have the same LAN controller on different PCHs. Separate TGP board +type from SPT which will allow for specific fixes to be applied for +TGP platforms. + +Suggested-by: Kai-Heng Feng +Signed-off-by: Sasha Neftin +Reviewed-by: Paul Menzel +Tested-by: Mark Pearson +Tested-by: Nechama Kraus +Signed-off-by: Tony Nguyen +Acked-by: Takashi Iwai + +--- + drivers/net/ethernet/intel/e1000e/e1000.h | 4 ++- + drivers/net/ethernet/intel/e1000e/ich8lan.c | 20 +++++++++++++++++++ + drivers/net/ethernet/intel/e1000e/netdev.c | 29 ++++++++++++++-------------- + 3 files changed, 38 insertions(+), 15 deletions(-) + +--- a/drivers/net/ethernet/intel/e1000e/e1000.h ++++ b/drivers/net/ethernet/intel/e1000e/e1000.h +@@ -113,7 +113,8 @@ enum e1000_boards { + board_pch2lan, + board_pch_lpt, + board_pch_spt, +- board_pch_cnp ++ board_pch_cnp, ++ board_pch_tgp + }; + + struct e1000_ps_page { +@@ -499,6 +500,7 @@ extern const struct e1000_info e1000_pch + extern const struct e1000_info e1000_pch_lpt_info; + extern const struct e1000_info e1000_pch_spt_info; + extern const struct e1000_info e1000_pch_cnp_info; ++extern const struct e1000_info e1000_pch_tgp_info; + extern const struct e1000_info e1000_es2_info; + + void e1000e_ptp_init(struct e1000_adapter *adapter); +--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c ++++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c +@@ -5995,3 +5995,23 @@ const struct e1000_info e1000_pch_cnp_in + .phy_ops = &ich8_phy_ops, + .nvm_ops = &spt_nvm_ops, + }; ++ ++const struct e1000_info e1000_pch_tgp_info = { ++ .mac = e1000_pch_tgp, ++ .flags = FLAG_IS_ICH ++ | FLAG_HAS_WOL ++ | FLAG_HAS_HW_TIMESTAMP ++ | FLAG_HAS_CTRLEXT_ON_LOAD ++ | FLAG_HAS_AMT ++ | FLAG_HAS_FLASH ++ | FLAG_HAS_JUMBO_FRAMES ++ | FLAG_APME_IN_WUC, ++ .flags2 = FLAG2_HAS_PHY_STATS ++ | FLAG2_HAS_EEE, ++ .pba = 26, ++ .max_hw_frame_size = 9022, ++ .get_variants = e1000_get_variants_ich8lan, ++ .mac_ops = &ich8_mac_ops, ++ .phy_ops = &ich8_phy_ops, ++ .nvm_ops = &spt_nvm_ops, ++}; +--- a/drivers/net/ethernet/intel/e1000e/netdev.c ++++ b/drivers/net/ethernet/intel/e1000e/netdev.c +@@ -54,6 +54,7 @@ static const struct e1000_info *e1000_in + [board_pch_lpt] = &e1000_pch_lpt_info, + [board_pch_spt] = &e1000_pch_spt_info, + [board_pch_cnp] = &e1000_pch_cnp_info, ++ [board_pch_tgp] = &e1000_pch_tgp_info, + }; + + struct e1000_reg_info { +@@ -7842,20 +7843,20 @@ static const struct pci_device_id e1000_ + { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_cnp }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_cnp }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_cnp }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_cnp }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_cnp }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_cnp }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_cnp }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_cnp }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_cnp }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_cnp }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_cnp }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_cnp }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM19), board_pch_cnp }, +- { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V19), board_pch_cnp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_tgp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_tgp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_tgp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_tgp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_tgp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_tgp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM19), board_pch_tgp }, ++ { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V19), board_pch_tgp }, + + { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ + }; diff --git a/patches.suse/edac-sb_edac-fix-top-of-high-memory-value-for-broadwell-haswell.patch b/patches.suse/edac-sb_edac-fix-top-of-high-memory-value-for-broadwell-haswell.patch new file mode 100644 index 0000000..1af228f --- /dev/null +++ b/patches.suse/edac-sb_edac-fix-top-of-high-memory-value-for-broadwell-haswell.patch @@ -0,0 +1,39 @@ +From: Eric Badger +Date: Sun, 10 Oct 2021 10:06:56 -0700 +Subject: EDAC/sb_edac: Fix top-of-high-memory value for Broadwell/Haswell +Git-commit: 537bddd069c743759addf422d0b8f028ff0f8dbc +Patch-mainline: v5.16-rc1 +References: bsc#1152489 + +The computation of TOHM is off by one bit. This missed bit results in +too low a value for TOHM, which can cause errors in regular memory to +incorrectly report: + + EDAC MC0: 1 CE Error at MMIOH area, on addr 0x000000207fffa680 on any memory + +Fixes: 50d1bb93672f ("sb_edac: add support for Haswell based systems") +Cc: stable@vger.kernel.org +Reported-by: Meeta Saggi +Signed-off-by: Eric Badger +Signed-off-by: Tony Luck +Link: https://lore.kernel.org/r/20211010170127.848113-1-ebadger@purestorage.com + +Acked-by: Borislav Petkov +--- + drivers/edac/sb_edac.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c +index 4c626fcd4dcb..1522d4aa2ca6 100644 +--- a/drivers/edac/sb_edac.c ++++ b/drivers/edac/sb_edac.c +@@ -1052,7 +1052,7 @@ static u64 haswell_get_tohm(struct sbridge_pvt *pvt) + pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); + rc = ((reg << 6) | rc) << 26; + +- return rc | 0x1ffffff; ++ return rc | 0x3ffffff; + } + + static u64 knl_get_tolm(struct sbridge_pvt *pvt) + diff --git a/patches.suse/fuse-fix-page-stealing.patch b/patches.suse/fuse-fix-page-stealing.patch new file mode 100644 index 0000000..1633690 --- /dev/null +++ b/patches.suse/fuse-fix-page-stealing.patch @@ -0,0 +1,62 @@ +From: Miklos Szeredi +Date: Tue, 2 Nov 2021 11:10:37 +0100 +Subject: fuse: fix page stealing +Git-commit: 712a951025c0667ff00b25afc360f74e639dfabe +Patch-mainline: v5.16-rc1 +References: bsc#1192718 + +It is possible to trigger a crash by splicing anon pipe bufs to the fuse +device. + +The reason for this is that anon_pipe_buf_release() will reuse buf->page if +the refcount is 1, but that page might have already been stolen and its +flags modified (e.g. PG_lru added). + +This happens in the unlikely case of fuse_dev_splice_write() getting around +to calling pipe_buf_release() after a page has been stolen, added to the +page cache and removed from the page cache. + +Fix by calling pipe_buf_release() right after the page was inserted into +the page cache. In this case the page has an elevated refcount so any +release function will know that the page isn't reusable. + +Reported-by: Frank Dinoff +Link: https://lore.kernel.org/r/CAAmZXrsGg2xsP1CK+cbuEMumtrqdvD-NKnWzhNcvn71RV3c1yw@mail.gmail.com/ +Fixes: dd3bb14f44a6 ("fuse: support splice() writing to fuse device") +Cc: # v2.6.35 +Signed-off-by: Miklos Szeredi +Acked-by: Luis Henriques +--- + fs/fuse/dev.c | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +--- a/fs/fuse/dev.c ++++ b/fs/fuse/dev.c +@@ -840,6 +840,12 @@ static int fuse_try_move_page(struct fus + goto out_put_old; + } + ++ /* ++ * Release while we have extra ref on stolen page. Otherwise ++ * anon_pipe_buf_release() might think the page can be reused. ++ */ ++ pipe_buf_release(cs->pipe, buf); ++ + get_page(newpage); + + if (!(buf->flags & PIPE_BUF_FLAG_LRU)) +@@ -2117,8 +2123,12 @@ static ssize_t fuse_dev_splice_write(str + + pipe_lock(pipe); + out_free: +- for (idx = 0; idx < nbuf; idx++) +- pipe_buf_release(pipe, &bufs[idx]); ++ for (idx = 0; idx < nbuf; idx++) { ++ struct pipe_buffer *buf = &bufs[idx]; ++ ++ if (buf->ops) ++ pipe_buf_release(pipe, buf); ++ } + pipe_unlock(pipe); + + kvfree(bufs); diff --git a/patches.suse/gpio-mpc8xxx-Use-devm_gpiochip_add_data-to-simplify-.patch b/patches.suse/gpio-mpc8xxx-Use-devm_gpiochip_add_data-to-simplify-.patch new file mode 100644 index 0000000..ae246f1 --- /dev/null +++ b/patches.suse/gpio-mpc8xxx-Use-devm_gpiochip_add_data-to-simplify-.patch @@ -0,0 +1,42 @@ +From: Christophe JAILLET +Date: Fri, 20 Aug 2021 17:38:13 +0200 +Subject: gpio: mpc8xxx: Use 'devm_gpiochip_add_data()' to simplify the code + and avoid a leak + +Git-commit: 889a1b3f35db6ba5ba6a0c23a3a55594570b6a17 +Patch-mainline: v5.15-rc1 +References: git-fixes + +If an error occurs after a 'gpiochip_add_data()' call it must be undone by +a corresponding 'gpiochip_remove()' as already done in the remove function. + +To simplify the code a fix a leak in the error handling path of the probe, +use the managed version instead (i.e. 'devm_gpiochip_add_data()') + +Fixes: 698b8eeaed72 ("gpio/mpc8xxx: change irq handler from chained to normal") +Signed-off-by: Christophe JAILLET +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/gpio/gpio-mpc8xxx.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/gpio/gpio-mpc8xxx.c ++++ b/drivers/gpio/gpio-mpc8xxx.c +@@ -374,7 +374,7 @@ static int mpc8xxx_probe(struct platform + of_device_is_compatible(np, "fsl,ls1088a-gpio")) + gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); + +- ret = gpiochip_add_data(gc, mpc8xxx_gc); ++ ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc); + if (ret) { + pr_err("%pOF: GPIO chip registration failed with status %d\n", + np, ret); +@@ -442,7 +442,6 @@ static int mpc8xxx_remove(struct platfor + irq_domain_remove(mpc8xxx_gc->irq); + } + +- gpiochip_remove(&mpc8xxx_gc->gc); + iounmap(mpc8xxx_gc->regs); + + return 0; diff --git a/patches.suse/gpio-rockchip-add-driver-for-rockchip-gpio.patch b/patches.suse/gpio-rockchip-add-driver-for-rockchip-gpio.patch new file mode 100644 index 0000000..2b725d1 --- /dev/null +++ b/patches.suse/gpio-rockchip-add-driver-for-rockchip-gpio.patch @@ -0,0 +1,681 @@ +From: Jianqun Xu +Date: Mon, 16 Aug 2021 09:20:53 +0800 +Subject: gpio/rockchip: add driver for rockchip gpio + +Git-commit: 936ee2675eee1faca0dcdfa79165c7990422e0fc +Patch-mainline: v5.15-rc1 +References: bsc#1192217 + +This patch add support for rockchip gpio controller, which is supported +in pinctrl driver in the past. + +With this patch, the pinctrl-rockchip driver will drop gpio related +codes and populate platform driver to gpio-rockchip. + +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20210816012053.1119069-1-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-rockchip.c | 626 +++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 635 insertions(+) + create mode 100644 drivers/gpio/gpio-rockchip.c + +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -441,6 +441,14 @@ config GPIO_REG + A 32-bit single register GPIO fixed in/out implementation. This + can be used to represent any register as a set of GPIO signals. + ++config GPIO_ROCKCHIP ++ tristate "Rockchip GPIO support" ++ depends on ARCH_ROCKCHIP || COMPILE_TEST ++ select GPIOLIB_IRQCHIP ++ default ARCH_ROCKCHIP ++ help ++ Say yes here to support GPIO on Rockchip SoCs. ++ + config GPIO_SAMA5D2_PIOBU + tristate "SAMA5D2 PIOBU GPIO support" + depends on MFD_SYSCON +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -117,6 +117,7 @@ obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t + obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o + obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o + obj-$(CONFIG_GPIO_REG) += gpio-reg.o ++obj-$(CONFIG_GPIO_ROCKCHIP) += gpio-rockchip.o + obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o + obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o + obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o +--- /dev/null ++++ b/drivers/gpio/gpio-rockchip.c +@@ -0,0 +1,626 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2013 MundoReader S.L. ++ * Author: Heiko Stuebner ++ * ++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../pinctrl/core.h" ++#include "../pinctrl/pinctrl-rockchip.h" ++ ++/* GPIO control registers */ ++#define GPIO_SWPORT_DR 0x00 ++#define GPIO_SWPORT_DDR 0x04 ++#define GPIO_INTEN 0x30 ++#define GPIO_INTMASK 0x34 ++#define GPIO_INTTYPE_LEVEL 0x38 ++#define GPIO_INT_POLARITY 0x3c ++#define GPIO_INT_STATUS 0x40 ++#define GPIO_INT_RAWSTATUS 0x44 ++#define GPIO_DEBOUNCE 0x48 ++#define GPIO_PORTS_EOI 0x4c ++#define GPIO_EXT_PORT 0x50 ++#define GPIO_LS_SYNC 0x60 ++ ++static int rockchip_gpio_get_direction(struct gpio_chip *chip, ++ unsigned int offset) ++{ ++ struct rockchip_pin_bank *bank = gpiochip_get_data(chip); ++ u32 data; ++ ++ data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); ++ if (data & BIT(offset)) ++ return GPIO_LINE_DIRECTION_OUT; ++ ++ return GPIO_LINE_DIRECTION_IN; ++} ++ ++static int rockchip_gpio_set_direction(struct gpio_chip *chip, ++ unsigned int offset, bool input) ++{ ++ struct rockchip_pin_bank *bank = gpiochip_get_data(chip); ++ unsigned long flags; ++ u32 data; ++ ++ raw_spin_lock_irqsave(&bank->slock, flags); ++ ++ data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); ++ /* set bit to 1 for output, 0 for input */ ++ if (!input) ++ data |= BIT(offset); ++ else ++ data &= ~BIT(offset); ++ writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); ++ ++ raw_spin_unlock_irqrestore(&bank->slock, flags); ++ ++ return 0; ++} ++ ++static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, ++ int value) ++{ ++ struct rockchip_pin_bank *bank = gpiochip_get_data(gc); ++ void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; ++ unsigned long flags; ++ u32 data; ++ ++ raw_spin_lock_irqsave(&bank->slock, flags); ++ ++ data = readl(reg); ++ data &= ~BIT(offset); ++ if (value) ++ data |= BIT(offset); ++ writel(data, reg); ++ ++ raw_spin_unlock_irqrestore(&bank->slock, flags); ++} ++ ++static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset) ++{ ++ struct rockchip_pin_bank *bank = gpiochip_get_data(gc); ++ u32 data; ++ ++ data = readl(bank->reg_base + GPIO_EXT_PORT); ++ data >>= offset; ++ data &= 1; ++ return data; ++} ++ ++static void rockchip_gpio_set_debounce(struct gpio_chip *gc, ++ unsigned int offset, bool enable) ++{ ++ struct rockchip_pin_bank *bank = gpiochip_get_data(gc); ++ void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; ++ unsigned long flags; ++ u32 data; ++ ++ raw_spin_lock_irqsave(&bank->slock, flags); ++ ++ data = readl(reg); ++ if (enable) ++ data |= BIT(offset); ++ else ++ data &= ~BIT(offset); ++ writel(data, reg); ++ ++ raw_spin_unlock_irqrestore(&bank->slock, flags); ++} ++ ++static int rockchip_gpio_direction_input(struct gpio_chip *gc, ++ unsigned int offset) ++{ ++ return rockchip_gpio_set_direction(gc, offset, true); ++} ++ ++static int rockchip_gpio_direction_output(struct gpio_chip *gc, ++ unsigned int offset, int value) ++{ ++ rockchip_gpio_set(gc, offset, value); ++ ++ return rockchip_gpio_set_direction(gc, offset, false); ++} ++ ++/* ++ * gpiolib set_config callback function. The setting of the pin ++ * mux function as 'gpio output' will be handled by the pinctrl subsystem ++ * interface. ++ */ ++static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, ++ unsigned long config) ++{ ++ enum pin_config_param param = pinconf_to_config_param(config); ++ ++ switch (param) { ++ case PIN_CONFIG_INPUT_DEBOUNCE: ++ rockchip_gpio_set_debounce(gc, offset, true); ++ /* ++ * Rockchip's gpio could only support up to one period ++ * of the debounce clock(pclk), which is far away from ++ * satisftying the requirement, as pclk is usually near ++ * 100MHz shared by all peripherals. So the fact is it ++ * has crippled debounce capability could only be useful ++ * to prevent any spurious glitches from waking up the system ++ * if the gpio is conguired as wakeup interrupt source. Let's ++ * still return -ENOTSUPP as before, to make sure the caller ++ * of gpiod_set_debounce won't change its behaviour. ++ */ ++ return -ENOTSUPP; ++ default: ++ return -ENOTSUPP; ++ } ++} ++ ++/* ++ * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin ++ * and a virtual IRQ, if not already present. ++ */ ++static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) ++{ ++ struct rockchip_pin_bank *bank = gpiochip_get_data(gc); ++ unsigned int virq; ++ ++ if (!bank->domain) ++ return -ENXIO; ++ ++ virq = irq_create_mapping(bank->domain, offset); ++ ++ return (virq) ? : -ENXIO; ++} ++ ++static const struct gpio_chip rockchip_gpiolib_chip = { ++ .request = gpiochip_generic_request, ++ .free = gpiochip_generic_free, ++ .set = rockchip_gpio_set, ++ .get = rockchip_gpio_get, ++ .get_direction = rockchip_gpio_get_direction, ++ .direction_input = rockchip_gpio_direction_input, ++ .direction_output = rockchip_gpio_direction_output, ++ .set_config = rockchip_gpio_set_config, ++ .to_irq = rockchip_gpio_to_irq, ++ .owner = THIS_MODULE, ++}; ++ ++static void rockchip_irq_demux(struct irq_desc *desc) ++{ ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); ++ u32 pend; ++ ++ dev_dbg(bank->dev, "got irq for bank %s\n", bank->name); ++ ++ chained_irq_enter(chip, desc); ++ ++ pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); ++ ++ while (pend) { ++ unsigned int irq, virq; ++ ++ irq = __ffs(pend); ++ pend &= ~BIT(irq); ++ virq = irq_find_mapping(bank->domain, irq); ++ ++ if (!virq) { ++ dev_err(bank->dev, "unmapped irq %d\n", irq); ++ continue; ++ } ++ ++ dev_dbg(bank->dev, "handling irq %d\n", irq); ++ ++ /* ++ * Triggering IRQ on both rising and falling edge ++ * needs manual intervention. ++ */ ++ if (bank->toggle_edge_mode & BIT(irq)) { ++ u32 data, data_old, polarity; ++ unsigned long flags; ++ ++ data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); ++ do { ++ raw_spin_lock_irqsave(&bank->slock, flags); ++ ++ polarity = readl_relaxed(bank->reg_base + ++ GPIO_INT_POLARITY); ++ if (data & BIT(irq)) ++ polarity &= ~BIT(irq); ++ else ++ polarity |= BIT(irq); ++ writel(polarity, ++ bank->reg_base + GPIO_INT_POLARITY); ++ ++ raw_spin_unlock_irqrestore(&bank->slock, flags); ++ ++ data_old = data; ++ data = readl_relaxed(bank->reg_base + ++ GPIO_EXT_PORT); ++ } while ((data & BIT(irq)) != (data_old & BIT(irq))); ++ } ++ ++ generic_handle_irq(virq); ++ } ++ ++ chained_irq_exit(chip, desc); ++} ++ ++static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); ++ struct rockchip_pin_bank *bank = gc->private; ++ u32 mask = BIT(d->hwirq); ++ u32 polarity; ++ u32 level; ++ u32 data; ++ unsigned long flags; ++ ++ raw_spin_lock_irqsave(&bank->slock, flags); ++ ++ data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); ++ data &= ~mask; ++ writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); ++ ++ raw_spin_unlock_irqrestore(&bank->slock, flags); ++ ++ if (type & IRQ_TYPE_EDGE_BOTH) ++ irq_set_handler_locked(d, handle_edge_irq); ++ else ++ irq_set_handler_locked(d, handle_level_irq); ++ ++ raw_spin_lock_irqsave(&bank->slock, flags); ++ irq_gc_lock(gc); ++ ++ level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); ++ polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); ++ ++ switch (type) { ++ case IRQ_TYPE_EDGE_BOTH: ++ bank->toggle_edge_mode |= mask; ++ level |= mask; ++ ++ /* ++ * Determine gpio state. If 1 next interrupt should be falling ++ * otherwise rising. ++ */ ++ data = readl(bank->reg_base + GPIO_EXT_PORT); ++ if (data & mask) ++ polarity &= ~mask; ++ else ++ polarity |= mask; ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ bank->toggle_edge_mode &= ~mask; ++ level |= mask; ++ polarity |= mask; ++ break; ++ case IRQ_TYPE_EDGE_FALLING: ++ bank->toggle_edge_mode &= ~mask; ++ level |= mask; ++ polarity &= ~mask; ++ break; ++ case IRQ_TYPE_LEVEL_HIGH: ++ bank->toggle_edge_mode &= ~mask; ++ level &= ~mask; ++ polarity |= mask; ++ break; ++ case IRQ_TYPE_LEVEL_LOW: ++ bank->toggle_edge_mode &= ~mask; ++ level &= ~mask; ++ polarity &= ~mask; ++ break; ++ default: ++ irq_gc_unlock(gc); ++ raw_spin_unlock_irqrestore(&bank->slock, flags); ++ clk_disable(bank->clk); ++ return -EINVAL; ++ } ++ ++ writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); ++ writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); ++ ++ irq_gc_unlock(gc); ++ raw_spin_unlock_irqrestore(&bank->slock, flags); ++ ++ return 0; ++} ++ ++static void rockchip_irq_suspend(struct irq_data *d) ++{ ++ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); ++ struct rockchip_pin_bank *bank = gc->private; ++ ++ bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); ++ irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); ++} ++ ++static void rockchip_irq_resume(struct irq_data *d) ++{ ++ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); ++ struct rockchip_pin_bank *bank = gc->private; ++ ++ irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); ++} ++ ++static void rockchip_irq_enable(struct irq_data *d) ++{ ++ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); ++ struct rockchip_pin_bank *bank = gc->private; ++ ++ irq_gc_mask_clr_bit(d); ++} ++ ++static void rockchip_irq_disable(struct irq_data *d) ++{ ++ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); ++ struct rockchip_pin_bank *bank = gc->private; ++ ++ irq_gc_mask_set_bit(d); ++ clk_disable(bank->clk); ++} ++ ++static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) ++{ ++ unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; ++ struct irq_chip_generic *gc; ++ int ret; ++ ++ bank->domain = irq_domain_add_linear(bank->of_node, 32, ++ &irq_generic_chip_ops, NULL); ++ if (!bank->domain) { ++ dev_warn(bank->dev, "could not init irq domain for bank %s\n", ++ bank->name); ++ return -EINVAL; ++ } ++ ++ ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, ++ "rockchip_gpio_irq", ++ handle_level_irq, ++ clr, 0, 0); ++ if (ret) { ++ dev_err(bank->dev, "could not alloc generic chips for bank %s\n", ++ bank->name); ++ irq_domain_remove(bank->domain); ++ return -EINVAL; ++ } ++ ++ gc = irq_get_domain_generic_chip(bank->domain, 0); ++ gc->reg_base = bank->reg_base; ++ gc->private = bank; ++ gc->chip_types[0].regs.mask = GPIO_INTMASK; ++ gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; ++ gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; ++ gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; ++ gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; ++ gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; ++ gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; ++ gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; ++ gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; ++ gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; ++ gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; ++ gc->wake_enabled = IRQ_MSK(bank->nr_pins); ++ ++ /* ++ * Linux assumes that all interrupts start out disabled/masked. ++ * Our driver only uses the concept of masked and always keeps ++ * things enabled, so for us that's all masked and all enabled. ++ */ ++ writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); ++ writel_relaxed(0xffffffff, bank->reg_base + GPIO_PORTS_EOI); ++ writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); ++ gc->mask_cache = 0xffffffff; ++ ++ irq_set_chained_handler_and_data(bank->irq, ++ rockchip_irq_demux, bank); ++ ++ return 0; ++} ++ ++static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank) ++{ ++ struct gpio_chip *gc; ++ int ret; ++ ++ bank->gpio_chip = rockchip_gpiolib_chip; ++ ++ gc = &bank->gpio_chip; ++ gc->base = bank->pin_base; ++ gc->ngpio = bank->nr_pins; ++ gc->label = bank->name; ++ gc->parent = bank->dev; ++#ifdef CONFIG_OF_GPIO ++ gc->of_node = of_node_get(bank->of_node); ++#endif ++ ++ ret = gpiochip_add_data(gc, bank); ++ if (ret) { ++ dev_err(bank->dev, "failed to add gpiochip %s, %d\n", ++ gc->label, ret); ++ return ret; ++ } ++ ++ /* ++ * For DeviceTree-supported systems, the gpio core checks the ++ * pinctrl's device node for the "gpio-ranges" property. ++ * If it is present, it takes care of adding the pin ranges ++ * for the driver. In this case the driver can skip ahead. ++ * ++ * In order to remain compatible with older, existing DeviceTree ++ * files which don't set the "gpio-ranges" property or systems that ++ * utilize ACPI the driver has to call gpiochip_add_pin_range(). ++ */ ++ if (!of_property_read_bool(bank->of_node, "gpio-ranges")) { ++ struct device_node *pctlnp = of_get_parent(bank->of_node); ++ struct pinctrl_dev *pctldev = NULL; ++ ++ if (!pctlnp) ++ return -ENODATA; ++ ++ pctldev = of_pinctrl_get(pctlnp); ++ if (!pctldev) ++ return -ENODEV; ++ ++ ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0, ++ gc->base, gc->ngpio); ++ if (ret) { ++ dev_err(bank->dev, "Failed to add pin range\n"); ++ goto fail; ++ } ++ } ++ ++ ret = rockchip_interrupts_register(bank); ++ if (ret) { ++ dev_err(bank->dev, "failed to register interrupt, %d\n", ret); ++ goto fail; ++ } ++ ++ return 0; ++ ++fail: ++ gpiochip_remove(&bank->gpio_chip); ++ ++ return ret; ++} ++ ++static int rockchip_get_bank_data(struct rockchip_pin_bank *bank) ++{ ++ struct resource res; ++ ++ if (of_address_to_resource(bank->of_node, 0, &res)) { ++ dev_err(bank->dev, "cannot find IO resource for bank\n"); ++ return -ENOENT; ++ } ++ ++ bank->reg_base = devm_ioremap_resource(bank->dev, &res); ++ if (IS_ERR(bank->reg_base)) ++ return PTR_ERR(bank->reg_base); ++ ++ bank->irq = irq_of_parse_and_map(bank->of_node, 0); ++ ++ bank->clk = of_clk_get(bank->of_node, 0); ++ if (!IS_ERR(bank->clk)) ++ return clk_prepare_enable(bank->clk); ++ ++ bank->clk = NULL; ++ return 0; ++} ++ ++static struct rockchip_pin_bank * ++rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id) ++{ ++ struct rockchip_pinctrl *info; ++ struct rockchip_pin_bank *bank; ++ int i, found = 0; ++ ++ info = pinctrl_dev_get_drvdata(pctldev); ++ bank = info->ctrl->pin_banks; ++ for (i = 0; i < info->ctrl->nr_banks; i++, bank++) { ++ if (bank->bank_num == id) { ++ found = 1; ++ break; ++ } ++ } ++ ++ return found ? bank : NULL; ++} ++ ++static int rockchip_gpio_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ struct device_node *pctlnp = of_get_parent(np); ++ struct pinctrl_dev *pctldev = NULL; ++ struct rockchip_pin_bank *bank = NULL; ++ static int gpio; ++ int id, ret; ++ ++ if (!np || !pctlnp) ++ return -ENODEV; ++ ++ pctldev = of_pinctrl_get(pctlnp); ++ if (!pctldev) ++ return -EPROBE_DEFER; ++ ++ id = of_alias_get_id(np, "gpio"); ++ if (id < 0) ++ id = gpio++; ++ ++ bank = rockchip_gpio_find_bank(pctldev, id); ++ if (!bank) ++ return -EINVAL; ++ ++ bank->dev = dev; ++ bank->of_node = np; ++ ++ raw_spin_lock_init(&bank->slock); ++ ++ ret = rockchip_get_bank_data(bank); ++ if (ret) ++ return ret; ++ ++ ret = rockchip_gpiolib_register(bank); ++ if (ret) { ++ clk_disable_unprepare(bank->clk); ++ return ret; ++ } ++ ++ platform_set_drvdata(pdev, bank); ++ dev_info(dev, "probed %pOF\n", np); ++ ++ return 0; ++} ++ ++static int rockchip_gpio_remove(struct platform_device *pdev) ++{ ++ struct rockchip_pin_bank *bank = platform_get_drvdata(pdev); ++ ++ clk_disable_unprepare(bank->clk); ++ gpiochip_remove(&bank->gpio_chip); ++ ++ return 0; ++} ++ ++static const struct of_device_id rockchip_gpio_match[] = { ++ { .compatible = "rockchip,gpio-bank", }, ++ { .compatible = "rockchip,rk3188-gpio-bank0" }, ++ { }, ++}; ++ ++static struct platform_driver rockchip_gpio_driver = { ++ .probe = rockchip_gpio_probe, ++ .remove = rockchip_gpio_remove, ++ .driver = { ++ .name = "rockchip-gpio", ++ .of_match_table = rockchip_gpio_match, ++ }, ++}; ++ ++static int __init rockchip_gpio_init(void) ++{ ++ return platform_driver_register(&rockchip_gpio_driver); ++} ++postcore_initcall(rockchip_gpio_init); ++ ++static void __exit rockchip_gpio_exit(void) ++{ ++ platform_driver_unregister(&rockchip_gpio_driver); ++} ++module_exit(rockchip_gpio_exit); ++ ++MODULE_DESCRIPTION("Rockchip gpio driver"); ++MODULE_ALIAS("platform:rockchip-gpio"); ++MODULE_LICENSE("GPL v2"); ++MODULE_DEVICE_TABLE(of, rockchip_gpio_match); diff --git a/patches.suse/gpio-rockchip-drop-irq_gc_lock-irq_gc_unlock-for-irq.patch b/patches.suse/gpio-rockchip-drop-irq_gc_lock-irq_gc_unlock-for-irq.patch new file mode 100644 index 0000000..bb12ea8 --- /dev/null +++ b/patches.suse/gpio-rockchip-drop-irq_gc_lock-irq_gc_unlock-for-irq.patch @@ -0,0 +1,43 @@ +From: Jianqun Xu +Date: Mon, 16 Aug 2021 09:21:35 +0800 +Subject: gpio/rockchip: drop irq_gc_lock/irq_gc_unlock for irq set type + +Git-commit: 93103f6eb09ca5152ef9173ec8b91b78df1905e8 +Patch-mainline: v5.15-rc1 +References: bsc#1192217 + +There has spin lock for irq set type already, so drop irq_gc_lock and +irq_gc_unlock. + +Reviewed-by: Heiko Stuebner +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20210816012135.1119234-1-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/gpio/gpio-rockchip.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c +index b2be56040289..036b2d959503 100644 +--- a/drivers/gpio/gpio-rockchip.c ++++ b/drivers/gpio/gpio-rockchip.c +@@ -406,7 +406,6 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) + irq_set_handler_locked(d, handle_level_irq); + + raw_spin_lock_irqsave(&bank->slock, flags); +- irq_gc_lock(gc); + + level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type); + polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity); +@@ -461,7 +460,6 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) + rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type); + rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity); + out: +- irq_gc_unlock(gc); + raw_spin_unlock_irqrestore(&bank->slock, flags); + + return ret; +-- +2.31.1 + diff --git a/patches.suse/gpio-rockchip-extended-debounce-support-is-only-avai.patch b/patches.suse/gpio-rockchip-extended-debounce-support-is-only-avai.patch new file mode 100644 index 0000000..cb53f35 --- /dev/null +++ b/patches.suse/gpio-rockchip-extended-debounce-support-is-only-avai.patch @@ -0,0 +1,44 @@ +From: Heiko Stuebner +Date: Tue, 14 Sep 2021 00:49:23 +0200 +Subject: gpio/rockchip: extended debounce support is only available on v2 + +Git-commit: 0f562b7de99085935d76b00c41ab5caa26ff5c74 +Patch-mainline: v5.15-rc3 +References: bsc#1192217 + +The gpio driver runs into issues on v1 gpio blocks, as the db_clk +and the whole extended debounce support is only ever defined on v2. +So checking for the IS_ERR on the db_clk is not enough, as it will +be NULL on v1. + +Fix this by adding the needed condition for v2 first before checking +the existence of the db_clk. + +This caused my rk3288-veyron-pinky to enter a reboot loop when it +tried to enable the power-key as adc-key device. + +Fixes: 3bcbd1a85b68 ("gpio/rockchip: support next version gpio controller") +Signed-off-by: Heiko Stuebner +Reviewed-by: Linus Walleij +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/gpio/gpio-rockchip.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c +index 036b2d959503..16d9bf7188e3 100644 +--- a/drivers/gpio/gpio-rockchip.c ++++ b/drivers/gpio/gpio-rockchip.c +@@ -195,7 +195,7 @@ static int rockchip_gpio_set_debounce(struct gpio_chip *gc, + unsigned int cur_div_reg; + u64 div; + +- if (!IS_ERR(bank->db_clk)) { ++ if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) { + div_debounce_support = true; + freq = clk_get_rate(bank->db_clk); + max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq; +-- +2.31.1 + diff --git a/patches.suse/gpio-rockchip-fetch-deferred-output-settings-on-prob.patch b/patches.suse/gpio-rockchip-fetch-deferred-output-settings-on-prob.patch new file mode 100644 index 0000000..683ac91 --- /dev/null +++ b/patches.suse/gpio-rockchip-fetch-deferred-output-settings-on-prob.patch @@ -0,0 +1,69 @@ +From: Heiko Stuebner +Date: Tue, 14 Sep 2021 00:49:26 +0200 +Subject: gpio/rockchip: fetch deferred output settings on probe + +Git-commit: 59dd178e1d7cb6cac03b32aba7ed9bbce6761b6f +Patch-mainline: v5.15-rc4 +References: bsc#1192217 + +Fetch the output settings the pinctrl driver may have created +for pinctrl hogs and set the relevant pins as requested. + +Fixes: 9ce9a02039de ("pinctrl/rockchip: drop the gpio related codes") +Signed-off-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20210913224926.1260726-5-heiko@sntech.de +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/gpio/gpio-rockchip.c | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c +index 036b2d959503..d67c64a39e47 100644 +--- a/drivers/gpio/gpio-rockchip.c ++++ b/drivers/gpio/gpio-rockchip.c +@@ -689,6 +689,7 @@ static int rockchip_gpio_probe(struct platform_device *pdev) + struct device_node *pctlnp = of_get_parent(np); + struct pinctrl_dev *pctldev = NULL; + struct rockchip_pin_bank *bank = NULL; ++ struct rockchip_pin_output_deferred *cfg; + static int gpio; + int id, ret; + +@@ -716,12 +717,33 @@ static int rockchip_gpio_probe(struct platform_device *pdev) + if (ret) + return ret; + ++ /* ++ * Prevent clashes with a deferred output setting ++ * being added right at this moment. ++ */ ++ mutex_lock(&bank->deferred_lock); ++ + ret = rockchip_gpiolib_register(bank); + if (ret) { + clk_disable_unprepare(bank->clk); ++ mutex_unlock(&bank->deferred_lock); + return ret; + } + ++ while (!list_empty(&bank->deferred_output)) { ++ cfg = list_first_entry(&bank->deferred_output, ++ struct rockchip_pin_output_deferred, head); ++ list_del(&cfg->head); ++ ++ ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg); ++ if (ret) ++ dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin, cfg->arg); ++ ++ kfree(cfg); ++ } ++ ++ mutex_unlock(&bank->deferred_lock); ++ + platform_set_drvdata(pdev, bank); + dev_info(dev, "probed %pOF\n", np); + +-- +2.31.1 + diff --git a/patches.suse/gpio-rockchip-fix-get_direction-value-handling.patch b/patches.suse/gpio-rockchip-fix-get_direction-value-handling.patch new file mode 100644 index 0000000..1ebf72c --- /dev/null +++ b/patches.suse/gpio-rockchip-fix-get_direction-value-handling.patch @@ -0,0 +1,40 @@ +From: Heiko Stuebner +Date: Tue, 14 Sep 2021 00:49:24 +0200 +Subject: gpio/rockchip: fix get_direction value handling + +Git-commit: b22a4705e2e60f342b1b851c9ebdb3ea02f21f8f +Patch-mainline: v5.15-rc3 +References: bsc#1192217 + +The function uses the newly introduced rockchip_gpio_readl_bit() +which directly returns the actual value of the requeste bit. +So using the existing bit-wise check for the bit inside the value +will always return 0. + +Fix this by dropping the bit manipulation on the result. + +Fixes: 3bcbd1a85b68 ("gpio/rockchip: support next version gpio controller") +Signed-off-by: Heiko Stuebner +Reviewed-by: Linus Walleij +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/gpio/gpio-rockchip.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c +index 16d9bf7188e3..3335bd57761d 100644 +--- a/drivers/gpio/gpio-rockchip.c ++++ b/drivers/gpio/gpio-rockchip.c +@@ -141,7 +141,7 @@ static int rockchip_gpio_get_direction(struct gpio_chip *chip, + u32 data; + + data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr); +- if (data & BIT(offset)) ++ if (data) + return GPIO_LINE_DIRECTION_OUT; + + return GPIO_LINE_DIRECTION_IN; +-- +2.31.1 + diff --git a/patches.suse/gpio-rockchip-support-next-version-gpio-controller.patch b/patches.suse/gpio-rockchip-support-next-version-gpio-controller.patch new file mode 100644 index 0000000..43d9cf5 --- /dev/null +++ b/patches.suse/gpio-rockchip-support-next-version-gpio-controller.patch @@ -0,0 +1,459 @@ +From: Jianqun Xu +Date: Mon, 16 Aug 2021 09:21:23 +0800 +Subject: gpio/rockchip: support next version gpio controller + +Git-commit: 3bcbd1a85b68e5f864029fd6f0bb0bcc8e2f1082 +Patch-mainline: v5.15-rc1 +References: bsc#1192217 + +The next version gpio controller on SoCs like rk3568 have more write +mask bits for registers. + +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20210816012123.1119179-1-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/gpio/gpio-rockchip.c | 283 +++++++++++++++++++++-------- + drivers/pinctrl/pinctrl-rockchip.h | 2 + + 2 files changed, 213 insertions(+), 72 deletions(-) + +diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c +index d6c07a957bd8..b2be56040289 100644 +--- a/drivers/gpio/gpio-rockchip.c ++++ b/drivers/gpio/gpio-rockchip.c +@@ -25,6 +25,7 @@ + #include "../pinctrl/pinctrl-rockchip.h" + + #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */ ++#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */ + + static const struct rockchip_gpio_regs gpio_regs_v1 = { + .port_dr = 0x00, +@@ -40,13 +41,106 @@ static const struct rockchip_gpio_regs gpio_regs_v1 = { + .ext_port = 0x50, + }; + ++static const struct rockchip_gpio_regs gpio_regs_v2 = { ++ .port_dr = 0x00, ++ .port_ddr = 0x08, ++ .int_en = 0x10, ++ .int_mask = 0x18, ++ .int_type = 0x20, ++ .int_polarity = 0x28, ++ .int_bothedge = 0x30, ++ .int_status = 0x50, ++ .int_rawstatus = 0x58, ++ .debounce = 0x38, ++ .dbclk_div_en = 0x40, ++ .dbclk_div_con = 0x48, ++ .port_eoi = 0x60, ++ .ext_port = 0x70, ++ .version_id = 0x78, ++}; ++ ++static inline void gpio_writel_v2(u32 val, void __iomem *reg) ++{ ++ writel((val & 0xffff) | 0xffff0000, reg); ++ writel((val >> 16) | 0xffff0000, reg + 0x4); ++} ++ ++static inline u32 gpio_readl_v2(void __iomem *reg) ++{ ++ return readl(reg + 0x4) << 16 | readl(reg); ++} ++ ++static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, ++ u32 value, unsigned int offset) ++{ ++ void __iomem *reg = bank->reg_base + offset; ++ ++ if (bank->gpio_type == GPIO_TYPE_V2) ++ gpio_writel_v2(value, reg); ++ else ++ writel(value, reg); ++} ++ ++static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, ++ unsigned int offset) ++{ ++ void __iomem *reg = bank->reg_base + offset; ++ u32 value; ++ ++ if (bank->gpio_type == GPIO_TYPE_V2) ++ value = gpio_readl_v2(reg); ++ else ++ value = readl(reg); ++ ++ return value; ++} ++ ++static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, ++ u32 bit, u32 value, ++ unsigned int offset) ++{ ++ void __iomem *reg = bank->reg_base + offset; ++ u32 data; ++ ++ if (bank->gpio_type == GPIO_TYPE_V2) { ++ if (value) ++ data = BIT(bit % 16) | BIT(bit % 16 + 16); ++ else ++ data = BIT(bit % 16 + 16); ++ writel(data, bit >= 16 ? reg + 0x4 : reg); ++ } else { ++ data = readl(reg); ++ data &= ~BIT(bit); ++ if (value) ++ data |= BIT(bit); ++ writel(data, reg); ++ } ++} ++ ++static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, ++ u32 bit, unsigned int offset) ++{ ++ void __iomem *reg = bank->reg_base + offset; ++ u32 data; ++ ++ if (bank->gpio_type == GPIO_TYPE_V2) { ++ data = readl(bit >= 16 ? reg + 0x4 : reg); ++ data >>= bit % 16; ++ } else { ++ data = readl(reg); ++ data >>= bit; ++ } ++ ++ return data & (0x1); ++} ++ + static int rockchip_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) + { + struct rockchip_pin_bank *bank = gpiochip_get_data(chip); + u32 data; + +- data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr); ++ data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr); + if (data & BIT(offset)) + return GPIO_LINE_DIRECTION_OUT; + +@@ -58,18 +152,10 @@ static int rockchip_gpio_set_direction(struct gpio_chip *chip, + { + struct rockchip_pin_bank *bank = gpiochip_get_data(chip); + unsigned long flags; +- u32 data; ++ u32 data = input ? 0 : 1; + + raw_spin_lock_irqsave(&bank->slock, flags); +- +- data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr); +- /* set bit to 1 for output, 0 for input */ +- if (!input) +- data |= BIT(offset); +- else +- data &= ~BIT(offset); +- writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr); +- ++ rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr); + raw_spin_unlock_irqrestore(&bank->slock, flags); + + return 0; +@@ -79,18 +165,10 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, + int value) + { + struct rockchip_pin_bank *bank = gpiochip_get_data(gc); +- void __iomem *reg = bank->reg_base + bank->gpio_regs->port_dr; + unsigned long flags; +- u32 data; + + raw_spin_lock_irqsave(&bank->slock, flags); +- +- data = readl(reg); +- data &= ~BIT(offset); +- if (value) +- data |= BIT(offset); +- writel(data, reg); +- ++ rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr); + raw_spin_unlock_irqrestore(&bank->slock, flags); + } + +@@ -106,24 +184,65 @@ static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset) + return data; + } + +-static void rockchip_gpio_set_debounce(struct gpio_chip *gc, +- unsigned int offset, bool enable) ++static int rockchip_gpio_set_debounce(struct gpio_chip *gc, ++ unsigned int offset, ++ unsigned int debounce) + { + struct rockchip_pin_bank *bank = gpiochip_get_data(gc); +- void __iomem *reg = bank->reg_base + bank->gpio_regs->debounce; +- unsigned long flags; +- u32 data; ++ const struct rockchip_gpio_regs *reg = bank->gpio_regs; ++ unsigned long flags, div_reg, freq, max_debounce; ++ bool div_debounce_support; ++ unsigned int cur_div_reg; ++ u64 div; ++ ++ if (!IS_ERR(bank->db_clk)) { ++ div_debounce_support = true; ++ freq = clk_get_rate(bank->db_clk); ++ max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq; ++ if (debounce > max_debounce) ++ return -EINVAL; ++ ++ div = debounce * freq; ++ div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1; ++ } else { ++ div_debounce_support = false; ++ } + + raw_spin_lock_irqsave(&bank->slock, flags); + +- data = readl(reg); +- if (enable) +- data |= BIT(offset); +- else +- data &= ~BIT(offset); +- writel(data, reg); ++ /* Only the v1 needs to configure div_en and div_con for dbclk */ ++ if (debounce) { ++ if (div_debounce_support) { ++ /* Configure the max debounce from consumers */ ++ cur_div_reg = readl(bank->reg_base + ++ reg->dbclk_div_con); ++ if (cur_div_reg < div_reg) ++ writel(div_reg, bank->reg_base + ++ reg->dbclk_div_con); ++ rockchip_gpio_writel_bit(bank, offset, 1, ++ reg->dbclk_div_en); ++ } ++ ++ rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce); ++ } else { ++ if (div_debounce_support) ++ rockchip_gpio_writel_bit(bank, offset, 0, ++ reg->dbclk_div_en); ++ ++ rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce); ++ } + + raw_spin_unlock_irqrestore(&bank->slock, flags); ++ ++ /* Enable or disable dbclk at last */ ++ if (div_debounce_support) { ++ if (debounce) ++ clk_prepare_enable(bank->db_clk); ++ else ++ clk_disable_unprepare(bank->db_clk); ++ } ++ ++ return 0; + } + + static int rockchip_gpio_direction_input(struct gpio_chip *gc, +@@ -272,12 +391,12 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) + u32 level; + u32 data; + unsigned long flags; ++ int ret = 0; + + raw_spin_lock_irqsave(&bank->slock, flags); + +- data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr); +- data &= ~mask; +- writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr); ++ rockchip_gpio_writel_bit(bank, d->hwirq, 0, ++ bank->gpio_regs->port_ddr); + + raw_spin_unlock_irqrestore(&bank->slock, flags); + +@@ -289,23 +408,30 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) + raw_spin_lock_irqsave(&bank->slock, flags); + irq_gc_lock(gc); + +- level = readl_relaxed(gc->reg_base + bank->gpio_regs->int_type); +- polarity = readl_relaxed(gc->reg_base + bank->gpio_regs->int_polarity); ++ level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type); ++ polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity); + + switch (type) { + case IRQ_TYPE_EDGE_BOTH: +- bank->toggle_edge_mode |= mask; +- level |= mask; +- +- /* +- * Determine gpio state. If 1 next interrupt should be falling +- * otherwise rising. +- */ +- data = readl(bank->reg_base + bank->gpio_regs->ext_port); +- if (data & mask) +- polarity &= ~mask; +- else +- polarity |= mask; ++ if (bank->gpio_type == GPIO_TYPE_V2) { ++ bank->toggle_edge_mode &= ~mask; ++ rockchip_gpio_writel_bit(bank, d->hwirq, 1, ++ bank->gpio_regs->int_bothedge); ++ goto out; ++ } else { ++ bank->toggle_edge_mode |= mask; ++ level |= mask; ++ ++ /* ++ * Determine gpio state. If 1 next interrupt should be ++ * falling otherwise rising. ++ */ ++ data = readl(bank->reg_base + bank->gpio_regs->ext_port); ++ if (data & mask) ++ polarity &= ~mask; ++ else ++ polarity |= mask; ++ } + break; + case IRQ_TYPE_EDGE_RISING: + bank->toggle_edge_mode &= ~mask; +@@ -328,19 +454,17 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) + polarity &= ~mask; + break; + default: +- irq_gc_unlock(gc); +- raw_spin_unlock_irqrestore(&bank->slock, flags); +- clk_disable(bank->clk); +- return -EINVAL; ++ ret = -EINVAL; ++ goto out; + } + +- writel_relaxed(level, gc->reg_base + bank->gpio_regs->int_type); +- writel_relaxed(polarity, gc->reg_base + bank->gpio_regs->int_polarity); +- ++ rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type); ++ rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity); ++out: + irq_gc_unlock(gc); + raw_spin_unlock_irqrestore(&bank->slock, flags); + +- return 0; ++ return ret; + } + + static void rockchip_irq_suspend(struct irq_data *d) +@@ -362,19 +486,12 @@ static void rockchip_irq_resume(struct irq_data *d) + + static void rockchip_irq_enable(struct irq_data *d) + { +- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); +- struct rockchip_pin_bank *bank = gc->private; +- + irq_gc_mask_clr_bit(d); + } + + static void rockchip_irq_disable(struct irq_data *d) + { +- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); +- struct rockchip_pin_bank *bank = gc->private; +- + irq_gc_mask_set_bit(d); +- clk_disable(bank->clk); + } + + static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) +@@ -403,6 +520,11 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) + } + + gc = irq_get_domain_generic_chip(bank->domain, 0); ++ if (bank->gpio_type == GPIO_TYPE_V2) { ++ gc->reg_writel = gpio_writel_v2; ++ gc->reg_readl = gpio_readl_v2; ++ } ++ + gc->reg_base = bank->reg_base; + gc->private = bank; + gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask; +@@ -423,9 +545,9 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) + * Our driver only uses the concept of masked and always keeps + * things enabled, so for us that's all masked and all enabled. + */ +- writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->int_mask); +- writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->port_eoi); +- writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->int_en); ++ rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask); ++ rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi); ++ rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en); + gc->mask_cache = 0xffffffff; + + irq_set_chained_handler_and_data(bank->irq, +@@ -503,6 +625,7 @@ static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank) + static int rockchip_get_bank_data(struct rockchip_pin_bank *bank) + { + struct resource res; ++ int id = 0; + + if (of_address_to_resource(bank->of_node, 0, &res)) { + dev_err(bank->dev, "cannot find IO resource for bank\n"); +@@ -514,15 +637,31 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank) + return PTR_ERR(bank->reg_base); + + bank->irq = irq_of_parse_and_map(bank->of_node, 0); +- +- bank->gpio_regs = &gpio_regs_v1; +- bank->gpio_type = GPIO_TYPE_V1; ++ if (!bank->irq) ++ return -EINVAL; + + bank->clk = of_clk_get(bank->of_node, 0); +- if (!IS_ERR(bank->clk)) +- return clk_prepare_enable(bank->clk); ++ if (IS_ERR(bank->clk)) ++ return PTR_ERR(bank->clk); ++ ++ clk_prepare_enable(bank->clk); ++ id = readl(bank->reg_base + gpio_regs_v2.version_id); ++ ++ /* If not gpio v2, that is default to v1. */ ++ if (id == GPIO_TYPE_V2) { ++ bank->gpio_regs = &gpio_regs_v2; ++ bank->gpio_type = GPIO_TYPE_V2; ++ bank->db_clk = of_clk_get(bank->of_node, 1); ++ if (IS_ERR(bank->db_clk)) { ++ dev_err(bank->dev, "cannot find debounce clk\n"); ++ clk_disable_unprepare(bank->clk); ++ return -EINVAL; ++ } ++ } else { ++ bank->gpio_regs = &gpio_regs_v1; ++ bank->gpio_type = GPIO_TYPE_V1; ++ } + +- bank->clk = NULL; + return 0; + } + +diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h +index 1b774b6bbc3e..589d4d2a98c9 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.h ++++ b/drivers/pinctrl/pinctrl-rockchip.h +@@ -121,6 +121,7 @@ struct rockchip_drv { + * @reg_base: register base of the gpio bank + * @regmap_pull: optional separate register for additional pull settings + * @clk: clock of the gpio bank ++ * @db_clk: clock of the gpio debounce + * @irq: interrupt of the gpio bank + * @saved_masks: Saved content of GPIO_INTEN at suspend time. + * @pin_base: first pin number +@@ -146,6 +147,7 @@ struct rockchip_pin_bank { + void __iomem *reg_base; + struct regmap *regmap_pull; + struct clk *clk; ++ struct clk *db_clk; + int irq; + u32 saved_masks; + u32 pin_base; +-- +2.31.1 + diff --git a/patches.suse/gpio-rockchip-use-struct-rockchip_gpio_regs-for-gpio.patch b/patches.suse/gpio-rockchip-use-struct-rockchip_gpio_regs-for-gpio.patch new file mode 100644 index 0000000..43bb354 --- /dev/null +++ b/patches.suse/gpio-rockchip-use-struct-rockchip_gpio_regs-for-gpio.patch @@ -0,0 +1,311 @@ +From: Jianqun Xu +Date: Mon, 16 Aug 2021 09:21:11 +0800 +Subject: gpio/rockchip: use struct rockchip_gpio_regs for gpio controller + +Git-commit: ff96a8c21cdbf4a36fbad341af3a41db44bbf878 +Patch-mainline: v5.15-rc1 +References: bsc#1192217 + +Store register offsets in the struct rockchip_gpio_regs, this patch +prepare for the driver update for new gpio controller. + +Reviewed-by: Heiko Stuebner +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20210816012111.1119125-1-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/gpio/gpio-rockchip.c | 86 ++++++++++++++++-------------- + drivers/pinctrl/pinctrl-rockchip.h | 38 +++++++++++++ + 2 files changed, 85 insertions(+), 39 deletions(-) + +diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c +index b455fcf7efda..d6c07a957bd8 100644 +--- a/drivers/gpio/gpio-rockchip.c ++++ b/drivers/gpio/gpio-rockchip.c +@@ -24,19 +24,21 @@ + #include "../pinctrl/core.h" + #include "../pinctrl/pinctrl-rockchip.h" + +-/* GPIO control registers */ +-#define GPIO_SWPORT_DR 0x00 +-#define GPIO_SWPORT_DDR 0x04 +-#define GPIO_INTEN 0x30 +-#define GPIO_INTMASK 0x34 +-#define GPIO_INTTYPE_LEVEL 0x38 +-#define GPIO_INT_POLARITY 0x3c +-#define GPIO_INT_STATUS 0x40 +-#define GPIO_INT_RAWSTATUS 0x44 +-#define GPIO_DEBOUNCE 0x48 +-#define GPIO_PORTS_EOI 0x4c +-#define GPIO_EXT_PORT 0x50 +-#define GPIO_LS_SYNC 0x60 ++#define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */ ++ ++static const struct rockchip_gpio_regs gpio_regs_v1 = { ++ .port_dr = 0x00, ++ .port_ddr = 0x04, ++ .int_en = 0x30, ++ .int_mask = 0x34, ++ .int_type = 0x38, ++ .int_polarity = 0x3c, ++ .int_status = 0x40, ++ .int_rawstatus = 0x44, ++ .debounce = 0x48, ++ .port_eoi = 0x4c, ++ .ext_port = 0x50, ++}; + + static int rockchip_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +@@ -44,7 +46,7 @@ static int rockchip_gpio_get_direction(struct gpio_chip *chip, + struct rockchip_pin_bank *bank = gpiochip_get_data(chip); + u32 data; + +- data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); ++ data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr); + if (data & BIT(offset)) + return GPIO_LINE_DIRECTION_OUT; + +@@ -60,13 +62,13 @@ static int rockchip_gpio_set_direction(struct gpio_chip *chip, + + raw_spin_lock_irqsave(&bank->slock, flags); + +- data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); ++ data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr); + /* set bit to 1 for output, 0 for input */ + if (!input) + data |= BIT(offset); + else + data &= ~BIT(offset); +- writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); ++ writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr); + + raw_spin_unlock_irqrestore(&bank->slock, flags); + +@@ -77,7 +79,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, + int value) + { + struct rockchip_pin_bank *bank = gpiochip_get_data(gc); +- void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; ++ void __iomem *reg = bank->reg_base + bank->gpio_regs->port_dr; + unsigned long flags; + u32 data; + +@@ -97,9 +99,10 @@ static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset) + struct rockchip_pin_bank *bank = gpiochip_get_data(gc); + u32 data; + +- data = readl(bank->reg_base + GPIO_EXT_PORT); ++ data = readl(bank->reg_base + bank->gpio_regs->ext_port); + data >>= offset; + data &= 1; ++ + return data; + } + +@@ -107,7 +110,7 @@ static void rockchip_gpio_set_debounce(struct gpio_chip *gc, + unsigned int offset, bool enable) + { + struct rockchip_pin_bank *bank = gpiochip_get_data(gc); +- void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; ++ void __iomem *reg = bank->reg_base + bank->gpio_regs->debounce; + unsigned long flags; + u32 data; + +@@ -207,7 +210,7 @@ static void rockchip_irq_demux(struct irq_desc *desc) + + chained_irq_enter(chip, desc); + +- pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); ++ pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status); + + while (pend) { + unsigned int irq, virq; +@@ -231,24 +234,26 @@ static void rockchip_irq_demux(struct irq_desc *desc) + u32 data, data_old, polarity; + unsigned long flags; + +- data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); ++ data = readl_relaxed(bank->reg_base + ++ bank->gpio_regs->ext_port); + do { + raw_spin_lock_irqsave(&bank->slock, flags); + + polarity = readl_relaxed(bank->reg_base + +- GPIO_INT_POLARITY); ++ bank->gpio_regs->int_polarity); + if (data & BIT(irq)) + polarity &= ~BIT(irq); + else + polarity |= BIT(irq); + writel(polarity, +- bank->reg_base + GPIO_INT_POLARITY); ++ bank->reg_base + ++ bank->gpio_regs->int_polarity); + + raw_spin_unlock_irqrestore(&bank->slock, flags); + + data_old = data; + data = readl_relaxed(bank->reg_base + +- GPIO_EXT_PORT); ++ bank->gpio_regs->ext_port); + } while ((data & BIT(irq)) != (data_old & BIT(irq))); + } + +@@ -270,9 +275,9 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) + + raw_spin_lock_irqsave(&bank->slock, flags); + +- data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); ++ data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr); + data &= ~mask; +- writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); ++ writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr); + + raw_spin_unlock_irqrestore(&bank->slock, flags); + +@@ -284,8 +289,8 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) + raw_spin_lock_irqsave(&bank->slock, flags); + irq_gc_lock(gc); + +- level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); +- polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); ++ level = readl_relaxed(gc->reg_base + bank->gpio_regs->int_type); ++ polarity = readl_relaxed(gc->reg_base + bank->gpio_regs->int_polarity); + + switch (type) { + case IRQ_TYPE_EDGE_BOTH: +@@ -296,7 +301,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) + * Determine gpio state. If 1 next interrupt should be falling + * otherwise rising. + */ +- data = readl(bank->reg_base + GPIO_EXT_PORT); ++ data = readl(bank->reg_base + bank->gpio_regs->ext_port); + if (data & mask) + polarity &= ~mask; + else +@@ -329,8 +334,8 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) + return -EINVAL; + } + +- writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); +- writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); ++ writel_relaxed(level, gc->reg_base + bank->gpio_regs->int_type); ++ writel_relaxed(polarity, gc->reg_base + bank->gpio_regs->int_polarity); + + irq_gc_unlock(gc); + raw_spin_unlock_irqrestore(&bank->slock, flags); +@@ -343,8 +348,8 @@ static void rockchip_irq_suspend(struct irq_data *d) + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct rockchip_pin_bank *bank = gc->private; + +- bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); +- irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); ++ bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask); ++ irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask); + } + + static void rockchip_irq_resume(struct irq_data *d) +@@ -352,7 +357,7 @@ static void rockchip_irq_resume(struct irq_data *d) + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct rockchip_pin_bank *bank = gc->private; + +- irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); ++ irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask); + } + + static void rockchip_irq_enable(struct irq_data *d) +@@ -400,8 +405,8 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) + gc = irq_get_domain_generic_chip(bank->domain, 0); + gc->reg_base = bank->reg_base; + gc->private = bank; +- gc->chip_types[0].regs.mask = GPIO_INTMASK; +- gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; ++ gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask; ++ gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi; + gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; + gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; + gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; +@@ -418,9 +423,9 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) + * Our driver only uses the concept of masked and always keeps + * things enabled, so for us that's all masked and all enabled. + */ +- writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); +- writel_relaxed(0xffffffff, bank->reg_base + GPIO_PORTS_EOI); +- writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); ++ writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->int_mask); ++ writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->port_eoi); ++ writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->int_en); + gc->mask_cache = 0xffffffff; + + irq_set_chained_handler_and_data(bank->irq, +@@ -510,6 +515,9 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank) + + bank->irq = irq_of_parse_and_map(bank->of_node, 0); + ++ bank->gpio_regs = &gpio_regs_v1; ++ bank->gpio_type = GPIO_TYPE_V1; ++ + bank->clk = of_clk_get(bank->of_node, 0); + if (!IS_ERR(bank->clk)) + return clk_prepare_enable(bank->clk); +diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h +index 4aa3d2f1fa67..1b774b6bbc3e 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.h ++++ b/drivers/pinctrl/pinctrl-rockchip.h +@@ -32,6 +32,42 @@ enum rockchip_pinctrl_type { + RK3568, + }; + ++/** ++ * struct rockchip_gpio_regs ++ * @port_dr: data register ++ * @port_ddr: data direction register ++ * @int_en: interrupt enable ++ * @int_mask: interrupt mask ++ * @int_type: interrupt trigger type, such as high, low, edge trriger type. ++ * @int_polarity: interrupt polarity enable register ++ * @int_bothedge: interrupt bothedge enable register ++ * @int_status: interrupt status register ++ * @int_rawstatus: int_status = int_rawstatus & int_mask ++ * @debounce: enable debounce for interrupt signal ++ * @dbclk_div_en: enable divider for debounce clock ++ * @dbclk_div_con: setting for divider of debounce clock ++ * @port_eoi: end of interrupt of the port ++ * @ext_port: port data from external ++ * @version_id: controller version register ++ */ ++struct rockchip_gpio_regs { ++ u32 port_dr; ++ u32 port_ddr; ++ u32 int_en; ++ u32 int_mask; ++ u32 int_type; ++ u32 int_polarity; ++ u32 int_bothedge; ++ u32 int_status; ++ u32 int_rawstatus; ++ u32 debounce; ++ u32 dbclk_div_en; ++ u32 dbclk_div_con; ++ u32 port_eoi; ++ u32 ext_port; ++ u32 version_id; ++}; ++ + /** + * struct rockchip_iomux + * @type: iomux variant using IOMUX_* constants +@@ -126,6 +162,8 @@ struct rockchip_pin_bank { + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range grange; + raw_spinlock_t slock; ++ const struct rockchip_gpio_regs *gpio_regs; ++ u32 gpio_type; + u32 toggle_edge_mode; + u32 recalced_mask; + u32 route_mask; +-- +2.31.1 + diff --git a/patches.suse/intel_idle-Disable-ACPI-_CST-on-Haswell.patch b/patches.suse/intel_idle-Disable-ACPI-_CST-on-Haswell.patch index 9a5c353..370a2eb 100644 --- a/patches.suse/intel_idle-Disable-ACPI-_CST-on-Haswell.patch +++ b/patches.suse/intel_idle-Disable-ACPI-_CST-on-Haswell.patch @@ -3,7 +3,7 @@ Date: Tue, 5 Jan 2021 11:26:33 +0000 Subject: [PATCH] intel_idle: Disable ACPI _CST on Haswell References: bsc#1177399, bsc#1180347, bsc#1180141 -Patch-mainline: No, upstream will always use ACPI information unless disabled by kernel command line +Patch-mainline: Never, upstream will always use ACPI information unless disabled by kernel command line Numerous workload regressions have bisected repeatedly to the commit 6d4f08a6776 ("intel_idle: Use ACPI _CST on server systems") but only on diff --git a/patches.suse/io_uring-ensure-req-submit-is-copied-when-req-is-def.patch b/patches.suse/io_uring-ensure-req-submit-is-copied-when-req-is-def.patch index e8d5023..90bffa9 100644 --- a/patches.suse/io_uring-ensure-req-submit-is-copied-when-req-is-def.patch +++ b/patches.suse/io_uring-ensure-req-submit-is-copied-when-req-is-def.patch @@ -4,8 +4,7 @@ Subject: io_uring: ensure req->submit is copied when req is deferred MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit -Git-commit: d123a552a2d8bff72638794140c050586f9b18c8 -Patch-mainline: 5.3.16 +Patch-mainline: Never, addressed by cleanup in mainline 5.5-rc1, patch from stable commit d123a552a2d8 References: bnc#1151927 5.3.16 There's an issue with deferred requests through drain, where if we do diff --git a/patches.suse/ipv4-make-exception-cache-less-predictible.patch b/patches.suse/ipv4-make-exception-cache-less-predictible.patch new file mode 100644 index 0000000..2591420 --- /dev/null +++ b/patches.suse/ipv4-make-exception-cache-less-predictible.patch @@ -0,0 +1,121 @@ +From: Eric Dumazet +Subject: ipv4: make exception cache less predictible +Git-commit: 67d6d681e15b578c1725bad8ad079e05d1c48a8e +Patch-mainline: v5.15-rc1 +References: bsc#1191790, CVE-2021-20322 +Acked-by: Jiri Bohac + +Even after commit 6457378fe796 ("ipv4: use siphash instead of Jenkins in +fnhe_hashfun()"), an attacker can still use brute force to learn +some secrets from a victim linux host. + +One way to defeat these attacks is to make the max depth of the hash +table bucket a random value. + +Before this patch, each bucket of the hash table used to store exceptions +could contain 6 items under attack. + +After the patch, each bucket would contains a random number of items, +between 6 and 10. The attacker can no longer infer secrets. + +This is slightly increasing memory size used by the hash table, +by 50% in average, we do not expect this to be a problem. + +This patch is more complex than the prior one (IPv6 equivalent), +because IPv4 was reusing the oldest entry. +Since we need to be able to evict more than one entry per +update_or_create_fnhe() call, I had to replace +fnhe_oldest() with fnhe_remove_oldest(). + +Also note that we will queue extra kfree_rcu() calls under stress, +which hopefully wont be a too big issue. + +Fixes: 4895c771c7f0 ("ipv4: Add FIB nexthop exceptions.") +Signed-off-by: Eric Dumazet +Reported-by: Keyu Man +Cc: Willy Tarreau +Signed-off-by: David S. Miller +Reviewed-by: David Ahern +Tested-by: David Ahern +Signed-off-by: David S. Miller + +diff --git a/net/ipv4/route.c b/net/ipv4/route.c +index 1e3b18797070..1b6c8fad6277 100644 +--- a/net/ipv4/route.c ++++ b/net/ipv4/route.c +@@ -587,18 +587,25 @@ static void fnhe_flush_routes(struct fib_nh_exception *fnhe) + } + } + +-static struct fib_nh_exception *fnhe_oldest(struct fnhe_hash_bucket *hash) ++static void fnhe_remove_oldest(struct fnhe_hash_bucket *hash) + { +- struct fib_nh_exception *fnhe, *oldest; ++ struct fib_nh_exception __rcu **fnhe_p, **oldest_p; ++ struct fib_nh_exception *fnhe, *oldest = NULL; + +- oldest = rcu_dereference(hash->chain); +- for (fnhe = rcu_dereference(oldest->fnhe_next); fnhe; +- fnhe = rcu_dereference(fnhe->fnhe_next)) { +- if (time_before(fnhe->fnhe_stamp, oldest->fnhe_stamp)) ++ for (fnhe_p = &hash->chain; ; fnhe_p = &fnhe->fnhe_next) { ++ fnhe = rcu_dereference_protected(*fnhe_p, ++ lockdep_is_held(&fnhe_lock)); ++ if (!fnhe) ++ break; ++ if (!oldest || ++ time_before(fnhe->fnhe_stamp, oldest->fnhe_stamp)) { + oldest = fnhe; ++ oldest_p = fnhe_p; ++ } + } + fnhe_flush_routes(oldest); +- return oldest; ++ *oldest_p = oldest->fnhe_next; ++ kfree_rcu(oldest, rcu); + } + + static u32 fnhe_hashfun(__be32 daddr) +@@ -677,16 +684,21 @@ static void update_or_create_fnhe(struct fib_nh_common *nhc, __be32 daddr, + if (rt) + fill_route_from_fnhe(rt, fnhe); + } else { +- if (depth > FNHE_RECLAIM_DEPTH) +- fnhe = fnhe_oldest(hash); +- else { +- fnhe = kzalloc(sizeof(*fnhe), GFP_ATOMIC); +- if (!fnhe) +- goto out_unlock; +- +- fnhe->fnhe_next = hash->chain; +- rcu_assign_pointer(hash->chain, fnhe); ++ /* Randomize max depth to avoid some side channels attacks. */ ++ int max_depth = FNHE_RECLAIM_DEPTH + ++ prandom_u32_max(FNHE_RECLAIM_DEPTH); ++ ++ while (depth > max_depth) { ++ fnhe_remove_oldest(hash); ++ depth--; + } ++ ++ fnhe = kzalloc(sizeof(*fnhe), GFP_ATOMIC); ++ if (!fnhe) ++ goto out_unlock; ++ ++ fnhe->fnhe_next = hash->chain; ++ + fnhe->fnhe_genid = genid; + fnhe->fnhe_daddr = daddr; + fnhe->fnhe_gw = gw; +@@ -694,6 +706,8 @@ static void update_or_create_fnhe(struct fib_nh_common *nhc, __be32 daddr, + fnhe->fnhe_mtu_locked = lock; + fnhe->fnhe_expires = max(1UL, expires); + ++ rcu_assign_pointer(hash->chain, fnhe); ++ + /* Exception created; mark the cached routes for the nexthop + * stale, so anyone caching it rechecks if this exception + * applies to them. +-- +2.33.0 + diff --git a/patches.suse/ipv4-use-siphash-instead-of-jenkins-in-fnhe_hashfun.patch b/patches.suse/ipv4-use-siphash-instead-of-jenkins-in-fnhe_hashfun.patch new file mode 100644 index 0000000..7dac782 --- /dev/null +++ b/patches.suse/ipv4-use-siphash-instead-of-jenkins-in-fnhe_hashfun.patch @@ -0,0 +1,48 @@ +From: Eric Dumazet +Subject: ipv4: use siphash instead of Jenkins in fnhe_hashfun() +Git-commit: 6457378fe796815c973f631a1904e147d6ee33b1 +Patch-mainline: v5.14 +References: bsc#1191790, CVE-2021-20322 +Acked-by: Jiri Bohac + +A group of security researchers brought to our attention +the weakness of hash function used in fnhe_hashfun(). + +Lets use siphash instead of Jenkins Hash, to considerably +reduce security risks. + +Also remove the inline keyword, this really is distracting. + +Fixes: d546c621542d ("ipv4: harden fnhe_hashfun()") +Signed-off-by: Eric Dumazet +Reported-by: Keyu Man +Cc: Willy Tarreau +Signed-off-by: David S. Miller + +--- + net/ipv4/route.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/net/ipv4/route.c ++++ b/net/ipv4/route.c +@@ -617,14 +617,14 @@ static struct fib_nh_exception *fnhe_old + return oldest; + } + +-static inline u32 fnhe_hashfun(__be32 daddr) ++static u32 fnhe_hashfun(__be32 daddr) + { +- static u32 fnhe_hashrnd __read_mostly; +- u32 hval; ++ static siphash_key_t fnhe_hash_key __read_mostly; ++ u64 hval; + +- net_get_random_once(&fnhe_hashrnd, sizeof(fnhe_hashrnd)); +- hval = jhash_1word((__force u32) daddr, fnhe_hashrnd); +- return hash_32(hval, FNHE_HASH_SHIFT); ++ net_get_random_once(&fnhe_hash_key, sizeof(fnhe_hash_key)); ++ hval = siphash_1u32((__force u32)daddr, &fnhe_hash_key); ++ return hash_64(hval, FNHE_HASH_SHIFT); + } + + static void fill_route_from_fnhe(struct rtable *rt, struct fib_nh_exception *fnhe) diff --git a/patches.suse/ipv6-make-exception-cache-less-predictible.patch b/patches.suse/ipv6-make-exception-cache-less-predictible.patch new file mode 100644 index 0000000..aa76710 --- /dev/null +++ b/patches.suse/ipv6-make-exception-cache-less-predictible.patch @@ -0,0 +1,59 @@ +From: Eric Dumazet +Subject: ipv6: make exception cache less predictible +Git-commit: a00df2caffed3883c341d5685f830434312e4a43 +Patch-mainline: v5.15-rc1 +References: bsc#1191790, CVE-2021-20322 +Acked-by: Jiri Bohac + +Even after commit 4785305c05b2 ("ipv6: use siphash in rt6_exception_hash()"), +an attacker can still use brute force to learn some secrets from a victim +linux host. + +One way to defeat these attacks is to make the max depth of the hash +table bucket a random value. + +Before this patch, each bucket of the hash table used to store exceptions +could contain 6 items under attack. + +After the patch, each bucket would contains a random number of items, +between 6 and 10. The attacker can no longer infer secrets. + +This is slightly increasing memory size used by the hash table, +we do not expect this to be a problem. + +Following patch is dealing with the same issue in IPv4. + +Fixes: 35732d01fe31 ("ipv6: introduce a hash table to store dst cache") +Signed-off-by: Eric Dumazet +Reported-by: Keyu Man +Cc: Wei Wang +Cc: Martin KaFai Lau +Reviewed-by: David Ahern +Signed-off-by: David S. Miller + +diff --git a/net/ipv6/route.c b/net/ipv6/route.c +index f34137d5bf85..dbc224023977 100644 +--- a/net/ipv6/route.c ++++ b/net/ipv6/route.c +@@ -1657,6 +1657,7 @@ static int rt6_insert_exception(struct rt6_info *nrt, + struct in6_addr *src_key = NULL; + struct rt6_exception *rt6_ex; + struct fib6_nh *nh = res->nh; ++ int max_depth; + int err = 0; + + spin_lock_bh(&rt6_exception_lock); +@@ -1711,7 +1712,9 @@ static int rt6_insert_exception(struct rt6_info *nrt, + bucket->depth++; + net->ipv6.rt6_stats->fib_rt_cache++; + +- if (bucket->depth > FIB6_MAX_DEPTH) ++ /* Randomize max depth to avoid some side channels attacks. */ ++ max_depth = FIB6_MAX_DEPTH + prandom_u32_max(FIB6_MAX_DEPTH); ++ while (bucket->depth > max_depth) + rt6_exception_remove_oldest(bucket); + + out: +-- +2.33.0 + diff --git a/patches.suse/ipv6-use-siphash-in-rt6_exception_hash.patch b/patches.suse/ipv6-use-siphash-in-rt6_exception_hash.patch new file mode 100644 index 0000000..8ada13a --- /dev/null +++ b/patches.suse/ipv6-use-siphash-in-rt6_exception_hash.patch @@ -0,0 +1,69 @@ +From: Eric Dumazet +Subject: ipv6: use siphash in rt6_exception_hash() +Git-commit: 4785305c05b25a242e5314cc821f54ade4c18810 +Patch-mainline: v5.14 +References: bsc#1191790, CVE-2021-20322 +Acked-by: Jiri Bohac + +A group of security researchers brought to our attention +the weakness of hash function used in rt6_exception_hash() + +Lets use siphash instead of Jenkins Hash, to considerably +reduce security risks. + +Following patch deals with IPv4. + +Fixes: 35732d01fe31 ("ipv6: introduce a hash table to store dst cache") +Signed-off-by: Eric Dumazet +Reported-by: Keyu Man +Cc: Wei Wang +Cc: Martin KaFai Lau +Acked-by: Wei Wang +Signed-off-by: David S. Miller + +diff --git a/net/ipv6/route.c b/net/ipv6/route.c +index b6ddf23d3833..c5e8ecb96426 100644 +--- a/net/ipv6/route.c ++++ b/net/ipv6/route.c +@@ -41,6 +41,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1484,17 +1485,24 @@ static void rt6_exception_remove_oldest(struct rt6_exception_bucket *bucket) + static u32 rt6_exception_hash(const struct in6_addr *dst, + const struct in6_addr *src) + { +- static u32 seed __read_mostly; +- u32 val; ++ static siphash_key_t rt6_exception_key __read_mostly; ++ struct { ++ struct in6_addr dst; ++ struct in6_addr src; ++ } __aligned(SIPHASH_ALIGNMENT) combined = { ++ .dst = *dst, ++ }; ++ u64 val; + +- net_get_random_once(&seed, sizeof(seed)); +- val = jhash2((const u32 *)dst, sizeof(*dst)/sizeof(u32), seed); ++ net_get_random_once(&rt6_exception_key, sizeof(rt6_exception_key)); + + #ifdef CONFIG_IPV6_SUBTREES + if (src) +- val = jhash2((const u32 *)src, sizeof(*src)/sizeof(u32), val); ++ combined.src = *src; + #endif +- return hash_32(val, FIB6_EXCEPTION_BUCKET_SIZE_SHIFT); ++ val = siphash(&combined, sizeof(combined), &rt6_exception_key); ++ ++ return hash_64(val, FIB6_EXCEPTION_BUCKET_SIZE_SHIFT); + } + + /* Helper function to find the cached rt in the hash table +-- +2.33.0 + diff --git a/patches.suse/locking-rwsem-Disable-reader-optimistic-spinning.patch b/patches.suse/locking-rwsem-Disable-reader-optimistic-spinning.patch index c884b31..c7acf9c 100644 --- a/patches.suse/locking-rwsem-Disable-reader-optimistic-spinning.patch +++ b/patches.suse/locking-rwsem-Disable-reader-optimistic-spinning.patch @@ -4,8 +4,7 @@ Date: Thu, 1 Oct 2020 09:01:42 -0700 Subject: [PATCH] locking/rwsem: Disable reader optimistic spinning References: bnc#1176588 -Patch-mainline: Not yet, would need to be posted for discussion -X-note: Obsoleted by 617f3ef95177840c77f59c2aec1029d27d5547d6 (jeffm) +Patch-mainline: Never, obsoleted in 5.11-rc1 by 617f3ef95177840c77f59c2aec1029d27d5547d6 (jeffm) Reader spinning can cause performance issues in workloads that could otherwise benefit if the rwsem waiter would immediately diff --git a/patches.suse/media-firewire-firedtv-avc-fix-a-buffer-overflow-in-.patch b/patches.suse/media-firewire-firedtv-avc-fix-a-buffer-overflow-in-.patch index 033897e..509bb92 100644 --- a/patches.suse/media-firewire-firedtv-avc-fix-a-buffer-overflow-in-.patch +++ b/patches.suse/media-firewire-firedtv-avc-fix-a-buffer-overflow-in-.patch @@ -2,9 +2,8 @@ From 35d2969ea3c7d32aee78066b1f3cf61a0d935a4e Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 7 Jun 2021 17:23:48 +0200 Subject: [PATCH] media: firewire: firedtv-avc: fix a buffer overflow in avc_ca_pmt() +Patch-mainline: v5.16-rc1 Git-commit: 35d2969ea3c7d32aee78066b1f3cf61a0d935a4e -Git-repo: git://linuxtv.org/mchehab/media-next.git -Patch-mainline: Queued in subsystem maintainer repo References: CVE-2021-42739 CVE-2021-3542 bsc#1184673 The bounds checking in avc_ca_pmt() is not strict enough. It should diff --git a/patches.suse/mm-hugetlb-initialize-hugetlb_usage-in-mm_init.patch b/patches.suse/mm-hugetlb-initialize-hugetlb_usage-in-mm_init.patch new file mode 100644 index 0000000..2be07b6 --- /dev/null +++ b/patches.suse/mm-hugetlb-initialize-hugetlb_usage-in-mm_init.patch @@ -0,0 +1,76 @@ +From: Liu Zixian +Date: Wed, 8 Sep 2021 18:10:05 -0700 +Subject: mm/hugetlb: initialize hugetlb_usage in mm_init +Git-commit: 13db8c50477d83ad3e3b9b0ae247e5cd833a7ae4 +Patch-mainline: v5.15-rc1 +References: bsc#1192906 + +After fork, the child process will get incorrect (2x) hugetlb_usage. If +a process uses 5 2MB hugetlb pages in an anonymous mapping, + + HugetlbPages: 10240 kB + +and then forks, the child will show, + + HugetlbPages: 20480 kB + +The reason for double the amount is because hugetlb_usage will be copied +from the parent and then increased when we copy page tables from parent +to child. Child will have 2x actual usage. + +Fix this by adding hugetlb_count_init in mm_init. + +Link: https://lkml.kernel.org/r/20210826071742.877-1-liuzixian4@huawei.com +Fixes: 5d317b2b6536 ("mm: hugetlb: proc: add HugetlbPages field to /proc/PID/status") +Signed-off-by: Liu Zixian +Reviewed-by: Naoya Horiguchi +Reviewed-by: Mike Kravetz +Cc: +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +Acked-by: Michal Koutný +--- + include/linux/hugetlb.h | 9 +++++++++ + kernel/fork.c | 1 + + 2 files changed, 10 insertions(+) + +diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h +index f7ca1a3870ea..1faebe1cd0ed 100644 +--- a/include/linux/hugetlb.h ++++ b/include/linux/hugetlb.h +@@ -858,6 +858,11 @@ static inline spinlock_t *huge_pte_lockptr(struct hstate *h, + + void hugetlb_report_usage(struct seq_file *m, struct mm_struct *mm); + ++static inline void hugetlb_count_init(struct mm_struct *mm) ++{ ++ atomic_long_set(&mm->hugetlb_usage, 0); ++} ++ + static inline void hugetlb_count_add(long l, struct mm_struct *mm) + { + atomic_long_add(l, &mm->hugetlb_usage); +@@ -1042,6 +1047,10 @@ static inline spinlock_t *huge_pte_lockptr(struct hstate *h, + return &mm->page_table_lock; + } + ++static inline void hugetlb_count_init(struct mm_struct *mm) ++{ ++} ++ + static inline void hugetlb_report_usage(struct seq_file *f, struct mm_struct *m) + { + } +diff --git a/kernel/fork.c b/kernel/fork.c +index ff5be23800af..38681ad44c76 100644 +--- a/kernel/fork.c ++++ b/kernel/fork.c +@@ -1063,6 +1063,7 @@ static struct mm_struct *mm_init(struct mm_struct *mm, struct task_struct *p, + mm->pmd_huge_pte = NULL; + #endif + mm_init_uprobes_state(mm); ++ hugetlb_count_init(mm); + + if (current->mm) { + mm->flags = current->mm->flags & MMF_INIT_MASK; + diff --git a/patches.suse/net-dsa-felix-re-enable-TX-flow-control-in-ocelot_po.patch b/patches.suse/net-dsa-felix-re-enable-TX-flow-control-in-ocelot_po.patch new file mode 100644 index 0000000..045b341 --- /dev/null +++ b/patches.suse/net-dsa-felix-re-enable-TX-flow-control-in-ocelot_po.patch @@ -0,0 +1,49 @@ +From: Vladimir Oltean +Date: Tue, 8 Jun 2021 14:15:35 +0300 +Subject: net: dsa: felix: re-enable TX flow control in ocelot_port_flush() + +Git-commit: 1650bdb1c516c248fb06f6d076559ff6437a5853 +Patch-mainline: v5.13-rc7 +References: git-fixes + +Because flow control is set up statically in ocelot_init_port(), and not +in phylink_mac_link_up(), what happens is that after the blamed commit, +the flow control remains disabled after the port flushing procedure. + +Fixes: eb4733d7cffc ("net: dsa: felix: implement port flushing on .phylink_mac_link_down") +Signed-off-by: Vladimir Oltean +Signed-off-by: David S. Miller +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/net/ethernet/mscc/ocelot.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/net/ethernet/mscc/ocelot.c ++++ b/drivers/net/ethernet/mscc/ocelot.c +@@ -404,6 +404,7 @@ static u32 ocelot_read_eq_avail(struct o + + int ocelot_port_flush(struct ocelot *ocelot, int port) + { ++ unsigned int pause_ena; + int err, val; + + /* Disable dequeuing from the egress queues */ +@@ -412,6 +413,8 @@ int ocelot_port_flush(struct ocelot *oce + QSYS_PORT_MODE, port); + + /* Disable flow control */ ++ pause_ena = ocelot_read_rix(ocelot, SYS_PAUSE_CFG, port) & ++ SYS_PAUSE_CFG_PAUSE_ENA; + ocelot_rmw_rix(ocelot, 0, SYS_PAUSE_CFG_PAUSE_ENA, SYS_PAUSE_CFG, port); + + /* Disable priority flow control */ +@@ -447,6 +450,9 @@ int ocelot_port_flush(struct ocelot *oce + /* Clear flushing again. */ + ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); + ++ /* Re-enable flow control */ ++ ocelot_rmw_rix(ocelot, pause_ena, SYS_PAUSE_CFG_PAUSE_ENA, SYS_PAUSE_CFG, port); ++ + return err; + } + EXPORT_SYMBOL(ocelot_port_flush); diff --git a/patches.suse/net-mscc-ocelot-fix-hardware-timestamp-dequeue-logic.patch b/patches.suse/net-mscc-ocelot-fix-hardware-timestamp-dequeue-logic.patch new file mode 100644 index 0000000..f81b109 --- /dev/null +++ b/patches.suse/net-mscc-ocelot-fix-hardware-timestamp-dequeue-logic.patch @@ -0,0 +1,57 @@ +From: laurent brando +Date: Mon, 27 Jul 2020 18:26:14 +0800 +Subject: net: mscc: ocelot: fix hardware timestamp dequeue logic + + +Git-commit: 5fd82200d870a5dd3e509c98ef2041f580b2c0e1 +Patch-mainline: v5.8 +References: git-fixes + +The next hw timestamp should be snapshoot to the read registers +only once the current timestamp has been read. +If none of the pending skbs matches the current HW timestamp +just gracefully flush the available timestamp by reading it. + +Signed-off-by: laurent brando +Signed-off-by: Vladimir Oltean +Signed-off-by: Yangbo Lu +Signed-off-by: David S. Miller +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/net/ethernet/mscc/ocelot.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c +index 9cfe1fd98c30..f17da67a4622 100644 +--- a/drivers/net/ethernet/mscc/ocelot.c ++++ b/drivers/net/ethernet/mscc/ocelot.c +@@ -748,21 +748,21 @@ void ocelot_get_txtstamp(struct ocelot *ocelot) + + spin_unlock_irqrestore(&port->tx_skbs.lock, flags); + +- /* Next ts */ +- ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); ++ /* Get the h/w timestamp */ ++ ocelot_get_hwtimestamp(ocelot, &ts); + + if (unlikely(!skb_match)) + continue; + +- /* Get the h/w timestamp */ +- ocelot_get_hwtimestamp(ocelot, &ts); +- + /* Set the timestamp into the skb */ + memset(&shhwtstamps, 0, sizeof(shhwtstamps)); + shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); + skb_tstamp_tx(skb_match, &shhwtstamps); + + dev_kfree_skb_any(skb_match); ++ ++ /* Next ts */ ++ ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); + } + } + EXPORT_SYMBOL(ocelot_get_txtstamp); +-- +2.31.1 + diff --git a/patches.suse/net-mscc-ocelot-warn-when-a-PTP-IRQ-is-raised-for-an.patch b/patches.suse/net-mscc-ocelot-warn-when-a-PTP-IRQ-is-raised-for-an.patch new file mode 100644 index 0000000..2ee0210 --- /dev/null +++ b/patches.suse/net-mscc-ocelot-warn-when-a-PTP-IRQ-is-raised-for-an.patch @@ -0,0 +1,51 @@ +From: Vladimir Oltean +Date: Tue, 12 Oct 2021 14:40:37 +0300 +Subject: net: mscc: ocelot: warn when a PTP IRQ is raised for an unknown skb + +Git-commit: 9fde506e0c53b8309f69b18b4b8144c544b4b3b1 +Patch-mainline: v5.15-rc6 +References: git-fixes + +When skb_match is NULL, it means we received a PTP IRQ for a timestamp +ID that the kernel has no idea about, since there is no skb in the +timestamping queue with that timestamp ID. + +This is a grave error and not something to just "continue" over. +So print a big warning in case this happens. + +Also, move the check above ocelot_get_hwtimestamp(), there is no point +in reading the full 64-bit current PTP time if we're not going to do +anything with it anyway for this skb. + +Fixes: 4e3b0468e6d7 ("net: mscc: PTP Hardware Clock (PHC) support") +Signed-off-by: Vladimir Oltean +Reviewed-by: Florian Fainelli +Signed-off-by: Jakub Kicinski +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/net/ethernet/mscc/ocelot.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c +index 9c62f1d13adc..687c07c338cd 100644 +--- a/drivers/net/ethernet/mscc/ocelot.c ++++ b/drivers/net/ethernet/mscc/ocelot.c +@@ -747,12 +747,12 @@ void ocelot_get_txtstamp(struct ocelot *ocelot) + + spin_unlock_irqrestore(&port->tx_skbs.lock, flags); + ++ if (WARN_ON(!skb_match)) ++ continue; ++ + /* Get the h/w timestamp */ + ocelot_get_hwtimestamp(ocelot, &ts); + +- if (unlikely(!skb_match)) +- continue; +- + /* Set the timestamp into the skb */ + memset(&shhwtstamps, 0, sizeof(shhwtstamps)); + shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); +-- +2.31.1 + diff --git a/patches.suse/net-smc-Correct-smc-link-connection-counter-in-case-of-smc-client b/patches.suse/net-smc-Correct-smc-link-connection-counter-in-case-of-smc-client new file mode 100644 index 0000000..53bdc78 --- /dev/null +++ b/patches.suse/net-smc-Correct-smc-link-connection-counter-in-case-of-smc-client @@ -0,0 +1,60 @@ +From: Guvenc Gulce +Date: Mon, 9 Aug 2021 11:05:57 +0200 +Subject: net/smc: Correct smc link connection counter in case of smc client +Git-commit: 64513d269e8971aabb7e787955a1b320e3031306 +Patch-mainline: v5.14-rc6 +References: git-fixes + +SMC clients may be assigned to a different link after the initial +connection between two peers was established. In such a case, +the connection counter was not correctly set. + +Update the connection counter correctly when a smc client connection +is assigned to a different smc link. + +Fixes: 07d51580ff65 ("net/smc: Add connection counters for links") +Signed-off-by: Guvenc Gulce +Tested-by: Karsten Graul +Signed-off-by: David S. Miller +Acked-by: Petr Tesarik +--- + net/smc/af_smc.c | 2 +- + net/smc/smc_core.c | 4 ++-- + net/smc/smc_core.h | 2 ++ + 3 files changed, 5 insertions(+), 3 deletions(-) + +--- a/net/smc/af_smc.c ++++ b/net/smc/af_smc.c +@@ -757,7 +757,7 @@ static int smc_connect_rdma(struct smc_s + reason_code = SMC_CLC_DECL_NOSRVLINK; + goto connect_abort; + } +- smc->conn.lnk = link; ++ smc_switch_link_and_count(&smc->conn, link); + } + + /* create send buffer and rmb */ +--- a/net/smc/smc_core.c ++++ b/net/smc/smc_core.c +@@ -916,8 +916,8 @@ static int smc_switch_cursor(struct smc_ + return rc; + } + +-static void smc_switch_link_and_count(struct smc_connection *conn, +- struct smc_link *to_lnk) ++void smc_switch_link_and_count(struct smc_connection *conn, ++ struct smc_link *to_lnk) + { + atomic_dec(&conn->lnk->conn_cnt); + conn->lnk = to_lnk; +--- a/net/smc/smc_core.h ++++ b/net/smc/smc_core.h +@@ -445,6 +445,8 @@ void smc_core_exit(void); + int smcr_link_init(struct smc_link_group *lgr, struct smc_link *lnk, + u8 link_idx, struct smc_init_info *ini); + void smcr_link_clear(struct smc_link *lnk, bool log); ++void smc_switch_link_and_count(struct smc_connection *conn, ++ struct smc_link *to_lnk); + int smcr_buf_map_lgr(struct smc_link *lnk); + int smcr_buf_reg_lgr(struct smc_link *lnk); + void smcr_lgr_set_type(struct smc_link_group *lgr, enum smc_lgr_type new_type); diff --git a/patches.suse/net-smc-fix-workqueue-leaked-lock-in-smc_conn_abort_work b/patches.suse/net-smc-fix-workqueue-leaked-lock-in-smc_conn_abort_work new file mode 100644 index 0000000..4da72d2 --- /dev/null +++ b/patches.suse/net-smc-fix-workqueue-leaked-lock-in-smc_conn_abort_work @@ -0,0 +1,41 @@ +From: Karsten Graul +Date: Mon, 20 Sep 2021 21:18:15 +0200 +Subject: net/smc: fix 'workqueue leaked lock' in smc_conn_abort_work +Git-commit: a18cee4791b1123d0a6579a7c89f4b87e48abe03 +Patch-mainline: v5.15-rc3 +References: git-fixes + +The abort_work is scheduled when a connection was detected to be +out-of-sync after a link failure. The work calls smc_conn_kill(), +which calls smc_close_active_abort() and that might end up calling +smc_close_cancel_work(). +smc_close_cancel_work() cancels any pending close_work and tx_work but +needs to release the sock_lock before and acquires the sock_lock again +afterwards. So when the sock_lock was NOT acquired before then it may +be held after the abort_work completes. Thats why the sock_lock is +acquired before the call to smc_conn_kill() in __smc_lgr_terminate(), +but this is missing in smc_conn_abort_work(). + +Fix that by acquiring the sock_lock first and release it after the +call to smc_conn_kill(). + +Fixes: b286a0651e44 ("net/smc: handle incoming CDC validation message") +Signed-off-by: Karsten Graul +Signed-off-by: David S. Miller +Acked-by: Petr Tesarik +--- + net/smc/smc_core.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/net/smc/smc_core.c ++++ b/net/smc/smc_core.c +@@ -1488,7 +1488,9 @@ static void smc_conn_abort_work(struct w + abort_work); + struct smc_sock *smc = container_of(conn, struct smc_sock, conn); + ++ lock_sock(&smc->sk); + smc_conn_kill(conn, true); ++ release_sock(&smc->sk); + sock_put(&smc->sk); /* sock_hold done by schedulers of abort_work */ + } + diff --git a/patches.suse/net-stmmac-add-EHL-2.5Gbps-PCI-info-and-PCI-ID.patch b/patches.suse/net-stmmac-add-EHL-2.5Gbps-PCI-info-and-PCI-ID.patch new file mode 100644 index 0000000..5cf20ed --- /dev/null +++ b/patches.suse/net-stmmac-add-EHL-2.5Gbps-PCI-info-and-PCI-ID.patch @@ -0,0 +1,71 @@ +From 7cffb7b9f1f553d548de8904666aac1e5225eb1f Mon Sep 17 00:00:00 2001 +From: Voon Weifeng +Date: Tue, 31 Mar 2020 01:05:12 +0800 +Subject: [PATCH 7/8] net: stmmac: add EHL 2.5Gbps PCI info and PCI ID +Git-commit: d63439f575dc3927331d8fbc6448f15902187d38 +Patch-mainline: v5.7-rc1 +References: bsc#1192691 + +Add EHL SGMII 2.5Gbps PCI info and PCI ID + +Signed-off-by: Voon Weifeng +Signed-off-by: David S. Miller +Signed-off-by: Denis Kirjanov +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 24 +++++++++++++++-------- + 1 file changed, 16 insertions(+), 8 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +index 1b0fb0093920..1f14add3ea7a 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +@@ -535,30 +535,38 @@ static int __maybe_unused intel_eth_pci_resume(struct device *dev) + static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, + intel_eth_pci_resume); + +-#define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937 +-#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30 +-#define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31 ++#define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937 ++#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30 ++#define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31 ++#define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32 + /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC + * which are named PSE0 and PSE1 + */ +-#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0 +-#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1 +-#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0 +-#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1 +-#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac ++#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0 ++#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1 ++#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2 ++#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0 ++#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1 ++#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2 ++#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac + + static const struct pci_device_id intel_eth_pci_id_table[] = { + { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_pci_info) }, + { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_pci_info) }, + { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_pci_info) }, ++ { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_pci_info) }, + { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, + &ehl_pse0_rgmii1g_pci_info) }, + { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, + &ehl_pse0_sgmii1g_pci_info) }, ++ { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, ++ &ehl_pse0_sgmii1g_pci_info) }, + { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, + &ehl_pse1_rgmii1g_pci_info) }, + { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, + &ehl_pse1_sgmii1g_pci_info) }, ++ { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, ++ &ehl_pse1_sgmii1g_pci_info) }, + { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_pci_info) }, + {} + }; +-- +2.16.4 + diff --git a/patches.suse/net-stmmac-add-EHL-PSE0-PSE1-1Gbps-PCI-info-and-PCI-.patch b/patches.suse/net-stmmac-add-EHL-PSE0-PSE1-1Gbps-PCI-info-and-PCI-.patch new file mode 100644 index 0000000..24dbec5 --- /dev/null +++ b/patches.suse/net-stmmac-add-EHL-PSE0-PSE1-1Gbps-PCI-info-and-PCI-.patch @@ -0,0 +1,121 @@ +From ff5af83a74f523d2668ae0ed7d076fed1f53eea3 Mon Sep 17 00:00:00 2001 +From: Voon Weifeng +Date: Tue, 31 Mar 2020 01:05:11 +0800 +Subject: [PATCH 6/8] net: stmmac: add EHL PSE0 & PSE1 1Gbps PCI info and PCI + ID +Git-commit: 67c08ac4140a4ae999c7d7e1d4c172fc852111d8 +Patch-mainline: v5.7-rc1 +References: bsc#1192691 + +Add EHL PSE0/1 RGMII & SGMII 1Gbps PCI info and PCI ID + +Signed-off-by: Voon Weifeng +Signed-off-by: Ong Boon Leong +Signed-off-by: David S. Miller +Signed-off-by: Denis Kirjanov +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 75 +++++++++++++++++++++++ + 1 file changed, 75 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +index ade17cfc9fa1..1b0fb0093920 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +@@ -208,6 +208,66 @@ static struct stmmac_pci_info ehl_rgmii1g_pci_info = { + .setup = ehl_rgmii_data, + }; + ++static int ehl_pse0_common_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ plat->bus_id = 2; ++ plat->phy_addr = 1; ++ return ehl_common_data(pdev, plat); ++} ++ ++static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; ++ return ehl_pse0_common_data(pdev, plat); ++} ++ ++static struct stmmac_pci_info ehl_pse0_rgmii1g_pci_info = { ++ .setup = ehl_pse0_rgmii1g_data, ++}; ++ ++static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ plat->phy_interface = PHY_INTERFACE_MODE_SGMII; ++ return ehl_pse0_common_data(pdev, plat); ++} ++ ++static struct stmmac_pci_info ehl_pse0_sgmii1g_pci_info = { ++ .setup = ehl_pse0_sgmii1g_data, ++}; ++ ++static int ehl_pse1_common_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ plat->bus_id = 3; ++ plat->phy_addr = 1; ++ return ehl_common_data(pdev, plat); ++} ++ ++static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; ++ return ehl_pse1_common_data(pdev, plat); ++} ++ ++static struct stmmac_pci_info ehl_pse1_rgmii1g_pci_info = { ++ .setup = ehl_pse1_rgmii1g_data, ++}; ++ ++static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ plat->phy_interface = PHY_INTERFACE_MODE_SGMII; ++ return ehl_pse1_common_data(pdev, plat); ++} ++ ++static struct stmmac_pci_info ehl_pse1_sgmii1g_pci_info = { ++ .setup = ehl_pse1_sgmii1g_data, ++}; ++ + static int tgl_common_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) + { +@@ -478,12 +538,27 @@ static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, + #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937 + #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30 + #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31 ++/* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC ++ * which are named PSE0 and PSE1 ++ */ ++#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0 ++#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1 ++#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0 ++#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1 + #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac + + static const struct pci_device_id intel_eth_pci_id_table[] = { + { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_pci_info) }, + { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_pci_info) }, + { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_pci_info) }, ++ { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, ++ &ehl_pse0_rgmii1g_pci_info) }, ++ { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, ++ &ehl_pse0_sgmii1g_pci_info) }, ++ { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, ++ &ehl_pse1_rgmii1g_pci_info) }, ++ { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, ++ &ehl_pse1_sgmii1g_pci_info) }, + { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_pci_info) }, + {} + }; +-- +2.16.4 + diff --git a/patches.suse/net-stmmac-add-EHL-RGMII-1Gbps-PCI-info-and-PCI-ID.patch b/patches.suse/net-stmmac-add-EHL-RGMII-1Gbps-PCI-info-and-PCI-ID.patch new file mode 100644 index 0000000..3032bda --- /dev/null +++ b/patches.suse/net-stmmac-add-EHL-RGMII-1Gbps-PCI-info-and-PCI-ID.patch @@ -0,0 +1,62 @@ +From 362431e62e73db430b7f32688920b2217770452b Mon Sep 17 00:00:00 2001 +From: Voon Weifeng +Date: Tue, 27 Aug 2019 09:38:10 +0800 +Subject: [PATCH 3/8] net: stmmac: add EHL RGMII 1Gbps PCI info and PCI ID +Git-commit: f6256585fecc9b9d2f0a335a92e864ccae98ea24 +Patch-mainline: v5.4-rc1 +References: bsc#1192691 + +Added EHL RGMII 1Gbps PCI ID. Different MII and speed will have +different PCI ID. + +Signed-off-by: Voon Weifeng +Signed-off-by: Ong Boon Leong +Signed-off-by: David S. Miller +Signed-off-by: Denis Kirjanov +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +index a81ae8095cdb..f5e075c8379b 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +@@ -213,6 +213,19 @@ static struct stmmac_pci_info ehl_sgmii1g_pci_info = { + .setup = ehl_sgmii_data, + }; + ++static int ehl_rgmii_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ plat->bus_id = 1; ++ plat->phy_addr = 0; ++ plat->interface = PHY_INTERFACE_MODE_RGMII; ++ return ehl_common_data(pdev, plat); ++} ++ ++static struct stmmac_pci_info ehl_rgmii1g_pci_info = { ++ .setup = ehl_rgmii_data, ++}; ++ + static int tgl_common_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) + { +@@ -481,6 +494,7 @@ static SIMPLE_DEV_PM_OPS(stmmac_pm_ops, stmmac_pci_suspend, stmmac_pci_resume); + + #define STMMAC_QUARK_ID 0x0937 + #define STMMAC_DEVICE_ID 0x1108 ++#define STMMAC_EHL_RGMII1G_ID 0x4b30 + #define STMMAC_EHL_SGMII1G_ID 0x4b31 + #define STMMAC_TGL_SGMII1G_ID 0xa0ac + +@@ -493,6 +507,7 @@ static const struct pci_device_id stmmac_id_table[] = { + STMMAC_DEVICE(STMMAC, STMMAC_DEVICE_ID, stmmac_pci_info), + STMMAC_DEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_MAC, stmmac_pci_info), + STMMAC_DEVICE(INTEL, STMMAC_QUARK_ID, quark_pci_info), ++ STMMAC_DEVICE(INTEL, STMMAC_EHL_RGMII1G_ID, ehl_rgmii1g_pci_info), + STMMAC_DEVICE(INTEL, STMMAC_EHL_SGMII1G_ID, ehl_sgmii1g_pci_info), + STMMAC_DEVICE(INTEL, STMMAC_TGL_SGMII1G_ID, tgl_sgmii1g_pci_info), + {} +-- +2.16.4 + diff --git a/patches.suse/net-stmmac-add-EHL-SGMII-1Gbps-PCI-info-and-PCI-ID.patch b/patches.suse/net-stmmac-add-EHL-SGMII-1Gbps-PCI-info-and-PCI-ID.patch new file mode 100644 index 0000000..f51170b --- /dev/null +++ b/patches.suse/net-stmmac-add-EHL-SGMII-1Gbps-PCI-info-and-PCI-ID.patch @@ -0,0 +1,154 @@ +From 94a6ba897ca42edf674828cbcab69b17a53bf524 Mon Sep 17 00:00:00 2001 +From: Voon Weifeng +Date: Tue, 27 Aug 2019 09:38:08 +0800 +Subject: [PATCH 1/8] net: stmmac: add EHL SGMII 1Gbps PCI info and PCI ID +Git-commit: 99122836d26a366847f92f9a211602a44a038c61 +Patch-mainline: v5.4-rc1 +References: bsc#1192691 + +Added EHL SGMII 1Gbps PCI ID. Different MII and speed will have +different PCI ID. + +Signed-off-by: Voon Weifeng +Signed-off-by: Ong Boon Leong +Signed-off-by: David S. Miller +Signed-off-by: Denis Kirjanov +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 107 +++++++++++++++++++++++ + 1 file changed, 107 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +index 3ffbdf4f5f1c..927a25953289 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +@@ -108,6 +108,111 @@ static const struct stmmac_pci_info stmmac_pci_info = { + .setup = stmmac_default_data, + }; + ++static int intel_mgbe_common_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ int i; ++ ++ plat->clk_csr = 5; ++ plat->has_gmac = 0; ++ plat->has_gmac4 = 1; ++ plat->force_sf_dma_mode = 0; ++ plat->tso_en = 1; ++ ++ plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; ++ ++ for (i = 0; i < plat->rx_queues_to_use; i++) { ++ plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; ++ plat->rx_queues_cfg[i].chan = i; ++ ++ /* Disable Priority config by default */ ++ plat->rx_queues_cfg[i].use_prio = false; ++ ++ /* Disable RX queues routing by default */ ++ plat->rx_queues_cfg[i].pkt_route = 0x0; ++ } ++ ++ for (i = 0; i < plat->tx_queues_to_use; i++) { ++ plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; ++ ++ /* Disable Priority config by default */ ++ plat->tx_queues_cfg[i].use_prio = false; ++ } ++ ++ /* FIFO size is 4096 bytes for 1 tx/rx queue */ ++ plat->tx_fifo_size = plat->tx_queues_to_use * 4096; ++ plat->rx_fifo_size = plat->rx_queues_to_use * 4096; ++ ++ plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; ++ plat->tx_queues_cfg[0].weight = 0x09; ++ plat->tx_queues_cfg[1].weight = 0x0A; ++ plat->tx_queues_cfg[2].weight = 0x0B; ++ plat->tx_queues_cfg[3].weight = 0x0C; ++ plat->tx_queues_cfg[4].weight = 0x0D; ++ plat->tx_queues_cfg[5].weight = 0x0E; ++ plat->tx_queues_cfg[6].weight = 0x0F; ++ plat->tx_queues_cfg[7].weight = 0x10; ++ ++ plat->mdio_bus_data->phy_mask = 0; ++ ++ plat->dma_cfg->pbl = 32; ++ plat->dma_cfg->pblx8 = true; ++ plat->dma_cfg->fixed_burst = 0; ++ plat->dma_cfg->mixed_burst = 0; ++ plat->dma_cfg->aal = 0; ++ ++ plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), ++ GFP_KERNEL); ++ if (!plat->axi) ++ return -ENOMEM; ++ ++ plat->axi->axi_lpi_en = 0; ++ plat->axi->axi_xit_frm = 0; ++ plat->axi->axi_wr_osr_lmt = 1; ++ plat->axi->axi_rd_osr_lmt = 1; ++ plat->axi->axi_blen[0] = 4; ++ plat->axi->axi_blen[1] = 8; ++ plat->axi->axi_blen[2] = 16; ++ ++ /* Set default value for multicast hash bins */ ++ plat->multicast_filter_bins = HASH_TABLE_SIZE; ++ ++ /* Set default value for unicast filter entries */ ++ plat->unicast_filter_entries = 1; ++ ++ /* Set the maxmtu to a default of JUMBO_LEN */ ++ plat->maxmtu = JUMBO_LEN; ++ ++ return 0; ++} ++ ++static int ehl_common_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ int ret; ++ ++ plat->rx_queues_to_use = 8; ++ plat->tx_queues_to_use = 8; ++ ret = intel_mgbe_common_data(pdev, plat); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int ehl_sgmii_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ plat->bus_id = 1; ++ plat->phy_addr = 0; ++ plat->interface = PHY_INTERFACE_MODE_SGMII; ++ return ehl_common_data(pdev, plat); ++} ++ ++static struct stmmac_pci_info ehl_sgmii1g_pci_info = { ++ .setup = ehl_sgmii_data, ++}; ++ + static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { + { + .func = 6, +@@ -349,6 +454,7 @@ static SIMPLE_DEV_PM_OPS(stmmac_pm_ops, stmmac_pci_suspend, stmmac_pci_resume); + + #define STMMAC_QUARK_ID 0x0937 + #define STMMAC_DEVICE_ID 0x1108 ++#define STMMAC_EHL_SGMII1G_ID 0x4b31 + + #define STMMAC_DEVICE(vendor_id, dev_id, info) { \ + PCI_VDEVICE(vendor_id, dev_id), \ +@@ -359,6 +465,7 @@ static const struct pci_device_id stmmac_id_table[] = { + STMMAC_DEVICE(STMMAC, STMMAC_DEVICE_ID, stmmac_pci_info), + STMMAC_DEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_MAC, stmmac_pci_info), + STMMAC_DEVICE(INTEL, STMMAC_QUARK_ID, quark_pci_info), ++ STMMAC_DEVICE(INTEL, STMMAC_EHL_SGMII1G_ID, ehl_sgmii1g_pci_info), + {} + }; + +-- +2.16.4 + diff --git a/patches.suse/net-stmmac-add-TGL-SGMII-1Gbps-PCI-info-and-PCI-ID.patch b/patches.suse/net-stmmac-add-TGL-SGMII-1Gbps-PCI-info-and-PCI-ID.patch new file mode 100644 index 0000000..b1210b3 --- /dev/null +++ b/patches.suse/net-stmmac-add-TGL-SGMII-1Gbps-PCI-info-and-PCI-ID.patch @@ -0,0 +1,76 @@ +From 2f1ee484893047f0a8470269b2e4b464c96acd57 Mon Sep 17 00:00:00 2001 +From: Voon Weifeng +Date: Tue, 27 Aug 2019 09:38:09 +0800 +Subject: [PATCH 2/8] net: stmmac: add TGL SGMII 1Gbps PCI info and PCI ID +Git-commit: e125dcef755612efa4f057dd7955cd8edd3fadb1 +Patch-mainline: v5.4-rc1 +References: bsc#1192691 + +Added TGL SGMII 1Gbps PCI ID. Different MII and speed will have +different PCI ID. + +Signed-off-by: Voon Weifeng +Signed-off-by: Ong Boon Leong +Signed-off-by: David S. Miller +Signed-off-by: Denis Kirjanov +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 29 ++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +index 927a25953289..a81ae8095cdb 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +@@ -213,6 +213,33 @@ static struct stmmac_pci_info ehl_sgmii1g_pci_info = { + .setup = ehl_sgmii_data, + }; + ++static int tgl_common_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ int ret; ++ ++ plat->rx_queues_to_use = 6; ++ plat->tx_queues_to_use = 4; ++ ret = intel_mgbe_common_data(pdev, plat); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int tgl_sgmii_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ plat->bus_id = 1; ++ plat->phy_addr = 0; ++ plat->interface = PHY_INTERFACE_MODE_SGMII; ++ return tgl_common_data(pdev, plat); ++} ++ ++static struct stmmac_pci_info tgl_sgmii1g_pci_info = { ++ .setup = tgl_sgmii_data, ++}; ++ + static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { + { + .func = 6, +@@ -455,6 +482,7 @@ static SIMPLE_DEV_PM_OPS(stmmac_pm_ops, stmmac_pci_suspend, stmmac_pci_resume); + #define STMMAC_QUARK_ID 0x0937 + #define STMMAC_DEVICE_ID 0x1108 + #define STMMAC_EHL_SGMII1G_ID 0x4b31 ++#define STMMAC_TGL_SGMII1G_ID 0xa0ac + + #define STMMAC_DEVICE(vendor_id, dev_id, info) { \ + PCI_VDEVICE(vendor_id, dev_id), \ +@@ -466,6 +494,7 @@ static const struct pci_device_id stmmac_id_table[] = { + STMMAC_DEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_MAC, stmmac_pci_info), + STMMAC_DEVICE(INTEL, STMMAC_QUARK_ID, quark_pci_info), + STMMAC_DEVICE(INTEL, STMMAC_EHL_SGMII1G_ID, ehl_sgmii1g_pci_info), ++ STMMAC_DEVICE(INTEL, STMMAC_TGL_SGMII1G_ID, tgl_sgmii1g_pci_info), + {} + }; + +-- +2.16.4 + diff --git a/patches.suse/net-stmmac-create-dwmac-intel.c-to-contain-all-Intel.patch b/patches.suse/net-stmmac-create-dwmac-intel.c-to-contain-all-Intel.patch new file mode 100644 index 0000000..7c1094d --- /dev/null +++ b/patches.suse/net-stmmac-create-dwmac-intel.c-to-contain-all-Intel.patch @@ -0,0 +1,922 @@ +From 8fd03f9541c032d36c9d0836f23ac558bf3a7301 Mon Sep 17 00:00:00 2001 +From: Voon Weifeng +Date: Tue, 31 Mar 2020 01:05:10 +0800 +Subject: [PATCH 5/8] net: stmmac: create dwmac-intel.c to contain all Intel + platform +Git-commit: 58da0cfa6cf1200b81b65aef36dfa6130b577ef6 +Patch-mainline: v5.7-rc1 +References: bsc#1192691 + +As stmmac_pci.c file is getting bigger and more complex, it is reasonable +to separate all the Intel specific dwmac pci device to a different file. +This move includes Intel Quark, TGL and EHL. A new kernel config +CONFIG_DWMAC_INTEL is introduced and depends on X86. For this initial +patch, all the necessary function such as probe() and exit() are identical +besides the function name. + +Signed-off-by: Voon Weifeng +Signed-off-by: David S. Miller +Signed-off-by: Denis Kirjanov +--- + drivers/net/ethernet/stmicro/stmmac/Kconfig | 9 + + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + + drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 507 ++++++++++++++++++++++ + drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 317 +------------- + 4 files changed, 524 insertions(+), 310 deletions(-) + create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c + +diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig +index 2325b40dff6e..0f8a0d0e6362 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig ++++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig +@@ -197,6 +197,15 @@ config DWMAC_SUN8I + EMAC ethernet controller. + endif + ++config DWMAC_INTEL ++ tristate "Intel GMAC support" ++ default X86 ++ depends on X86 && STMMAC_ETH && PCI ++ depends on COMMON_CLK ++ ---help--- ++ This selects the Intel platform specific bus support for the ++ stmmac driver. This driver is used for Intel Quark/EHL/TGL. ++ + config STMMAC_PCI + tristate "STMMAC PCI bus support" + depends on STMMAC_ETH && PCI +diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile +index c59926d96bcc..5a6f265bc540 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Makefile ++++ b/drivers/net/ethernet/stmicro/stmmac/Makefile +@@ -30,5 +30,6 @@ obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o + stmmac-platform-objs:= stmmac_platform.o + dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o + ++obj-$(CONFIG_DWMAC_INTEL) += dwmac-intel.o + obj-$(CONFIG_STMMAC_PCI) += stmmac-pci.o + stmmac-pci-objs:= stmmac_pci.o +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +new file mode 100644 +index 000000000000..ade17cfc9fa1 +--- /dev/null ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +@@ -0,0 +1,507 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Copyright (c) 2020, Intel Corporation ++ */ ++ ++#include ++#include ++#include ++#include "stmmac.h" ++ ++/* This struct is used to associate PCI Function of MAC controller on a board, ++ * discovered via DMI, with the address of PHY connected to the MAC. The ++ * negative value of the address means that MAC controller is not connected ++ * with PHY. ++ */ ++struct stmmac_pci_func_data { ++ unsigned int func; ++ int phy_addr; ++}; ++ ++struct stmmac_pci_dmi_data { ++ const struct stmmac_pci_func_data *func; ++ size_t nfuncs; ++}; ++ ++struct stmmac_pci_info { ++ int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); ++}; ++ ++static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, ++ const struct dmi_system_id *dmi_list) ++{ ++ const struct stmmac_pci_func_data *func_data; ++ const struct stmmac_pci_dmi_data *dmi_data; ++ const struct dmi_system_id *dmi_id; ++ int func = PCI_FUNC(pdev->devfn); ++ size_t n; ++ ++ dmi_id = dmi_first_match(dmi_list); ++ if (!dmi_id) ++ return -ENODEV; ++ ++ dmi_data = dmi_id->driver_data; ++ func_data = dmi_data->func; ++ ++ for (n = 0; n < dmi_data->nfuncs; n++, func_data++) ++ if (func_data->func == func) ++ return func_data->phy_addr; ++ ++ return -ENODEV; ++} ++ ++static void common_default_data(struct plat_stmmacenet_data *plat) ++{ ++ plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ ++ plat->has_gmac = 1; ++ plat->force_sf_dma_mode = 1; ++ ++ plat->mdio_bus_data->needs_reset = true; ++ ++ /* Set default value for multicast hash bins */ ++ plat->multicast_filter_bins = HASH_TABLE_SIZE; ++ ++ /* Set default value for unicast filter entries */ ++ plat->unicast_filter_entries = 1; ++ ++ /* Set the maxmtu to a default of JUMBO_LEN */ ++ plat->maxmtu = JUMBO_LEN; ++ ++ /* Set default number of RX and TX queues to use */ ++ plat->tx_queues_to_use = 1; ++ plat->rx_queues_to_use = 1; ++ ++ /* Disable Priority config by default */ ++ plat->tx_queues_cfg[0].use_prio = false; ++ plat->rx_queues_cfg[0].use_prio = false; ++ ++ /* Disable RX queues routing by default */ ++ plat->rx_queues_cfg[0].pkt_route = 0x0; ++} ++ ++static int intel_mgbe_common_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ int i; ++ ++ plat->clk_csr = 5; ++ plat->has_gmac = 0; ++ plat->has_gmac4 = 1; ++ plat->force_sf_dma_mode = 0; ++ plat->tso_en = 1; ++ ++ plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; ++ ++ for (i = 0; i < plat->rx_queues_to_use; i++) { ++ plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; ++ plat->rx_queues_cfg[i].chan = i; ++ ++ /* Disable Priority config by default */ ++ plat->rx_queues_cfg[i].use_prio = false; ++ ++ /* Disable RX queues routing by default */ ++ plat->rx_queues_cfg[i].pkt_route = 0x0; ++ } ++ ++ for (i = 0; i < plat->tx_queues_to_use; i++) { ++ plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; ++ ++ /* Disable Priority config by default */ ++ plat->tx_queues_cfg[i].use_prio = false; ++ } ++ ++ /* FIFO size is 4096 bytes for 1 tx/rx queue */ ++ plat->tx_fifo_size = plat->tx_queues_to_use * 4096; ++ plat->rx_fifo_size = plat->rx_queues_to_use * 4096; ++ ++ plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; ++ plat->tx_queues_cfg[0].weight = 0x09; ++ plat->tx_queues_cfg[1].weight = 0x0A; ++ plat->tx_queues_cfg[2].weight = 0x0B; ++ plat->tx_queues_cfg[3].weight = 0x0C; ++ plat->tx_queues_cfg[4].weight = 0x0D; ++ plat->tx_queues_cfg[5].weight = 0x0E; ++ plat->tx_queues_cfg[6].weight = 0x0F; ++ plat->tx_queues_cfg[7].weight = 0x10; ++ ++ plat->dma_cfg->pbl = 32; ++ plat->dma_cfg->pblx8 = true; ++ plat->dma_cfg->fixed_burst = 0; ++ plat->dma_cfg->mixed_burst = 0; ++ plat->dma_cfg->aal = 0; ++ ++ plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), ++ GFP_KERNEL); ++ if (!plat->axi) ++ return -ENOMEM; ++ ++ plat->axi->axi_lpi_en = 0; ++ plat->axi->axi_xit_frm = 0; ++ plat->axi->axi_wr_osr_lmt = 1; ++ plat->axi->axi_rd_osr_lmt = 1; ++ plat->axi->axi_blen[0] = 4; ++ plat->axi->axi_blen[1] = 8; ++ plat->axi->axi_blen[2] = 16; ++ ++ /* Set system clock */ ++ plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, ++ "stmmac-clk", NULL, 0, ++ plat->clk_ptp_rate); ++ ++ if (IS_ERR(plat->stmmac_clk)) { ++ dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); ++ plat->stmmac_clk = NULL; ++ } ++ clk_prepare_enable(plat->stmmac_clk); ++ ++ /* Set default value for multicast hash bins */ ++ plat->multicast_filter_bins = HASH_TABLE_SIZE; ++ ++ /* Set default value for unicast filter entries */ ++ plat->unicast_filter_entries = 1; ++ ++ /* Set the maxmtu to a default of JUMBO_LEN */ ++ plat->maxmtu = JUMBO_LEN; ++ ++ return 0; ++} ++ ++static int ehl_common_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ int ret; ++ ++ plat->rx_queues_to_use = 8; ++ plat->tx_queues_to_use = 8; ++ plat->clk_ptp_rate = 200000000; ++ ret = intel_mgbe_common_data(pdev, plat); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int ehl_sgmii_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ plat->bus_id = 1; ++ plat->phy_addr = 0; ++ plat->phy_interface = PHY_INTERFACE_MODE_SGMII; ++ ++ return ehl_common_data(pdev, plat); ++} ++ ++static struct stmmac_pci_info ehl_sgmii1g_pci_info = { ++ .setup = ehl_sgmii_data, ++}; ++ ++static int ehl_rgmii_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ plat->bus_id = 1; ++ plat->phy_addr = 0; ++ plat->phy_interface = PHY_INTERFACE_MODE_RGMII; ++ ++ return ehl_common_data(pdev, plat); ++} ++ ++static struct stmmac_pci_info ehl_rgmii1g_pci_info = { ++ .setup = ehl_rgmii_data, ++}; ++ ++static int tgl_common_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ int ret; ++ ++ plat->rx_queues_to_use = 6; ++ plat->tx_queues_to_use = 4; ++ plat->clk_ptp_rate = 200000000; ++ ret = intel_mgbe_common_data(pdev, plat); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int tgl_sgmii_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ plat->bus_id = 1; ++ plat->phy_addr = 0; ++ plat->phy_interface = PHY_INTERFACE_MODE_SGMII; ++ return tgl_common_data(pdev, plat); ++} ++ ++static struct stmmac_pci_info tgl_sgmii1g_pci_info = { ++ .setup = tgl_sgmii_data, ++}; ++ ++static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { ++ { ++ .func = 6, ++ .phy_addr = 1, ++ }, ++}; ++ ++static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { ++ .func = galileo_stmmac_func_data, ++ .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), ++}; ++ ++static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { ++ { ++ .func = 6, ++ .phy_addr = 1, ++ }, ++ { ++ .func = 7, ++ .phy_addr = 1, ++ }, ++}; ++ ++static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { ++ .func = iot2040_stmmac_func_data, ++ .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), ++}; ++ ++static const struct dmi_system_id quark_pci_dmi[] = { ++ { ++ .matches = { ++ DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), ++ }, ++ .driver_data = (void *)&galileo_stmmac_dmi_data, ++ }, ++ { ++ .matches = { ++ DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), ++ }, ++ .driver_data = (void *)&galileo_stmmac_dmi_data, ++ }, ++ /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. ++ * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which ++ * has only one pci network device while other asset tags are ++ * for IOT2040 which has two. ++ */ ++ { ++ .matches = { ++ DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), ++ DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, ++ "6ES7647-0AA00-0YA2"), ++ }, ++ .driver_data = (void *)&galileo_stmmac_dmi_data, ++ }, ++ { ++ .matches = { ++ DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), ++ }, ++ .driver_data = (void *)&iot2040_stmmac_dmi_data, ++ }, ++ {} ++}; ++ ++static int quark_default_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ int ret; ++ ++ /* Set common default data first */ ++ common_default_data(plat); ++ ++ /* Refuse to load the driver and register net device if MAC controller ++ * does not connect to any PHY interface. ++ */ ++ ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); ++ if (ret < 0) { ++ /* Return error to the caller on DMI enabled boards. */ ++ if (dmi_get_system_info(DMI_BOARD_NAME)) ++ return ret; ++ ++ /* Galileo boards with old firmware don't support DMI. We always ++ * use 1 here as PHY address, so at least the first found MAC ++ * controller would be probed. ++ */ ++ ret = 1; ++ } ++ ++ plat->bus_id = pci_dev_id(pdev); ++ plat->phy_addr = ret; ++ plat->phy_interface = PHY_INTERFACE_MODE_RMII; ++ ++ plat->dma_cfg->pbl = 16; ++ plat->dma_cfg->pblx8 = true; ++ plat->dma_cfg->fixed_burst = 1; ++ /* AXI (TODO) */ ++ ++ return 0; ++} ++ ++static const struct stmmac_pci_info quark_pci_info = { ++ .setup = quark_default_data, ++}; ++ ++/** ++ * intel_eth_pci_probe ++ * ++ * @pdev: pci device pointer ++ * @id: pointer to table of device id/id's. ++ * ++ * Description: This probing function gets called for all PCI devices which ++ * match the ID table and are not "owned" by other driver yet. This function ++ * gets passed a "struct pci_dev *" for each device whose entry in the ID table ++ * matches the device. The probe functions returns zero when the driver choose ++ * to take "ownership" of the device or an error code(-ve no) otherwise. ++ */ ++static int intel_eth_pci_probe(struct pci_dev *pdev, ++ const struct pci_device_id *id) ++{ ++ struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; ++ struct plat_stmmacenet_data *plat; ++ struct stmmac_resources res; ++ int i; ++ int ret; ++ ++ plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); ++ if (!plat) ++ return -ENOMEM; ++ ++ plat->mdio_bus_data = devm_kzalloc(&pdev->dev, ++ sizeof(*plat->mdio_bus_data), ++ GFP_KERNEL); ++ if (!plat->mdio_bus_data) ++ return -ENOMEM; ++ ++ plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), ++ GFP_KERNEL); ++ if (!plat->dma_cfg) ++ return -ENOMEM; ++ ++ /* Enable pci device */ ++ ret = pci_enable_device(pdev); ++ if (ret) { ++ dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", ++ __func__); ++ return ret; ++ } ++ ++ /* Get the base address of device */ ++ for (i = 0; i < PCI_STD_NUM_BARS; i++) { ++ if (pci_resource_len(pdev, i) == 0) ++ continue; ++ ret = pcim_iomap_regions(pdev, BIT(i), pci_name(pdev)); ++ if (ret) ++ return ret; ++ break; ++ } ++ ++ pci_set_master(pdev); ++ ++ ret = info->setup(pdev, plat); ++ if (ret) ++ return ret; ++ ++ pci_enable_msi(pdev); ++ ++ memset(&res, 0, sizeof(res)); ++ res.addr = pcim_iomap_table(pdev)[i]; ++ res.wol_irq = pdev->irq; ++ res.irq = pdev->irq; ++ ++ return stmmac_dvr_probe(&pdev->dev, plat, &res); ++} ++ ++/** ++ * intel_eth_pci_remove ++ * ++ * @pdev: platform device pointer ++ * Description: this function calls the main to free the net resources ++ * and releases the PCI resources. ++ */ ++static void intel_eth_pci_remove(struct pci_dev *pdev) ++{ ++ struct net_device *ndev = dev_get_drvdata(&pdev->dev); ++ struct stmmac_priv *priv = netdev_priv(ndev); ++ int i; ++ ++ stmmac_dvr_remove(&pdev->dev); ++ ++ if (priv->plat->stmmac_clk) ++ clk_unregister_fixed_rate(priv->plat->stmmac_clk); ++ ++ for (i = 0; i < PCI_STD_NUM_BARS; i++) { ++ if (pci_resource_len(pdev, i) == 0) ++ continue; ++ pcim_iounmap_regions(pdev, BIT(i)); ++ break; ++ } ++ ++ pci_disable_device(pdev); ++} ++ ++static int __maybe_unused intel_eth_pci_suspend(struct device *dev) ++{ ++ struct pci_dev *pdev = to_pci_dev(dev); ++ int ret; ++ ++ ret = stmmac_suspend(dev); ++ if (ret) ++ return ret; ++ ++ ret = pci_save_state(pdev); ++ if (ret) ++ return ret; ++ ++ pci_disable_device(pdev); ++ pci_wake_from_d3(pdev, true); ++ return 0; ++} ++ ++static int __maybe_unused intel_eth_pci_resume(struct device *dev) ++{ ++ struct pci_dev *pdev = to_pci_dev(dev); ++ int ret; ++ ++ pci_restore_state(pdev); ++ pci_set_power_state(pdev, PCI_D0); ++ ++ ret = pci_enable_device(pdev); ++ if (ret) ++ return ret; ++ ++ pci_set_master(pdev); ++ ++ return stmmac_resume(dev); ++} ++ ++static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, ++ intel_eth_pci_resume); ++ ++#define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937 ++#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30 ++#define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31 ++#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac ++ ++static const struct pci_device_id intel_eth_pci_id_table[] = { ++ { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_pci_info) }, ++ { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_pci_info) }, ++ { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_pci_info) }, ++ { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_pci_info) }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); ++ ++static struct pci_driver intel_eth_pci_driver = { ++ .name = "intel-eth-pci", ++ .id_table = intel_eth_pci_id_table, ++ .probe = intel_eth_pci_probe, ++ .remove = intel_eth_pci_remove, ++ .driver = { ++ .pm = &intel_eth_pm_ops, ++ }, ++}; ++ ++module_pci_driver(intel_eth_pci_driver); ++ ++MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver"); ++MODULE_AUTHOR("Voon Weifeng "); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +index b8c2489e4e23..a7a08c7f05d7 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +@@ -14,49 +14,10 @@ + + #include "stmmac.h" + +-/* +- * This struct is used to associate PCI Function of MAC controller on a board, +- * discovered via DMI, with the address of PHY connected to the MAC. The +- * negative value of the address means that MAC controller is not connected +- * with PHY. +- */ +-struct stmmac_pci_func_data { +- unsigned int func; +- int phy_addr; +-}; +- +-struct stmmac_pci_dmi_data { +- const struct stmmac_pci_func_data *func; +- size_t nfuncs; +-}; +- + struct stmmac_pci_info { + int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); + }; + +-static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, +- const struct dmi_system_id *dmi_list) +-{ +- const struct stmmac_pci_func_data *func_data; +- const struct stmmac_pci_dmi_data *dmi_data; +- const struct dmi_system_id *dmi_id; +- int func = PCI_FUNC(pdev->devfn); +- size_t n; +- +- dmi_id = dmi_first_match(dmi_list); +- if (!dmi_id) +- return -ENODEV; +- +- dmi_data = dmi_id->driver_data; +- func_data = dmi_data->func; +- +- for (n = 0; n < dmi_data->nfuncs; n++, func_data++) +- if (func_data->func == func) +- return func_data->phy_addr; +- +- return -ENODEV; +-} +- + static void common_default_data(struct plat_stmmacenet_data *plat) + { + plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ +@@ -108,257 +69,6 @@ static const struct stmmac_pci_info stmmac_pci_info = { + .setup = stmmac_default_data, + }; + +-static int intel_mgbe_common_data(struct pci_dev *pdev, +- struct plat_stmmacenet_data *plat) +-{ +- int i; +- +- plat->clk_csr = 5; +- plat->has_gmac = 0; +- plat->has_gmac4 = 1; +- plat->force_sf_dma_mode = 0; +- plat->tso_en = 1; +- +- plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; +- +- for (i = 0; i < plat->rx_queues_to_use; i++) { +- plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; +- plat->rx_queues_cfg[i].chan = i; +- +- /* Disable Priority config by default */ +- plat->rx_queues_cfg[i].use_prio = false; +- +- /* Disable RX queues routing by default */ +- plat->rx_queues_cfg[i].pkt_route = 0x0; +- } +- +- for (i = 0; i < plat->tx_queues_to_use; i++) { +- plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; +- +- /* Disable Priority config by default */ +- plat->tx_queues_cfg[i].use_prio = false; +- } +- +- /* FIFO size is 4096 bytes for 1 tx/rx queue */ +- plat->tx_fifo_size = plat->tx_queues_to_use * 4096; +- plat->rx_fifo_size = plat->rx_queues_to_use * 4096; +- +- plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; +- plat->tx_queues_cfg[0].weight = 0x09; +- plat->tx_queues_cfg[1].weight = 0x0A; +- plat->tx_queues_cfg[2].weight = 0x0B; +- plat->tx_queues_cfg[3].weight = 0x0C; +- plat->tx_queues_cfg[4].weight = 0x0D; +- plat->tx_queues_cfg[5].weight = 0x0E; +- plat->tx_queues_cfg[6].weight = 0x0F; +- plat->tx_queues_cfg[7].weight = 0x10; +- +- plat->mdio_bus_data->phy_mask = 0; +- +- plat->dma_cfg->pbl = 32; +- plat->dma_cfg->pblx8 = true; +- plat->dma_cfg->fixed_burst = 0; +- plat->dma_cfg->mixed_burst = 0; +- plat->dma_cfg->aal = 0; +- +- plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), +- GFP_KERNEL); +- if (!plat->axi) +- return -ENOMEM; +- +- plat->axi->axi_lpi_en = 0; +- plat->axi->axi_xit_frm = 0; +- plat->axi->axi_wr_osr_lmt = 1; +- plat->axi->axi_rd_osr_lmt = 1; +- plat->axi->axi_blen[0] = 4; +- plat->axi->axi_blen[1] = 8; +- plat->axi->axi_blen[2] = 16; +- +- /* Set default value for multicast hash bins */ +- plat->multicast_filter_bins = HASH_TABLE_SIZE; +- +- /* Set default value for unicast filter entries */ +- plat->unicast_filter_entries = 1; +- +- /* Set the maxmtu to a default of JUMBO_LEN */ +- plat->maxmtu = JUMBO_LEN; +- +- return 0; +-} +- +-static int ehl_common_data(struct pci_dev *pdev, +- struct plat_stmmacenet_data *plat) +-{ +- int ret; +- +- plat->rx_queues_to_use = 8; +- plat->tx_queues_to_use = 8; +- ret = intel_mgbe_common_data(pdev, plat); +- if (ret) +- return ret; +- +- return 0; +-} +- +-static int ehl_sgmii_data(struct pci_dev *pdev, +- struct plat_stmmacenet_data *plat) +-{ +- plat->bus_id = 1; +- plat->phy_addr = 0; +- plat->interface = PHY_INTERFACE_MODE_SGMII; +- return ehl_common_data(pdev, plat); +-} +- +-static struct stmmac_pci_info ehl_sgmii1g_pci_info = { +- .setup = ehl_sgmii_data, +-}; +- +-static int ehl_rgmii_data(struct pci_dev *pdev, +- struct plat_stmmacenet_data *plat) +-{ +- plat->bus_id = 1; +- plat->phy_addr = 0; +- plat->interface = PHY_INTERFACE_MODE_RGMII; +- return ehl_common_data(pdev, plat); +-} +- +-static struct stmmac_pci_info ehl_rgmii1g_pci_info = { +- .setup = ehl_rgmii_data, +-}; +- +-static int tgl_common_data(struct pci_dev *pdev, +- struct plat_stmmacenet_data *plat) +-{ +- int ret; +- +- plat->rx_queues_to_use = 6; +- plat->tx_queues_to_use = 4; +- ret = intel_mgbe_common_data(pdev, plat); +- if (ret) +- return ret; +- +- return 0; +-} +- +-static int tgl_sgmii_data(struct pci_dev *pdev, +- struct plat_stmmacenet_data *plat) +-{ +- plat->bus_id = 1; +- plat->phy_addr = 0; +- plat->interface = PHY_INTERFACE_MODE_SGMII; +- return tgl_common_data(pdev, plat); +-} +- +-static struct stmmac_pci_info tgl_sgmii1g_pci_info = { +- .setup = tgl_sgmii_data, +-}; +- +-static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { +- { +- .func = 6, +- .phy_addr = 1, +- }, +-}; +- +-static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { +- .func = galileo_stmmac_func_data, +- .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), +-}; +- +-static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { +- { +- .func = 6, +- .phy_addr = 1, +- }, +- { +- .func = 7, +- .phy_addr = 1, +- }, +-}; +- +-static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { +- .func = iot2040_stmmac_func_data, +- .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), +-}; +- +-static const struct dmi_system_id quark_pci_dmi[] = { +- { +- .matches = { +- DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), +- }, +- .driver_data = (void *)&galileo_stmmac_dmi_data, +- }, +- { +- .matches = { +- DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), +- }, +- .driver_data = (void *)&galileo_stmmac_dmi_data, +- }, +- /* +- * There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. +- * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which +- * has only one pci network device while other asset tags are +- * for IOT2040 which has two. +- */ +- { +- .matches = { +- DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), +- DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, +- "6ES7647-0AA00-0YA2"), +- }, +- .driver_data = (void *)&galileo_stmmac_dmi_data, +- }, +- { +- .matches = { +- DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), +- }, +- .driver_data = (void *)&iot2040_stmmac_dmi_data, +- }, +- {} +-}; +- +-static int quark_default_data(struct pci_dev *pdev, +- struct plat_stmmacenet_data *plat) +-{ +- int ret; +- +- /* Set common default data first */ +- common_default_data(plat); +- +- /* +- * Refuse to load the driver and register net device if MAC controller +- * does not connect to any PHY interface. +- */ +- ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); +- if (ret < 0) { +- /* Return error to the caller on DMI enabled boards. */ +- if (dmi_get_system_info(DMI_BOARD_NAME)) +- return ret; +- +- /* +- * Galileo boards with old firmware don't support DMI. We always +- * use 1 here as PHY address, so at least the first found MAC +- * controller would be probed. +- */ +- ret = 1; +- } +- +- plat->bus_id = pci_dev_id(pdev); +- plat->phy_addr = ret; +- plat->phy_interface = PHY_INTERFACE_MODE_RMII; +- +- plat->dma_cfg->pbl = 16; +- plat->dma_cfg->pblx8 = true; +- plat->dma_cfg->fixed_burst = 1; +- /* AXI (TODO) */ +- +- return 0; +-} +- +-static const struct stmmac_pci_info quark_pci_info = { +- .setup = quark_default_data, +-}; +- + static int snps_gmac5_default_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) + { +@@ -559,28 +269,15 @@ static int __maybe_unused stmmac_pci_resume(struct device *dev) + static SIMPLE_DEV_PM_OPS(stmmac_pm_ops, stmmac_pci_suspend, stmmac_pci_resume); + + /* synthetic ID, no official vendor */ +-#define PCI_VENDOR_ID_STMMAC 0x700 +- +-#define STMMAC_QUARK_ID 0x0937 +-#define STMMAC_DEVICE_ID 0x1108 +-#define STMMAC_EHL_RGMII1G_ID 0x4b30 +-#define STMMAC_EHL_SGMII1G_ID 0x4b31 +-#define STMMAC_TGL_SGMII1G_ID 0xa0ac +-#define STMMAC_GMAC5_ID 0x7102 +- +-#define STMMAC_DEVICE(vendor_id, dev_id, info) { \ +- PCI_VDEVICE(vendor_id, dev_id), \ +- .driver_data = (kernel_ulong_t)&info \ +- } ++#define PCI_VENDOR_ID_STMMAC 0x0700 ++ ++#define PCI_DEVICE_ID_STMMAC_STMMAC 0x1108 ++#define PCI_DEVICE_ID_SYNOPSYS_GMAC5_ID 0x7102 + + static const struct pci_device_id stmmac_id_table[] = { +- STMMAC_DEVICE(STMMAC, STMMAC_DEVICE_ID, stmmac_pci_info), +- STMMAC_DEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_MAC, stmmac_pci_info), +- STMMAC_DEVICE(INTEL, STMMAC_QUARK_ID, quark_pci_info), +- STMMAC_DEVICE(INTEL, STMMAC_EHL_RGMII1G_ID, ehl_rgmii1g_pci_info), +- STMMAC_DEVICE(INTEL, STMMAC_EHL_SGMII1G_ID, ehl_sgmii1g_pci_info), +- STMMAC_DEVICE(INTEL, STMMAC_TGL_SGMII1G_ID, tgl_sgmii1g_pci_info), +- STMMAC_DEVICE(SYNOPSYS, STMMAC_GMAC5_ID, snps_gmac5_pci_info), ++ { PCI_DEVICE_DATA(STMMAC, STMMAC, &stmmac_pci_info) }, ++ { PCI_DEVICE_DATA(STMICRO, MAC, &stmmac_pci_info) }, ++ { PCI_DEVICE_DATA(SYNOPSYS, GMAC5_ID, &snps_gmac5_pci_info) }, + {} + }; + +-- +2.16.4 + diff --git a/patches.suse/net-stmmac-pci-Add-HAPS-support-using-GMAC5.patch b/patches.suse/net-stmmac-pci-Add-HAPS-support-using-GMAC5.patch new file mode 100644 index 0000000..a220a50 --- /dev/null +++ b/patches.suse/net-stmmac-pci-Add-HAPS-support-using-GMAC5.patch @@ -0,0 +1,116 @@ +From 6bcdedc607688f87e3ec7194de8651357cab5840 Mon Sep 17 00:00:00 2001 +From: Jose Abreu +Date: Mon, 9 Sep 2019 18:54:26 +0200 +Subject: [PATCH 4/8] net: stmmac: pci: Add HAPS support using GMAC5 +Git-commit: ebecb860ed2288868a0911f3af3c277641041b0d +Patch-mainline: v5.4-rc1 +References: bsc#1192691 + +Add the support for Synopsys HAPS board that uses GMAC5. + +Signed-off-by: Jose Abreu +Signed-off-by: David S. Miller +Signed-off-by: Denis Kirjanov +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 71 ++++++++++++++++++++++++ + 1 file changed, 71 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +index f5e075c8379b..b8c2489e4e23 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +@@ -359,6 +359,75 @@ static const struct stmmac_pci_info quark_pci_info = { + .setup = quark_default_data, + }; + ++static int snps_gmac5_default_data(struct pci_dev *pdev, ++ struct plat_stmmacenet_data *plat) ++{ ++ int i; ++ ++ plat->clk_csr = 5; ++ plat->has_gmac4 = 1; ++ plat->force_sf_dma_mode = 1; ++ plat->tso_en = 1; ++ plat->pmt = 1; ++ ++ plat->mdio_bus_data->phy_mask = 0; ++ ++ /* Set default value for multicast hash bins */ ++ plat->multicast_filter_bins = HASH_TABLE_SIZE; ++ ++ /* Set default value for unicast filter entries */ ++ plat->unicast_filter_entries = 1; ++ ++ /* Set the maxmtu to a default of JUMBO_LEN */ ++ plat->maxmtu = JUMBO_LEN; ++ ++ /* Set default number of RX and TX queues to use */ ++ plat->tx_queues_to_use = 4; ++ plat->rx_queues_to_use = 4; ++ ++ plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; ++ for (i = 0; i < plat->tx_queues_to_use; i++) { ++ plat->tx_queues_cfg[i].use_prio = false; ++ plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; ++ plat->tx_queues_cfg[i].weight = 25; ++ } ++ ++ plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; ++ for (i = 0; i < plat->rx_queues_to_use; i++) { ++ plat->rx_queues_cfg[i].use_prio = false; ++ plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; ++ plat->rx_queues_cfg[i].pkt_route = 0x0; ++ plat->rx_queues_cfg[i].chan = i; ++ } ++ ++ plat->bus_id = 1; ++ plat->phy_addr = -1; ++ plat->interface = PHY_INTERFACE_MODE_GMII; ++ ++ plat->dma_cfg->pbl = 32; ++ plat->dma_cfg->pblx8 = true; ++ ++ /* Axi Configuration */ ++ plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), GFP_KERNEL); ++ if (!plat->axi) ++ return -ENOMEM; ++ ++ plat->axi->axi_wr_osr_lmt = 31; ++ plat->axi->axi_rd_osr_lmt = 31; ++ ++ plat->axi->axi_fb = false; ++ plat->axi->axi_blen[0] = 4; ++ plat->axi->axi_blen[1] = 8; ++ plat->axi->axi_blen[2] = 16; ++ plat->axi->axi_blen[3] = 32; ++ ++ return 0; ++} ++ ++static const struct stmmac_pci_info snps_gmac5_pci_info = { ++ .setup = snps_gmac5_default_data, ++}; ++ + /** + * stmmac_pci_probe + * +@@ -497,6 +566,7 @@ static SIMPLE_DEV_PM_OPS(stmmac_pm_ops, stmmac_pci_suspend, stmmac_pci_resume); + #define STMMAC_EHL_RGMII1G_ID 0x4b30 + #define STMMAC_EHL_SGMII1G_ID 0x4b31 + #define STMMAC_TGL_SGMII1G_ID 0xa0ac ++#define STMMAC_GMAC5_ID 0x7102 + + #define STMMAC_DEVICE(vendor_id, dev_id, info) { \ + PCI_VDEVICE(vendor_id, dev_id), \ +@@ -510,6 +580,7 @@ static const struct pci_device_id stmmac_id_table[] = { + STMMAC_DEVICE(INTEL, STMMAC_EHL_RGMII1G_ID, ehl_rgmii1g_pci_info), + STMMAC_DEVICE(INTEL, STMMAC_EHL_SGMII1G_ID, ehl_sgmii1g_pci_info), + STMMAC_DEVICE(INTEL, STMMAC_TGL_SGMII1G_ID, tgl_sgmii1g_pci_info), ++ STMMAC_DEVICE(SYNOPSYS, STMMAC_GMAC5_ID, snps_gmac5_pci_info), + {} + }; + +-- +2.16.4 + diff --git a/patches.suse/pinctrl-pinctrl-rockchip-Fix-a-bunch-of-kerneldoc-mi.patch b/patches.suse/pinctrl-pinctrl-rockchip-Fix-a-bunch-of-kerneldoc-mi.patch new file mode 100644 index 0000000..e828886 --- /dev/null +++ b/patches.suse/pinctrl-pinctrl-rockchip-Fix-a-bunch-of-kerneldoc-mi.patch @@ -0,0 +1,153 @@ +From: Lee Jones +Date: Mon, 13 Jul 2020 15:49:24 +0100 +Subject: pinctrl: pinctrl-rockchip: Fix a bunch of kerneldoc misdemeanours + +Git-commit: e1524ea84af7172acc20827f8dca3fc8f72b8f37 +Patch-mainline: v5.9-rc1 +References: bsc#1192217 + +Demote headers which are clearly not kerneldoc, provide titles for +struct definition blocks, fix API slip (bitrot) misspellings and +provide some missing entries. + +Fixes the following W=1 kernel build warning(s): + + drivers/pinctrl/pinctrl-rockchip.c:82: warning: cannot understand function prototype: 'struct rockchip_iomux ' + drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_DEFAULT' not described in enum 'rockchip_pin_drv_type' + drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_1V8_OR_3V0' not described in enum 'rockchip_pin_drv_type' + drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_1V8_ONLY' not described in enum 'rockchip_pin_drv_type' + drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_1V8_3V0_AUTO' not described in enum 'rockchip_pin_drv_type' + drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_3V3_ONLY' not described in enum 'rockchip_pin_drv_type' + drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_MAX' not described in enum 'rockchip_pin_drv_type' + drivers/pinctrl/pinctrl-rockchip.c:106: warning: Enum value 'PULL_TYPE_IO_DEFAULT' not described in enum 'rockchip_pin_pull_type' + drivers/pinctrl/pinctrl-rockchip.c:106: warning: Enum value 'PULL_TYPE_IO_1V8_ONLY' not described in enum 'rockchip_pin_pull_type' + drivers/pinctrl/pinctrl-rockchip.c:106: warning: Enum value 'PULL_TYPE_MAX' not described in enum 'rockchip_pin_pull_type' + drivers/pinctrl/pinctrl-rockchip.c:109: warning: Cannot understand * @drv_type: drive strength variant using rockchip_perpin_drv_type + on line 109 - I thought it was a doc line + drivers/pinctrl/pinctrl-rockchip.c:122: warning: Cannot understand * @reg_base: register base of the gpio bank + on line 109 - I thought it was a doc line + drivers/pinctrl/pinctrl-rockchip.c:325: warning: Function parameter or member 'route_location' not described in 'rockchip_mux_route_data' + drivers/pinctrl/pinctrl-rockchip.c:328: warning: Cannot understand */ + on line 109 - I thought it was a doc line + drivers/pinctrl/pinctrl-rockchip.c:375: warning: Function parameter or member 'data' not described in 'rockchip_pin_group' + drivers/pinctrl/pinctrl-rockchip.c:387: warning: Function parameter or member 'ngroups' not described in 'rockchip_pmx_func' + +Signed-off-by: Lee Jones +Reviewed-by: Heiko Stuebner +Cc: Heiko Stuebner +Cc: Jean-Christophe PLAGNIOL-VILLARD +Cc: linux-rockchip@lists.infradead.org +Link: https://lore.kernel.org/r/20200713144930.1034632-20-lee.jones@linaro.org +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.c | 22 ++++++++++++---------- + 1 file changed, 12 insertions(+), 10 deletions(-) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index c07324d1f265..c96d810635ad 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -63,7 +63,7 @@ enum rockchip_pinctrl_type { + RK3399, + }; + +-/** ++/* + * Encode variants of iomux registers into a type variable + */ + #define IOMUX_GPIO_ONLY BIT(0) +@@ -74,6 +74,7 @@ enum rockchip_pinctrl_type { + #define IOMUX_WIDTH_2BIT BIT(5) + + /** ++ * struct rockchip_iomux + * @type: iomux variant using IOMUX_* constants + * @offset: if initialized to -1 it will be autocalculated, by specifying + * an initial offset value the relevant source offset can be reset +@@ -84,7 +85,7 @@ struct rockchip_iomux { + int offset; + }; + +-/** ++/* + * enum type index corresponding to rockchip_perpin_drv_list arrays index. + */ + enum rockchip_pin_drv_type { +@@ -96,7 +97,7 @@ enum rockchip_pin_drv_type { + DRV_TYPE_MAX + }; + +-/** ++/* + * enum type index corresponding to rockchip_pull_list arrays index. + */ + enum rockchip_pin_pull_type { +@@ -106,6 +107,7 @@ enum rockchip_pin_pull_type { + }; + + /** ++ * struct rockchip_drv + * @drv_type: drive strength variant using rockchip_perpin_drv_type + * @offset: if initialized to -1 it will be autocalculated, by specifying + * an initial offset value the relevant source offset can be reset +@@ -119,8 +121,9 @@ struct rockchip_drv { + }; + + /** ++ * struct rockchip_pin_bank + * @reg_base: register base of the gpio bank +- * @reg_pull: optional separate register for additional pull settings ++ * @regmap_pull: optional separate register for additional pull settings + * @clk: clock of the gpio bank + * @irq: interrupt of the gpio bank + * @saved_masks: Saved content of GPIO_INTEN at suspend time. +@@ -138,6 +141,8 @@ struct rockchip_drv { + * @gpio_chip: gpiolib chip + * @grange: gpio range + * @slock: spinlock for the gpio bank ++ * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode ++ * @recalced_mask: bit mask to indicate a need to recalulate the mask + * @route_mask: bits describing the routing pins of per bank + */ + struct rockchip_pin_bank { +@@ -312,6 +317,7 @@ enum rockchip_mux_route_location { + * @bank_num: bank number. + * @pin: index at register or used to calc index. + * @func: the min pin. ++ * @route_location: the mux route location (same, pmu, grf). + * @route_offset: the max pin. + * @route_val: the register offset. + */ +@@ -324,8 +330,6 @@ struct rockchip_mux_route_data { + u32 route_val; + }; + +-/** +- */ + struct rockchip_pin_ctrl { + struct rockchip_pin_bank *pin_banks; + u32 nr_banks; +@@ -363,9 +367,7 @@ struct rockchip_pin_config { + * @name: name of the pin group, used to lookup the group. + * @pins: the pins included in this group. + * @npins: number of pins included in this group. +- * @func: the mux function number to be programmed when selected. +- * @configs: the config values to be set for each pin +- * @nconfigs: number of configs for each pin ++ * @data: local pin configuration + */ + struct rockchip_pin_group { + const char *name; +@@ -378,7 +380,7 @@ struct rockchip_pin_group { + * struct rockchip_pmx_func: represent a pin function. + * @name: name of the pin function, used to lookup the function. + * @groups: one or more names of pin groups that provide this function. +- * @num_groups: number of groups included in @groups. ++ * @ngroups: number of groups included in @groups. + */ + struct rockchip_pmx_func { + const char *name; +-- +2.31.1 + diff --git a/patches.suse/pinctrl-rockchip-Replace-HTTP-links-with-HTTPS-ones.patch b/patches.suse/pinctrl-rockchip-Replace-HTTP-links-with-HTTPS-ones.patch new file mode 100644 index 0000000..520dfec --- /dev/null +++ b/patches.suse/pinctrl-rockchip-Replace-HTTP-links-with-HTTPS-ones.patch @@ -0,0 +1,48 @@ +From: "Alexander A. Klimov" +Date: Mon, 13 Jul 2020 20:35:41 +0200 +Subject: pinctrl: rockchip: Replace HTTP links with HTTPS ones + +Git-commit: 3e3f742b23ac975c49572c34f333e6b5b43c35e8 +Patch-mainline: v5.9-rc1 +References: bsc#1192217 + +Rationale: +Reduces attack surface on kernel devs opening the links for MITM +as HTTPS traffic is much harder to manipulate. + +Deterministic algorithm: +For each file: + If not .svg: + For each line: + If doesn't contain `\bxmlns\b`: + For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: + If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: + If both the HTTP and HTTPS versions + return 200 OK and serve the same content: + Replace HTTP with HTTPS. + +Signed-off-by: Alexander A. Klimov +Acked-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20200713183541.36963-1-grandmaster@al2klimov.de +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index c96d810635ad..0401c1da79dd 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -9,7 +9,7 @@ + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2012 Linaro Ltd +- * http://www.linaro.org ++ * https://www.linaro.org + * + * and pinctrl-at91: + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD +-- +2.31.1 + diff --git a/patches.suse/pinctrl-rockchip-add-a-queue-for-deferred-pin-output.patch b/patches.suse/pinctrl-rockchip-add-a-queue-for-deferred-pin-output.patch new file mode 100644 index 0000000..c08d491 --- /dev/null +++ b/patches.suse/pinctrl-rockchip-add-a-queue-for-deferred-pin-output.patch @@ -0,0 +1,189 @@ +From: Heiko Stuebner +Date: Tue, 14 Sep 2021 00:49:25 +0200 +Subject: pinctrl/rockchip: add a queue for deferred pin output settings on + probe + +Git-commit: e7165b1dff06b6e4373ab7758b21f3d9ed8a64ca +Patch-mainline: v5.15-rc4 +References: bsc#1192217 + +The separation of pinctrl and gpio drivers created a tiny window where +a pinconfig setting might produce a null-pointer dereference. + +The affected device were rk3288-veyron devices in this case. + +Pinctrl-hogs are claimed when the pinctrl driver is registered, +at which point their pinconfig settings will be applied. +At this time the now separate gpio devices will not have been created +yet and the matching driver won't have probed yet, making the gpio->foo() +call run into a null-ptr. + +As probing is not really guaranteed to have been completed at a specific +time, introduce a queue that can hold the output settings until the gpio +driver has probed and will (in a separate patch) fetch the elements +of the list. + +We expect the gpio driver to empty the list, but will nevertheless empty +it ourself on remove if that didn't happen. + +Fixes: 9ce9a02039de ("pinctrl/rockchip: drop the gpio related codes") +Signed-off-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20210913224926.1260726-4-heiko@sntech.de +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.c | 67 ++++++++++++++++++++++++++++++ + drivers/pinctrl/pinctrl-rockchip.h | 10 +++++ + 2 files changed, 77 insertions(+) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index ae33e376695f..5ce260f152ce 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -2092,6 +2092,23 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, + return false; + } + ++static int rockchip_pinconf_defer_output(struct rockchip_pin_bank *bank, ++ unsigned int pin, u32 arg) ++{ ++ struct rockchip_pin_output_deferred *cfg; ++ ++ cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); ++ if (!cfg) ++ return -ENOMEM; ++ ++ cfg->pin = pin; ++ cfg->arg = arg; ++ ++ list_add_tail(&cfg->head, &bank->deferred_output); ++ ++ return 0; ++} ++ + /* set the pin config settings for a specified pin */ + static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned num_configs) +@@ -2136,6 +2153,22 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + if (rc != RK_FUNC_GPIO) + return -EINVAL; + ++ /* ++ * Check for gpio driver not being probed yet. ++ * The lock makes sure that either gpio-probe has completed ++ * or the gpio driver hasn't probed yet. ++ */ ++ mutex_lock(&bank->deferred_lock); ++ if (!gpio || !gpio->direction_output) { ++ rc = rockchip_pinconf_defer_output(bank, pin - bank->pin_base, arg); ++ mutex_unlock(&bank->deferred_lock); ++ if (rc) ++ return rc; ++ ++ break; ++ } ++ mutex_unlock(&bank->deferred_lock); ++ + rc = gpio->direction_output(gpio, pin - bank->pin_base, + arg); + if (rc) +@@ -2204,6 +2237,11 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + if (rc != RK_FUNC_GPIO) + return -EINVAL; + ++ if (!gpio || !gpio->get) { ++ arg = 0; ++ break; ++ } ++ + rc = gpio->get(gpio, pin - bank->pin_base); + if (rc < 0) + return rc; +@@ -2450,6 +2488,9 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, + pin_bank->name, pin); + pdesc++; + } ++ ++ INIT_LIST_HEAD(&pin_bank->deferred_output); ++ mutex_init(&pin_bank->deferred_lock); + } + + ret = rockchip_pinctrl_parse_dt(pdev, info); +@@ -2716,6 +2757,31 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) + return 0; + } + ++static int rockchip_pinctrl_remove(struct platform_device *pdev) ++{ ++ struct rockchip_pinctrl *info = platform_get_drvdata(pdev); ++ struct rockchip_pin_bank *bank; ++ struct rockchip_pin_output_deferred *cfg; ++ int i; ++ ++ of_platform_depopulate(&pdev->dev); ++ ++ for (i = 0; i < info->ctrl->nr_banks; i++) { ++ bank = &info->ctrl->pin_banks[i]; ++ ++ mutex_lock(&bank->deferred_lock); ++ while (!list_empty(&bank->deferred_output)) { ++ cfg = list_first_entry(&bank->deferred_output, ++ struct rockchip_pin_output_deferred, head); ++ list_del(&cfg->head); ++ kfree(cfg); ++ } ++ mutex_unlock(&bank->deferred_lock); ++ } ++ ++ return 0; ++} ++ + static struct rockchip_pin_bank px30_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, +@@ -3175,6 +3241,7 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { + + static struct platform_driver rockchip_pinctrl_driver = { + .probe = rockchip_pinctrl_probe, ++ .remove = rockchip_pinctrl_remove, + .driver = { + .name = "rockchip-pinctrl", + .pm = &rockchip_pinctrl_dev_pm_ops, +diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h +index 589d4d2a98c9..91f10279d084 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.h ++++ b/drivers/pinctrl/pinctrl-rockchip.h +@@ -141,6 +141,8 @@ struct rockchip_drv { + * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode + * @recalced_mask: bit mask to indicate a need to recalulate the mask + * @route_mask: bits describing the routing pins of per bank ++ * @deferred_output: gpio output settings to be done after gpio bank probed ++ * @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl + */ + struct rockchip_pin_bank { + struct device *dev; +@@ -169,6 +171,8 @@ struct rockchip_pin_bank { + u32 toggle_edge_mode; + u32 recalced_mask; + u32 route_mask; ++ struct list_head deferred_output; ++ struct mutex deferred_lock; + }; + + /** +@@ -243,6 +247,12 @@ struct rockchip_pin_config { + unsigned int nconfigs; + }; + ++struct rockchip_pin_output_deferred { ++ struct list_head head; ++ unsigned int pin; ++ u32 arg; ++}; ++ + /** + * struct rockchip_pin_group: represent group of pins of a pinmux function. + * @name: name of the pin group, used to lookup the group. +-- +2.31.1 + diff --git a/patches.suse/pinctrl-rockchip-add-pinctrl-device-to-gpio-bank-str.patch b/patches.suse/pinctrl-rockchip-add-pinctrl-device-to-gpio-bank-str.patch new file mode 100644 index 0000000..3f4fe59 --- /dev/null +++ b/patches.suse/pinctrl-rockchip-add-pinctrl-device-to-gpio-bank-str.patch @@ -0,0 +1,41 @@ +From: Jianqun Xu +Date: Mon, 16 Aug 2021 09:19:42 +0800 +Subject: pinctrl/rockchip: add pinctrl device to gpio bank struct + +Git-commit: 5f82afd868a04f65630c22f75b40c60cba418b8e +Patch-mainline: v5.15-rc1 +References: bsc#1192217 + +Store a pointer from the pinctrl device for the gpio bank. + +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20210816011948.1118959-4-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h +index dba9e9540633..4aa3d2f1fa67 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.h ++++ b/drivers/pinctrl/pinctrl-rockchip.h +@@ -81,6 +81,7 @@ struct rockchip_drv { + + /** + * struct rockchip_pin_bank ++ * @dev: the pinctrl device bind to the bank + * @reg_base: register base of the gpio bank + * @regmap_pull: optional separate register for additional pull settings + * @clk: clock of the gpio bank +@@ -105,6 +106,7 @@ struct rockchip_drv { + * @route_mask: bits describing the routing pins of per bank + */ + struct rockchip_pin_bank { ++ struct device *dev; + void __iomem *reg_base; + struct regmap *regmap_pull; + struct clk *clk; +-- +2.31.1 + diff --git a/patches.suse/pinctrl-rockchip-add-rk3308-SoC-support.patch b/patches.suse/pinctrl-rockchip-add-rk3308-SoC-support.patch new file mode 100644 index 0000000..c71bfe9 --- /dev/null +++ b/patches.suse/pinctrl-rockchip-add-rk3308-SoC-support.patch @@ -0,0 +1,492 @@ +From: Jianqun Xu +Date: Tue, 15 Oct 2019 17:17:08 +0800 +Subject: pinctrl: rockchip: add rk3308 SoC support + +Git-commit: 7825aeb7b20854740586a9f7484c1fdfc516eca5 +Patch-mainline: v5.5-rc1 +References: bsc#1192217 + +This patch do support pinctrl for RK3308 SoCs. + +Reviewed-by: Heiko Stuebner +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20191015091708.7934-3-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.c | 382 ++++++++++++++++++++++++++++- + 1 file changed, 381 insertions(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index dc0bbf198cbc..fc9a2a9959d9 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -58,6 +58,7 @@ enum rockchip_pinctrl_type { + RK3128, + RK3188, + RK3288, ++ RK3308, + RK3368, + RK3399, + }; +@@ -70,6 +71,7 @@ enum rockchip_pinctrl_type { + #define IOMUX_SOURCE_PMU BIT(2) + #define IOMUX_UNROUTED BIT(3) + #define IOMUX_WIDTH_3BIT BIT(4) ++#define IOMUX_WIDTH_2BIT BIT(5) + + /** + * @type: iomux variant using IOMUX_* constants +@@ -656,6 +658,100 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { + }, + }; + ++static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { ++ { ++ .num = 1, ++ .pin = 14, ++ .reg = 0x28, ++ .bit = 12, ++ .mask = 0xf ++ }, { ++ .num = 1, ++ .pin = 15, ++ .reg = 0x2c, ++ .bit = 0, ++ .mask = 0x3 ++ }, { ++ .num = 1, ++ .pin = 18, ++ .reg = 0x30, ++ .bit = 4, ++ .mask = 0xf ++ }, { ++ .num = 1, ++ .pin = 19, ++ .reg = 0x30, ++ .bit = 8, ++ .mask = 0xf ++ }, { ++ .num = 1, ++ .pin = 20, ++ .reg = 0x30, ++ .bit = 12, ++ .mask = 0xf ++ }, { ++ .num = 1, ++ .pin = 21, ++ .reg = 0x34, ++ .bit = 0, ++ .mask = 0xf ++ }, { ++ .num = 1, ++ .pin = 22, ++ .reg = 0x34, ++ .bit = 4, ++ .mask = 0xf ++ }, { ++ .num = 1, ++ .pin = 23, ++ .reg = 0x34, ++ .bit = 8, ++ .mask = 0xf ++ }, { ++ .num = 3, ++ .pin = 12, ++ .reg = 0x68, ++ .bit = 8, ++ .mask = 0xf ++ }, { ++ .num = 3, ++ .pin = 13, ++ .reg = 0x68, ++ .bit = 12, ++ .mask = 0xf ++ }, { ++ .num = 2, ++ .pin = 2, ++ .reg = 0x608, ++ .bit = 0, ++ .mask = 0x7 ++ }, { ++ .num = 2, ++ .pin = 3, ++ .reg = 0x608, ++ .bit = 4, ++ .mask = 0x7 ++ }, { ++ .num = 2, ++ .pin = 16, ++ .reg = 0x610, ++ .bit = 8, ++ .mask = 0x7 ++ }, { ++ .num = 3, ++ .pin = 10, ++ .reg = 0x610, ++ .bit = 0, ++ .mask = 0x7 ++ }, { ++ .num = 3, ++ .pin = 11, ++ .reg = 0x610, ++ .bit = 4, ++ .mask = 0x7 ++ }, ++}; ++ + static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { + { + .num = 2, +@@ -982,6 +1078,192 @@ static struct rockchip_mux_route_data rk3288_mux_route_data[] = { + }, + }; + ++static struct rockchip_mux_route_data rk3308_mux_route_data[] = { ++ { ++ /* rtc_clk */ ++ .bank_num = 0, ++ .pin = 19, ++ .func = 1, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 0) | BIT(0), ++ }, { ++ /* uart2_rxm0 */ ++ .bank_num = 1, ++ .pin = 22, ++ .func = 2, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 2) | BIT(16 + 3), ++ }, { ++ /* uart2_rxm1 */ ++ .bank_num = 4, ++ .pin = 26, ++ .func = 2, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), ++ }, { ++ /* i2c3_sdam0 */ ++ .bank_num = 0, ++ .pin = 15, ++ .func = 2, ++ .route_offset = 0x608, ++ .route_val = BIT(16 + 8) | BIT(16 + 9), ++ }, { ++ /* i2c3_sdam1 */ ++ .bank_num = 3, ++ .pin = 12, ++ .func = 2, ++ .route_offset = 0x608, ++ .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), ++ }, { ++ /* i2c3_sdam2 */ ++ .bank_num = 2, ++ .pin = 0, ++ .func = 3, ++ .route_offset = 0x608, ++ .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), ++ }, { ++ /* i2s-8ch-1-sclktxm0 */ ++ .bank_num = 1, ++ .pin = 3, ++ .func = 2, ++ .route_offset = 0x308, ++ .route_val = BIT(16 + 3), ++ }, { ++ /* i2s-8ch-1-sclkrxm0 */ ++ .bank_num = 1, ++ .pin = 4, ++ .func = 2, ++ .route_offset = 0x308, ++ .route_val = BIT(16 + 3), ++ }, { ++ /* i2s-8ch-1-sclktxm1 */ ++ .bank_num = 1, ++ .pin = 13, ++ .func = 2, ++ .route_offset = 0x308, ++ .route_val = BIT(16 + 3) | BIT(3), ++ }, { ++ /* i2s-8ch-1-sclkrxm1 */ ++ .bank_num = 1, ++ .pin = 14, ++ .func = 2, ++ .route_offset = 0x308, ++ .route_val = BIT(16 + 3) | BIT(3), ++ }, { ++ /* pdm-clkm0 */ ++ .bank_num = 1, ++ .pin = 4, ++ .func = 3, ++ .route_offset = 0x308, ++ .route_val = BIT(16 + 12) | BIT(16 + 13), ++ }, { ++ /* pdm-clkm1 */ ++ .bank_num = 1, ++ .pin = 14, ++ .func = 4, ++ .route_offset = 0x308, ++ .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), ++ }, { ++ /* pdm-clkm2 */ ++ .bank_num = 2, ++ .pin = 6, ++ .func = 2, ++ .route_offset = 0x308, ++ .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), ++ }, { ++ /* pdm-clkm-m2 */ ++ .bank_num = 2, ++ .pin = 4, ++ .func = 3, ++ .route_offset = 0x600, ++ .route_val = BIT(16 + 2) | BIT(2), ++ }, { ++ /* spi1_miso */ ++ .bank_num = 3, ++ .pin = 10, ++ .func = 3, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 9), ++ }, { ++ /* spi1_miso_m1 */ ++ .bank_num = 2, ++ .pin = 4, ++ .func = 2, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 9) | BIT(9), ++ }, { ++ /* owire_m0 */ ++ .bank_num = 0, ++ .pin = 11, ++ .func = 3, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 10) | BIT(16 + 11), ++ }, { ++ /* owire_m1 */ ++ .bank_num = 1, ++ .pin = 22, ++ .func = 7, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), ++ }, { ++ /* owire_m2 */ ++ .bank_num = 2, ++ .pin = 2, ++ .func = 5, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), ++ }, { ++ /* can_rxd_m0 */ ++ .bank_num = 0, ++ .pin = 11, ++ .func = 2, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 12) | BIT(16 + 13), ++ }, { ++ /* can_rxd_m1 */ ++ .bank_num = 1, ++ .pin = 22, ++ .func = 5, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), ++ }, { ++ /* can_rxd_m2 */ ++ .bank_num = 2, ++ .pin = 2, ++ .func = 4, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), ++ }, { ++ /* mac_rxd0_m0 */ ++ .bank_num = 1, ++ .pin = 20, ++ .func = 3, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 14), ++ }, { ++ /* mac_rxd0_m1 */ ++ .bank_num = 4, ++ .pin = 2, ++ .func = 2, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 14) | BIT(14), ++ }, { ++ /* uart3_rx */ ++ .bank_num = 3, ++ .pin = 12, ++ .func = 4, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 15), ++ }, { ++ /* uart3_rx_m1 */ ++ .bank_num = 0, ++ .pin = 17, ++ .func = 3, ++ .route_offset = 0x314, ++ .route_val = BIT(16 + 15) | BIT(15), ++ }, ++}; ++ + static struct rockchip_mux_route_data rk3328_mux_route_data[] = { + { + /* uart2dbg_rxm0 */ +@@ -1475,6 +1757,26 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + return 0; + } + ++#define RK3308_SCHMITT_PINS_PER_REG 8 ++#define RK3308_SCHMITT_BANK_STRIDE 16 ++#define RK3308_SCHMITT_GRF_OFFSET 0x1a0 ++ ++static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ *regmap = info->regmap_base; ++ *reg = RK3308_SCHMITT_GRF_OFFSET; ++ ++ *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; ++ *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); ++ *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; ++ ++ return 0; ++} ++ + #define RK2928_PULL_OFFSET 0x118 + #define RK2928_PULL_PINS_PER_REG 16 + #define RK2928_PULL_BANK_STRIDE 8 +@@ -1646,6 +1948,40 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + *bit *= RK3288_DRV_BITS_PER_PIN; + } + ++#define RK3308_PULL_OFFSET 0xa0 ++ ++static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ *regmap = info->regmap_base; ++ *reg = RK3308_PULL_OFFSET; ++ *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; ++ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); ++ ++ *bit = (pin_num % RK3188_PULL_PINS_PER_REG); ++ *bit *= RK3188_PULL_BITS_PER_PIN; ++} ++ ++#define RK3308_DRV_GRF_OFFSET 0x100 ++ ++static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ *regmap = info->regmap_base; ++ *reg = RK3308_DRV_GRF_OFFSET; ++ *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; ++ *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); ++ ++ *bit = (pin_num % RK3288_DRV_PINS_PER_REG); ++ *bit *= RK3288_DRV_BITS_PER_PIN; ++} ++ + #define RK3368_PULL_GRF_OFFSET 0x100 + #define RK3368_PULL_PMU_OFFSET 0x10 + +@@ -1986,6 +2322,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) + case RV1108: + case RK3188: + case RK3288: ++ case RK3308: + case RK3368: + case RK3399: + pull_type = bank->pull_type[pin_num / 8]; +@@ -2030,6 +2367,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, + case RV1108: + case RK3188: + case RK3288: ++ case RK3308: + case RK3368: + case RK3399: + pull_type = bank->pull_type[pin_num / 8]; +@@ -2293,6 +2631,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, + case RV1108: + case RK3188: + case RK3288: ++ case RK3308: + case RK3368: + case RK3399: + return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); +@@ -3303,7 +3642,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( + * 4bit iomux'es are spread over two registers. + */ + inc = (iom->type & (IOMUX_WIDTH_4BIT | +- IOMUX_WIDTH_3BIT)) ? 8 : 4; ++ IOMUX_WIDTH_3BIT | ++ IOMUX_WIDTH_2BIT)) ? 8 : 4; + if (iom->type & IOMUX_SOURCE_PMU) + pmu_offs += inc; + else +@@ -3709,6 +4049,44 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { + .drv_calc_reg = rk3288_calc_drv_reg_and_bit, + }; + ++static struct rockchip_pin_bank rk3308_pin_banks[] = { ++ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT), ++ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT), ++ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT), ++ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT), ++ PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT, ++ IOMUX_WIDTH_2BIT), ++}; ++ ++static struct rockchip_pin_ctrl rk3308_pin_ctrl = { ++ .pin_banks = rk3308_pin_banks, ++ .nr_banks = ARRAY_SIZE(rk3308_pin_banks), ++ .label = "RK3308-GPIO", ++ .type = RK3308, ++ .grf_mux_offset = 0x0, ++ .iomux_recalced = rk3308_mux_recalced_data, ++ .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), ++ .iomux_routes = rk3308_mux_route_data, ++ .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), ++ .pull_calc_reg = rk3308_calc_pull_reg_and_bit, ++ .drv_calc_reg = rk3308_calc_drv_reg_and_bit, ++ .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, ++}; ++ + static struct rockchip_pin_bank rk3328_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), +@@ -3849,6 +4227,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { + .data = &rk3228_pin_ctrl }, + { .compatible = "rockchip,rk3288-pinctrl", + .data = &rk3288_pin_ctrl }, ++ { .compatible = "rockchip,rk3308-pinctrl", ++ .data = &rk3308_pin_ctrl }, + { .compatible = "rockchip,rk3328-pinctrl", + .data = &rk3328_pin_ctrl }, + { .compatible = "rockchip,rk3368-pinctrl", +-- +2.31.1 + diff --git a/patches.suse/pinctrl-rockchip-add-support-for-rk3568.patch b/patches.suse/pinctrl-rockchip-add-support-for-rk3568.patch new file mode 100644 index 0000000..aa9d88e --- /dev/null +++ b/patches.suse/pinctrl-rockchip-add-support-for-rk3568.patch @@ -0,0 +1,418 @@ +From: Jianqun Xu +Date: Fri, 19 Mar 2021 16:14:41 +0800 +Subject: pinctrl: rockchip: add support for rk3568 + +Git-commit: c0dadc0e47a895e95c17a4df1fa12737e1d57d6f +Patch-mainline: v5.13-rc1 +References: bsc#1192217 + +RK3568 SoCs have 5 gpio controllers, each gpio has 32 pins. GPIO supports +set iomux, pull, drive strength and schmitt. + +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20210319081441.368358-1-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.c | 292 ++++++++++++++++++++++++++++- + 1 file changed, 290 insertions(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index 65aa87476eae..05128f53824c 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -63,8 +63,17 @@ enum rockchip_pinctrl_type { + RK3308, + RK3368, + RK3399, ++ RK3568, + }; + ++ ++/** ++ * Generate a bitmask for setting a value (v) with a write mask bit in hiword ++ * register 31:16 area. ++ */ ++#define WRITE_MASK_VAL(h, l, v) \ ++ (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) ++ + /* + * Encode variants of iomux registers into a type variable + */ +@@ -292,6 +301,25 @@ struct rockchip_pin_bank { + .pull_type[3] = pull3, \ + } + ++#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ ++ { \ ++ .bank_num = ID, \ ++ .pin = PIN, \ ++ .func = FUNC, \ ++ .route_offset = REG, \ ++ .route_val = VAL, \ ++ .route_location = FLAG, \ ++ } ++ ++#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \ ++ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME) ++ ++#define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \ ++ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF) ++ ++#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ ++ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) ++ + /** + * struct rockchip_mux_recalced_data: represent a pin iomux data. + * @num: bank number. +@@ -1396,6 +1424,102 @@ static struct rockchip_mux_route_data rk3399_mux_route_data[] = { + }, + }; + ++static struct rockchip_mux_route_data rk3568_mux_route_data[] = { ++ RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ ++ RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ ++ RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ ++ RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */ ++ RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */ ++ RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */ ++ RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */ ++ RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */ ++ RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */ ++ RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */ ++ RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */ ++ RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */ ++ RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */ ++ RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */ ++ RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */ ++ RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */ ++ RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */ ++ RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */ ++ RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */ ++ RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */ ++ RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */ ++ RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */ ++ RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */ ++ RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */ ++ RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */ ++ RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */ ++ RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */ ++ RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */ ++ RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */ ++ RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */ ++ RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */ ++ RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */ ++ RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */ ++ RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */ ++ RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */ ++ RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */ ++ RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */ ++ RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */ ++ RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */ ++ RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */ ++ RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */ ++ RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */ ++ RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */ ++ RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */ ++ RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */ ++ RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */ ++ RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */ ++ RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */ ++ RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */ ++ RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */ ++ RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */ ++ RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */ ++ RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */ ++ RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */ ++ RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */ ++ RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */ ++ RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */ ++ RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */ ++ RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */ ++ RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */ ++ RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */ ++ RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */ ++ RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */ ++ RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */ ++ RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */ ++ RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */ ++ RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */ ++ RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */ ++ RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */ ++ RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */ ++ RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */ ++ RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */ ++ RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */ ++ RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */ ++ RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */ ++ RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */ ++ RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */ ++ RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */ ++ RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */ ++ RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ ++ RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ ++ RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ ++ RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ ++ RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */ ++ RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */ ++ RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */ ++ RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */ ++ RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */ ++ RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */ ++ RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */ ++ RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */ ++ RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */ ++ RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */ ++}; ++ + static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, + int mux, u32 *loc, u32 *reg, u32 *value) + { +@@ -2104,6 +2228,68 @@ static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + *bit = (pin_num % 8) * 2; + } + ++#define RK3568_PULL_PMU_OFFSET 0x20 ++#define RK3568_PULL_GRF_OFFSET 0x80 ++#define RK3568_PULL_BITS_PER_PIN 2 ++#define RK3568_PULL_PINS_PER_REG 8 ++#define RK3568_PULL_BANK_STRIDE 0x10 ++ ++static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ if (bank->bank_num == 0) { ++ *regmap = info->regmap_pmu; ++ *reg = RK3568_PULL_PMU_OFFSET; ++ *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; ++ *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); ++ ++ *bit = pin_num % RK3568_PULL_PINS_PER_REG; ++ *bit *= RK3568_PULL_BITS_PER_PIN; ++ } else { ++ *regmap = info->regmap_base; ++ *reg = RK3568_PULL_GRF_OFFSET; ++ *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; ++ *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); ++ ++ *bit = (pin_num % RK3568_PULL_PINS_PER_REG); ++ *bit *= RK3568_PULL_BITS_PER_PIN; ++ } ++} ++ ++#define RK3568_DRV_PMU_OFFSET 0x70 ++#define RK3568_DRV_GRF_OFFSET 0x200 ++#define RK3568_DRV_BITS_PER_PIN 8 ++#define RK3568_DRV_PINS_PER_REG 2 ++#define RK3568_DRV_BANK_STRIDE 0x40 ++ ++static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ /* The first 32 pins of the first bank are located in PMU */ ++ if (bank->bank_num == 0) { ++ *regmap = info->regmap_pmu; ++ *reg = RK3568_DRV_PMU_OFFSET; ++ *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); ++ ++ *bit = pin_num % RK3568_DRV_PINS_PER_REG; ++ *bit *= RK3568_DRV_BITS_PER_PIN; ++ } else { ++ *regmap = info->regmap_base; ++ *reg = RK3568_DRV_GRF_OFFSET; ++ *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; ++ *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); ++ ++ *bit = (pin_num % RK3568_DRV_PINS_PER_REG); ++ *bit *= RK3568_DRV_BITS_PER_PIN; ++ } ++} ++ + static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { + { 2, 4, 8, 12, -1, -1, -1, -1 }, + { 3, 6, 9, 12, -1, -1, -1, -1 }, +@@ -2204,6 +2390,11 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, + bank->bank_num, pin_num, strength); + + ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); ++ if (ctrl->type == RK3568) { ++ rmask_bits = RK3568_DRV_BITS_PER_PIN; ++ ret = (1 << (strength + 1)) - 1; ++ goto config; ++ } + + ret = -EINVAL; + for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { +@@ -2273,6 +2464,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, + return -EINVAL; + } + ++config: + /* enable the write to the equivalent lower bits */ + data = ((1 << rmask_bits) - 1) << (bit + 16); + rmask = data | (data >> 16); +@@ -2375,6 +2567,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, + case RK3308: + case RK3368: + case RK3399: ++ case RK3568: + pull_type = bank->pull_type[pin_num / 8]; + ret = -EINVAL; + for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); +@@ -2384,6 +2577,14 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, + break; + } + } ++ /* ++ * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6, ++ * where that pull up value becomes 3. ++ */ ++ if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { ++ if (ret == 1) ++ ret = 3; ++ } + + if (ret < 0) { + dev_err(info->dev, "unsupported pull setting %d\n", +@@ -2428,6 +2629,35 @@ static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + return 0; + } + ++#define RK3568_SCHMITT_BITS_PER_PIN 2 ++#define RK3568_SCHMITT_PINS_PER_REG 8 ++#define RK3568_SCHMITT_BANK_STRIDE 0x10 ++#define RK3568_SCHMITT_GRF_OFFSET 0xc0 ++#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 ++ ++static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, ++ int pin_num, ++ struct regmap **regmap, ++ int *reg, u8 *bit) ++{ ++ struct rockchip_pinctrl *info = bank->drvdata; ++ ++ if (bank->bank_num == 0) { ++ *regmap = info->regmap_pmu; ++ *reg = RK3568_SCHMITT_PMUGRF_OFFSET; ++ } else { ++ *regmap = info->regmap_base; ++ *reg = RK3568_SCHMITT_GRF_OFFSET; ++ *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; ++ } ++ ++ *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); ++ *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; ++ *bit *= RK3568_SCHMITT_BITS_PER_PIN; ++ ++ return 0; ++} ++ + static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) + { + struct rockchip_pinctrl *info = bank->drvdata; +@@ -2446,6 +2676,13 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) + return ret; + + data >>= bit; ++ switch (ctrl->type) { ++ case RK3568: ++ return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); ++ default: ++ break; ++ } ++ + return data & 0x1; + } + +@@ -2467,8 +2704,17 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, + return ret; + + /* enable the write to the equivalent lower bits */ +- data = BIT(bit + 16) | (enable << bit); +- rmask = BIT(bit + 16) | BIT(bit); ++ switch (ctrl->type) { ++ case RK3568: ++ data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); ++ rmask = data | (data >> 16); ++ data |= ((enable ? 0x2 : 0x1) << bit); ++ break; ++ default: ++ data = BIT(bit + 16) | (enable << bit); ++ rmask = BIT(bit + 16) | BIT(bit); ++ break; ++ } + + return regmap_update_bits(regmap, reg, rmask, data); + } +@@ -2642,6 +2888,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, + case RK3308: + case RK3368: + case RK3399: ++ case RK3568: + return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); + } + +@@ -4213,6 +4460,45 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = { + .drv_calc_reg = rk3399_calc_drv_reg_and_bit, + }; + ++static struct rockchip_pin_bank rk3568_pin_banks[] = { ++ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, ++ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, ++ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, ++ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), ++ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT), ++ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT), ++ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT), ++ PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT, ++ IOMUX_WIDTH_4BIT), ++}; ++ ++static struct rockchip_pin_ctrl rk3568_pin_ctrl = { ++ .pin_banks = rk3568_pin_banks, ++ .nr_banks = ARRAY_SIZE(rk3568_pin_banks), ++ .label = "RK3568-GPIO", ++ .type = RK3568, ++ .grf_mux_offset = 0x0, ++ .pmu_mux_offset = 0x0, ++ .grf_drv_offset = 0x0200, ++ .pmu_drv_offset = 0x0070, ++ .iomux_routes = rk3568_mux_route_data, ++ .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), ++ .pull_calc_reg = rk3568_calc_pull_reg_and_bit, ++ .drv_calc_reg = rk3568_calc_drv_reg_and_bit, ++ .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit, ++}; ++ + static const struct of_device_id rockchip_pinctrl_dt_match[] = { + { .compatible = "rockchip,px30-pinctrl", + .data = &px30_pin_ctrl }, +@@ -4242,6 +4528,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { + .data = &rk3368_pin_ctrl }, + { .compatible = "rockchip,rk3399-pinctrl", + .data = &rk3399_pin_ctrl }, ++ { .compatible = "rockchip,rk3568-pinctrl", ++ .data = &rk3568_pin_ctrl }, + {}, + }; + +-- +2.31.1 + diff --git a/patches.suse/pinctrl-rockchip-always-enable-clock-for-gpio-contro.patch b/patches.suse/pinctrl-rockchip-always-enable-clock-for-gpio-contro.patch new file mode 100644 index 0000000..3fd4d38 --- /dev/null +++ b/patches.suse/pinctrl-rockchip-always-enable-clock-for-gpio-contro.patch @@ -0,0 +1,212 @@ +From: Jianqun Xu +Date: Mon, 16 Aug 2021 09:19:40 +0800 +Subject: pinctrl/rockchip: always enable clock for gpio controller + +Git-commit: 4b522bbf80f67ff17c0cc1fe66654202810b4482 +Patch-mainline: v5.15-rc1 +References: bsc#1192217 + +Since gate and ungate pclk of gpio has very litte benifit for system +power consumption, just keep it always ungate. + +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20210816011948.1118959-2-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.c | 39 ------------------------------------- + 1 file changed, 1 insertion(+), 38 deletions(-) + +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -2299,16 +2299,8 @@ static int rockchip_gpio_get_direction(s + { + struct rockchip_pin_bank *bank = gpiochip_get_data(chip); + u32 data; +- int ret; + +- ret = clk_enable(bank->clk); +- if (ret < 0) { +- dev_err(bank->drvdata->dev, +- "failed to enable clock for bank %s\n", bank->name); +- return ret; +- } + data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); +- clk_disable(bank->clk); + + return !(data & BIT(offset)); + } +@@ -2332,7 +2324,6 @@ static int _rockchip_pmx_gpio_set_direct + if (ret < 0) + return ret; + +- clk_enable(bank->clk); + raw_spin_lock_irqsave(&bank->slock, flags); + + data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); +@@ -2344,7 +2335,6 @@ static int _rockchip_pmx_gpio_set_direct + writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); + + raw_spin_unlock_irqrestore(&bank->slock, flags); +- clk_disable(bank->clk); + + return 0; + } +@@ -2795,7 +2785,6 @@ static void rockchip_gpio_set(struct gpi + unsigned long flags; + u32 data; + +- clk_enable(bank->clk); + raw_spin_lock_irqsave(&bank->slock, flags); + + data = readl(reg); +@@ -2805,7 +2794,6 @@ static void rockchip_gpio_set(struct gpi + writel(data, reg); + + raw_spin_unlock_irqrestore(&bank->slock, flags); +- clk_disable(bank->clk); + } + + /* +@@ -2817,9 +2805,7 @@ static int rockchip_gpio_get(struct gpio + struct rockchip_pin_bank *bank = gpiochip_get_data(gc); + u32 data; + +- clk_enable(bank->clk); + data = readl(bank->reg_base + GPIO_EXT_PORT); +- clk_disable(bank->clk); + data >>= offset; + data &= 1; + return data; +@@ -2855,7 +2841,6 @@ static void rockchip_gpio_set_debounce(s + unsigned long flags; + u32 data; + +- clk_enable(bank->clk); + raw_spin_lock_irqsave(&bank->slock, flags); + + data = readl(reg); +@@ -2866,7 +2851,6 @@ static void rockchip_gpio_set_debounce(s + writel(data, reg); + + raw_spin_unlock_irqrestore(&bank->slock, flags); +- clk_disable(bank->clk); + } + + /* +@@ -2911,9 +2895,7 @@ static int rockchip_gpio_to_irq(struct g + if (!bank->domain) + return -ENXIO; + +- clk_enable(bank->clk); + virq = irq_create_mapping(bank->domain, offset); +- clk_disable(bank->clk); + + return (virq) ? : -ENXIO; + } +@@ -3012,7 +2994,6 @@ static int rockchip_irq_set_type(struct + if (ret < 0) + return ret; + +- clk_enable(bank->clk); + raw_spin_lock_irqsave(&bank->slock, flags); + + data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); +@@ -3070,7 +3051,6 @@ static int rockchip_irq_set_type(struct + default: + irq_gc_unlock(gc); + raw_spin_unlock_irqrestore(&bank->slock, flags); +- clk_disable(bank->clk); + return -EINVAL; + } + +@@ -3079,7 +3059,6 @@ static int rockchip_irq_set_type(struct + + irq_gc_unlock(gc); + raw_spin_unlock_irqrestore(&bank->slock, flags); +- clk_disable(bank->clk); + + return 0; + } +@@ -3089,10 +3068,8 @@ static void rockchip_irq_suspend(struct + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct rockchip_pin_bank *bank = gc->private; + +- clk_enable(bank->clk); + bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); + irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); +- clk_disable(bank->clk); + } + + static void rockchip_irq_resume(struct irq_data *d) +@@ -3100,9 +3077,7 @@ static void rockchip_irq_resume(struct i + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct rockchip_pin_bank *bank = gc->private; + +- clk_enable(bank->clk); + irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); +- clk_disable(bank->clk); + } + + static void rockchip_irq_enable(struct irq_data *d) +@@ -3110,7 +3085,6 @@ static void rockchip_irq_enable(struct i + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct rockchip_pin_bank *bank = gc->private; + +- clk_enable(bank->clk); + irq_gc_mask_clr_bit(d); + } + +@@ -3120,7 +3094,6 @@ static void rockchip_irq_disable(struct + struct rockchip_pin_bank *bank = gc->private; + + irq_gc_mask_set_bit(d); +- clk_disable(bank->clk); + } + + static int rockchip_interrupts_register(struct platform_device *pdev, +@@ -3140,19 +3113,11 @@ static int rockchip_interrupts_register( + continue; + } + +- ret = clk_enable(bank->clk); +- if (ret) { +- dev_err(&pdev->dev, "failed to enable clock for bank %s\n", +- bank->name); +- continue; +- } +- + bank->domain = irq_domain_add_linear(bank->of_node, 32, + &irq_generic_chip_ops, NULL); + if (!bank->domain) { + dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", + bank->name); +- clk_disable(bank->clk); + continue; + } + +@@ -3163,7 +3128,6 @@ static int rockchip_interrupts_register( + dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", + bank->name); + irq_domain_remove(bank->domain); +- clk_disable(bank->clk); + continue; + } + +@@ -3195,7 +3159,6 @@ static int rockchip_interrupts_register( + + irq_set_chained_handler_and_data(bank->irq, + rockchip_irq_demux, bank); +- clk_disable(bank->clk); + } + + return 0; +@@ -3314,7 +3277,7 @@ static int rockchip_get_bank_data(struct + if (IS_ERR(bank->clk)) + return PTR_ERR(bank->clk); + +- return clk_prepare(bank->clk); ++ return clk_prepare_enable(bank->clk); + } + + static const struct of_device_id rockchip_pinctrl_dt_match[]; diff --git a/patches.suse/pinctrl-rockchip-clear-int-status-when-driver-probed.patch b/patches.suse/pinctrl-rockchip-clear-int-status-when-driver-probed.patch new file mode 100644 index 0000000..656eafd --- /dev/null +++ b/patches.suse/pinctrl-rockchip-clear-int-status-when-driver-probed.patch @@ -0,0 +1,37 @@ +From: Jianqun Xu +Date: Tue, 23 Feb 2021 18:19:37 +0800 +Subject: pinctrl: rockchip: clear int status when driver probed + +Git-commit: b37c35781d9ad929c150b2b0b1eb0070a312585b +Patch-mainline: v5.13-rc1 +References: bsc#1192217 + +Some devices may do gpio interrupt trigger and make an int status before +pinctrl driver probed, then the gpio handler will keep complain untill +the device driver works to stop trigger. + +Signed-off-by: Ziyuan Xu +Signed-off-by: Jianqun Xu +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20210223101937.273085-1-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index aa1a1c850d05..ec4cb88572cf 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -3433,6 +3433,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev, + * things enabled, so for us that's all masked and all enabled. + */ + writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); ++ writel_relaxed(0xffffffff, bank->reg_base + GPIO_PORTS_EOI); + writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); + gc->mask_cache = 0xffffffff; + +-- +2.31.1 + diff --git a/patches.suse/pinctrl-rockchip-create-irq-mapping-in-gpio_to_irq.patch b/patches.suse/pinctrl-rockchip-create-irq-mapping-in-gpio_to_irq.patch new file mode 100644 index 0000000..03a3c4d --- /dev/null +++ b/patches.suse/pinctrl-rockchip-create-irq-mapping-in-gpio_to_irq.patch @@ -0,0 +1,99 @@ +From: Jianqun Xu +Date: Tue, 13 Oct 2020 14:37:31 +0800 +Subject: pinctrl: rockchip: create irq mapping in gpio_to_irq + +Git-commit: 8045ec42d14c6f77b5e925d1421150c043dfb75d +Patch-mainline: v5.10-rc4 +References: bsc#1192217 + +Remove totally irq mappings create in probe, the gpio irq mapping will +be created when do + gpio_to_irq -> + rockchip_gpio_to_irq -> + irq_create_mapping + +This patch can speed up system boot on, also abandon many unused irq +mappings' create. + +Signed-off-by: Jianqun Xu +Reviewed-by: Heiko Stuebner +Reviewed-by: Kever Yang +Link: https://lore.kernel.org/r/20201013063731.3618-4-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.c | 28 ++++++++++++---------------- + 1 file changed, 12 insertions(+), 16 deletions(-) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index 7b398ed2113e..aa1a1c850d05 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -3196,7 +3196,7 @@ static void rockchip_irq_demux(struct irq_desc *desc) + + irq = __ffs(pend); + pend &= ~BIT(irq); +- virq = irq_linear_revmap(bank->domain, irq); ++ virq = irq_find_mapping(bank->domain, irq); + + if (!virq) { + dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); +@@ -3375,7 +3375,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev, + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + struct irq_chip_generic *gc; + int ret; +- int i, j; ++ int i; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + if (!bank->valid) { +@@ -3402,7 +3402,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev, + + ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, + "rockchip_gpio_irq", handle_level_irq, +- clr, 0, IRQ_GC_INIT_MASK_CACHE); ++ clr, 0, 0); + if (ret) { + dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", + bank->name); +@@ -3411,14 +3411,6 @@ static int rockchip_interrupts_register(struct platform_device *pdev, + continue; + } + +- /* +- * Linux assumes that all interrupts start out disabled/masked. +- * Our driver only uses the concept of masked and always keeps +- * things enabled, so for us that's all masked and all enabled. +- */ +- writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); +- writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); +- + gc = irq_get_domain_generic_chip(bank->domain, 0); + gc->reg_base = bank->reg_base; + gc->private = bank; +@@ -3435,13 +3427,17 @@ static int rockchip_interrupts_register(struct platform_device *pdev, + gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; + gc->wake_enabled = IRQ_MSK(bank->nr_pins); + ++ /* ++ * Linux assumes that all interrupts start out disabled/masked. ++ * Our driver only uses the concept of masked and always keeps ++ * things enabled, so for us that's all masked and all enabled. ++ */ ++ writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); ++ writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); ++ gc->mask_cache = 0xffffffff; ++ + irq_set_chained_handler_and_data(bank->irq, + rockchip_irq_demux, bank); +- +- /* map the gpio irqs here, when the clock is still running */ +- for (j = 0 ; j < 32 ; j++) +- irq_create_mapping(bank->domain, j); +- + clk_disable(bank->clk); + } + +-- +2.31.1 + diff --git a/patches.suse/pinctrl-rockchip-do-coding-style-for-mux-route-struc.patch b/patches.suse/pinctrl-rockchip-do-coding-style-for-mux-route-struc.patch new file mode 100644 index 0000000..6a961b0 --- /dev/null +++ b/patches.suse/pinctrl-rockchip-do-coding-style-for-mux-route-struc.patch @@ -0,0 +1,760 @@ +From: Jianqun Xu +Date: Tue, 20 Apr 2021 17:12:40 +0800 +Subject: pinctrl: rockchip: do coding style for mux route struct + +Git-commit: fe202ea8e5b170ef7b3741da885e8cb7bae1106e +Patch-mainline: v5.13-rc1 +References: bsc#1192217 + +The mux route tables take many lines for each SoC, and it will be more +instances for newly SoC, that makes the file size increase larger. + +This patch only do coding style for mux route struct, by adding a new +definition and replace the structs by script which supplied by +huangtao@rock-chips.com + +sed -i -e " +/static struct rockchip_mux_route_data /bcheck +b +:append-next-line +N +:check +/^[^;]*$/bappend-next-line +s/[[:blank:]]*.bank_num = \([[:digit:]]*,\)\n/\tRK_MUXROUTE_SAME(\1/g +s/[[:blank:]]*.pin =[[:blank:]]*0,\n/ RK_PA0,/g +s/[[:blank:]]*.pin =[[:blank:]]*1,\n/ RK_PA1,/g +s/[[:blank:]]*.pin =[[:blank:]]*2,\n/ RK_PA2,/g +s/[[:blank:]]*.pin =[[:blank:]]*3,\n/ RK_PA3,/g +s/[[:blank:]]*.pin =[[:blank:]]*4,\n/ RK_PA4,/g +s/[[:blank:]]*.pin =[[:blank:]]*5,\n/ RK_PA5,/g +s/[[:blank:]]*.pin =[[:blank:]]*6,\n/ RK_PA6,/g +s/[[:blank:]]*.pin =[[:blank:]]*7,\n/ RK_PA7,/g +s/[[:blank:]]*.pin =[[:blank:]]*8,\n/ RK_PB0,/g +s/[[:blank:]]*.pin =[[:blank:]]*9,\n/ RK_PB1,/g +s/[[:blank:]]*.pin =[[:blank:]]*10,\n/ RK_PB2,/g +s/[[:blank:]]*.pin =[[:blank:]]*11,\n/ RK_PB3,/g +s/[[:blank:]]*.pin =[[:blank:]]*12,\n/ RK_PB4,/g +s/[[:blank:]]*.pin =[[:blank:]]*13,\n/ RK_PB5,/g +s/[[:blank:]]*.pin =[[:blank:]]*14,\n/ RK_PB6,/g +s/[[:blank:]]*.pin =[[:blank:]]*15,\n/ RK_PB7,/g +s/[[:blank:]]*.pin =[[:blank:]]*16,\n/ RK_PC0,/g +s/[[:blank:]]*.pin =[[:blank:]]*17,\n/ RK_PC1,/g +s/[[:blank:]]*.pin =[[:blank:]]*18,\n/ RK_PC2,/g +s/[[:blank:]]*.pin =[[:blank:]]*19,\n/ RK_PC3,/g +s/[[:blank:]]*.pin =[[:blank:]]*20,\n/ RK_PC4,/g +s/[[:blank:]]*.pin =[[:blank:]]*21,\n/ RK_PC5,/g +s/[[:blank:]]*.pin =[[:blank:]]*22,\n/ RK_PC6,/g +s/[[:blank:]]*.pin =[[:blank:]]*23,\n/ RK_PC7,/g +s/[[:blank:]]*.pin =[[:blank:]]*24,\n/ RK_PD0,/g +s/[[:blank:]]*.pin =[[:blank:]]*25,\n/ RK_PD1,/g +s/[[:blank:]]*.pin =[[:blank:]]*26,\n/ RK_PD2,/g +s/[[:blank:]]*.pin =[[:blank:]]*27,\n/ RK_PD3,/g +s/[[:blank:]]*.pin =[[:blank:]]*28,\n/ RK_PD4,/g +s/[[:blank:]]*.pin =[[:blank:]]*29,\n/ RK_PD5,/g +s/[[:blank:]]*.pin =[[:blank:]]*30,\n/ RK_PD6,/g +s/[[:blank:]]*.pin =[[:blank:]]*31,\n/ RK_PD7,/g +s/[[:blank:]]*.func = \([[:digit:]]*,\)\n/ \1/g +s/[[:blank:]]*.route_location =[[:blank:]]*\([[:print:]]*,\)\n//g +s/[[:blank:]]*.route_offset = \(0x[[:xdigit:]]*,\)\n/ \1/g +s/[[:blank:]]*.route_val =[[:blank:]]*\([[:print:]]*\),\n/ \1),/g +s/\t{\n//g +s/\t}, {\n//g +s/\t},//g +s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),\n/\tRK_MUXROUTE_SAME(\2), \1\n/g +s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),/\tRK_MUXROUTE_SAME(\2), \1\n/g +" drivers/pinctrl/pinctrl-rockchip.c + +Reviewed-by: Heiko Stuebner +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20210420091240.1246429-1-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.c | 650 ++++------------------------- + 1 file changed, 80 insertions(+), 570 deletions(-) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index 05128f53824c..94fa18cdcd8d 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -831,597 +831,107 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, + } + + static struct rockchip_mux_route_data px30_mux_route_data[] = { +- { +- /* cif-d2m0 */ +- .bank_num = 2, +- .pin = 0, +- .func = 1, +- .route_offset = 0x184, +- .route_val = BIT(16 + 7), +- }, { +- /* cif-d2m1 */ +- .bank_num = 3, +- .pin = 3, +- .func = 3, +- .route_offset = 0x184, +- .route_val = BIT(16 + 7) | BIT(7), +- }, { +- /* pdm-m0 */ +- .bank_num = 3, +- .pin = 22, +- .func = 2, +- .route_offset = 0x184, +- .route_val = BIT(16 + 8), +- }, { +- /* pdm-m1 */ +- .bank_num = 2, +- .pin = 22, +- .func = 1, +- .route_offset = 0x184, +- .route_val = BIT(16 + 8) | BIT(8), +- }, { +- /* uart2-rxm0 */ +- .bank_num = 1, +- .pin = 27, +- .func = 2, +- .route_offset = 0x184, +- .route_val = BIT(16 + 10), +- }, { +- /* uart2-rxm1 */ +- .bank_num = 2, +- .pin = 14, +- .func = 2, +- .route_offset = 0x184, +- .route_val = BIT(16 + 10) | BIT(10), +- }, { +- /* uart3-rxm0 */ +- .bank_num = 0, +- .pin = 17, +- .func = 2, +- .route_offset = 0x184, +- .route_val = BIT(16 + 9), +- }, { +- /* uart3-rxm1 */ +- .bank_num = 1, +- .pin = 15, +- .func = 2, +- .route_offset = 0x184, +- .route_val = BIT(16 + 9) | BIT(9), +- }, ++ RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */ ++ RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */ ++ RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */ ++ RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */ ++ RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */ ++ RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */ ++ RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */ ++ RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */ + }; + + static struct rockchip_mux_route_data rk3128_mux_route_data[] = { +- { +- /* spi-0 */ +- .bank_num = 1, +- .pin = 10, +- .func = 1, +- .route_offset = 0x144, +- .route_val = BIT(16 + 3) | BIT(16 + 4), +- }, { +- /* spi-1 */ +- .bank_num = 1, +- .pin = 27, +- .func = 3, +- .route_offset = 0x144, +- .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), +- }, { +- /* spi-2 */ +- .bank_num = 0, +- .pin = 13, +- .func = 2, +- .route_offset = 0x144, +- .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), +- }, { +- /* i2s-0 */ +- .bank_num = 1, +- .pin = 5, +- .func = 1, +- .route_offset = 0x144, +- .route_val = BIT(16 + 5), +- }, { +- /* i2s-1 */ +- .bank_num = 0, +- .pin = 14, +- .func = 1, +- .route_offset = 0x144, +- .route_val = BIT(16 + 5) | BIT(5), +- }, { +- /* emmc-0 */ +- .bank_num = 1, +- .pin = 22, +- .func = 2, +- .route_offset = 0x144, +- .route_val = BIT(16 + 6), +- }, { +- /* emmc-1 */ +- .bank_num = 2, +- .pin = 4, +- .func = 2, +- .route_offset = 0x144, +- .route_val = BIT(16 + 6) | BIT(6), +- }, ++ RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ ++ RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ ++ RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ ++ RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */ ++ RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */ ++ RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */ ++ RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ + }; + + static struct rockchip_mux_route_data rk3188_mux_route_data[] = { +- { +- /* non-iomuxed emmc/flash pins on flash-dqs */ +- .bank_num = 0, +- .pin = 24, +- .func = 1, +- .route_location = ROCKCHIP_ROUTE_GRF, +- .route_offset = 0xa0, +- .route_val = BIT(16 + 11), +- }, { +- /* non-iomuxed emmc/flash pins on emmc-clk */ +- .bank_num = 0, +- .pin = 24, +- .func = 2, +- .route_location = ROCKCHIP_ROUTE_GRF, +- .route_offset = 0xa0, +- .route_val = BIT(16 + 11) | BIT(11), +- }, ++ RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ ++ RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ + }; + + static struct rockchip_mux_route_data rk3228_mux_route_data[] = { +- { +- /* pwm0-0 */ +- .bank_num = 0, +- .pin = 26, +- .func = 1, +- .route_offset = 0x50, +- .route_val = BIT(16), +- }, { +- /* pwm0-1 */ +- .bank_num = 3, +- .pin = 21, +- .func = 1, +- .route_offset = 0x50, +- .route_val = BIT(16) | BIT(0), +- }, { +- /* pwm1-0 */ +- .bank_num = 0, +- .pin = 27, +- .func = 1, +- .route_offset = 0x50, +- .route_val = BIT(16 + 1), +- }, { +- /* pwm1-1 */ +- .bank_num = 0, +- .pin = 30, +- .func = 2, +- .route_offset = 0x50, +- .route_val = BIT(16 + 1) | BIT(1), +- }, { +- /* pwm2-0 */ +- .bank_num = 0, +- .pin = 28, +- .func = 1, +- .route_offset = 0x50, +- .route_val = BIT(16 + 2), +- }, { +- /* pwm2-1 */ +- .bank_num = 1, +- .pin = 12, +- .func = 2, +- .route_offset = 0x50, +- .route_val = BIT(16 + 2) | BIT(2), +- }, { +- /* pwm3-0 */ +- .bank_num = 3, +- .pin = 26, +- .func = 1, +- .route_offset = 0x50, +- .route_val = BIT(16 + 3), +- }, { +- /* pwm3-1 */ +- .bank_num = 1, +- .pin = 11, +- .func = 2, +- .route_offset = 0x50, +- .route_val = BIT(16 + 3) | BIT(3), +- }, { +- /* sdio-0_d0 */ +- .bank_num = 1, +- .pin = 1, +- .func = 1, +- .route_offset = 0x50, +- .route_val = BIT(16 + 4), +- }, { +- /* sdio-1_d0 */ +- .bank_num = 3, +- .pin = 2, +- .func = 1, +- .route_offset = 0x50, +- .route_val = BIT(16 + 4) | BIT(4), +- }, { +- /* spi-0_rx */ +- .bank_num = 0, +- .pin = 13, +- .func = 2, +- .route_offset = 0x50, +- .route_val = BIT(16 + 5), +- }, { +- /* spi-1_rx */ +- .bank_num = 2, +- .pin = 0, +- .func = 2, +- .route_offset = 0x50, +- .route_val = BIT(16 + 5) | BIT(5), +- }, { +- /* emmc-0_cmd */ +- .bank_num = 1, +- .pin = 22, +- .func = 2, +- .route_offset = 0x50, +- .route_val = BIT(16 + 7), +- }, { +- /* emmc-1_cmd */ +- .bank_num = 2, +- .pin = 4, +- .func = 2, +- .route_offset = 0x50, +- .route_val = BIT(16 + 7) | BIT(7), +- }, { +- /* uart2-0_rx */ +- .bank_num = 1, +- .pin = 19, +- .func = 2, +- .route_offset = 0x50, +- .route_val = BIT(16 + 8), +- }, { +- /* uart2-1_rx */ +- .bank_num = 1, +- .pin = 10, +- .func = 2, +- .route_offset = 0x50, +- .route_val = BIT(16 + 8) | BIT(8), +- }, { +- /* uart1-0_rx */ +- .bank_num = 1, +- .pin = 10, +- .func = 1, +- .route_offset = 0x50, +- .route_val = BIT(16 + 11), +- }, { +- /* uart1-1_rx */ +- .bank_num = 3, +- .pin = 13, +- .func = 1, +- .route_offset = 0x50, +- .route_val = BIT(16 + 11) | BIT(11), +- }, ++ RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ ++ RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ ++ RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ ++ RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */ ++ RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */ ++ RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */ ++ RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */ ++ RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */ ++ RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */ ++ RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */ ++ RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */ ++ RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */ ++ RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */ ++ RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */ ++ RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */ ++ RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */ ++ RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */ ++ RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ + }; + + static struct rockchip_mux_route_data rk3288_mux_route_data[] = { +- { +- /* edphdmi_cecinoutt1 */ +- .bank_num = 7, +- .pin = 16, +- .func = 2, +- .route_offset = 0x264, +- .route_val = BIT(16 + 12) | BIT(12), +- }, { +- /* edphdmi_cecinout */ +- .bank_num = 7, +- .pin = 23, +- .func = 4, +- .route_offset = 0x264, +- .route_val = BIT(16 + 12), +- }, ++ RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ ++ RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ + }; + + static struct rockchip_mux_route_data rk3308_mux_route_data[] = { +- { +- /* rtc_clk */ +- .bank_num = 0, +- .pin = 19, +- .func = 1, +- .route_offset = 0x314, +- .route_val = BIT(16 + 0) | BIT(0), +- }, { +- /* uart2_rxm0 */ +- .bank_num = 1, +- .pin = 22, +- .func = 2, +- .route_offset = 0x314, +- .route_val = BIT(16 + 2) | BIT(16 + 3), +- }, { +- /* uart2_rxm1 */ +- .bank_num = 4, +- .pin = 26, +- .func = 2, +- .route_offset = 0x314, +- .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), +- }, { +- /* i2c3_sdam0 */ +- .bank_num = 0, +- .pin = 15, +- .func = 2, +- .route_offset = 0x608, +- .route_val = BIT(16 + 8) | BIT(16 + 9), +- }, { +- /* i2c3_sdam1 */ +- .bank_num = 3, +- .pin = 12, +- .func = 2, +- .route_offset = 0x608, +- .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), +- }, { +- /* i2c3_sdam2 */ +- .bank_num = 2, +- .pin = 0, +- .func = 3, +- .route_offset = 0x608, +- .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), +- }, { +- /* i2s-8ch-1-sclktxm0 */ +- .bank_num = 1, +- .pin = 3, +- .func = 2, +- .route_offset = 0x308, +- .route_val = BIT(16 + 3), +- }, { +- /* i2s-8ch-1-sclkrxm0 */ +- .bank_num = 1, +- .pin = 4, +- .func = 2, +- .route_offset = 0x308, +- .route_val = BIT(16 + 3), +- }, { +- /* i2s-8ch-1-sclktxm1 */ +- .bank_num = 1, +- .pin = 13, +- .func = 2, +- .route_offset = 0x308, +- .route_val = BIT(16 + 3) | BIT(3), +- }, { +- /* i2s-8ch-1-sclkrxm1 */ +- .bank_num = 1, +- .pin = 14, +- .func = 2, +- .route_offset = 0x308, +- .route_val = BIT(16 + 3) | BIT(3), +- }, { +- /* pdm-clkm0 */ +- .bank_num = 1, +- .pin = 4, +- .func = 3, +- .route_offset = 0x308, +- .route_val = BIT(16 + 12) | BIT(16 + 13), +- }, { +- /* pdm-clkm1 */ +- .bank_num = 1, +- .pin = 14, +- .func = 4, +- .route_offset = 0x308, +- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), +- }, { +- /* pdm-clkm2 */ +- .bank_num = 2, +- .pin = 6, +- .func = 2, +- .route_offset = 0x308, +- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), +- }, { +- /* pdm-clkm-m2 */ +- .bank_num = 2, +- .pin = 4, +- .func = 3, +- .route_offset = 0x600, +- .route_val = BIT(16 + 2) | BIT(2), +- }, { +- /* spi1_miso */ +- .bank_num = 3, +- .pin = 10, +- .func = 3, +- .route_offset = 0x314, +- .route_val = BIT(16 + 9), +- }, { +- /* spi1_miso_m1 */ +- .bank_num = 2, +- .pin = 4, +- .func = 2, +- .route_offset = 0x314, +- .route_val = BIT(16 + 9) | BIT(9), +- }, { +- /* owire_m0 */ +- .bank_num = 0, +- .pin = 11, +- .func = 3, +- .route_offset = 0x314, +- .route_val = BIT(16 + 10) | BIT(16 + 11), +- }, { +- /* owire_m1 */ +- .bank_num = 1, +- .pin = 22, +- .func = 7, +- .route_offset = 0x314, +- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), +- }, { +- /* owire_m2 */ +- .bank_num = 2, +- .pin = 2, +- .func = 5, +- .route_offset = 0x314, +- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), +- }, { +- /* can_rxd_m0 */ +- .bank_num = 0, +- .pin = 11, +- .func = 2, +- .route_offset = 0x314, +- .route_val = BIT(16 + 12) | BIT(16 + 13), +- }, { +- /* can_rxd_m1 */ +- .bank_num = 1, +- .pin = 22, +- .func = 5, +- .route_offset = 0x314, +- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), +- }, { +- /* can_rxd_m2 */ +- .bank_num = 2, +- .pin = 2, +- .func = 4, +- .route_offset = 0x314, +- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), +- }, { +- /* mac_rxd0_m0 */ +- .bank_num = 1, +- .pin = 20, +- .func = 3, +- .route_offset = 0x314, +- .route_val = BIT(16 + 14), +- }, { +- /* mac_rxd0_m1 */ +- .bank_num = 4, +- .pin = 2, +- .func = 2, +- .route_offset = 0x314, +- .route_val = BIT(16 + 14) | BIT(14), +- }, { +- /* uart3_rx */ +- .bank_num = 3, +- .pin = 12, +- .func = 4, +- .route_offset = 0x314, +- .route_val = BIT(16 + 15), +- }, { +- /* uart3_rx_m1 */ +- .bank_num = 0, +- .pin = 17, +- .func = 3, +- .route_offset = 0x314, +- .route_val = BIT(16 + 15) | BIT(15), +- }, ++ RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ ++ RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ ++ RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ ++ RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */ ++ RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */ ++ RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */ ++ RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ ++ RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ ++ RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ ++ RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ ++ RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ ++ RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ ++ RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ ++ RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ ++ RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */ ++ RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */ ++ RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */ ++ RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */ ++ RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */ ++ RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */ ++ RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */ ++ RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */ ++ RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */ ++ RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */ ++ RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */ ++ RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */ + }; + + static struct rockchip_mux_route_data rk3328_mux_route_data[] = { +- { +- /* uart2dbg_rxm0 */ +- .bank_num = 1, +- .pin = 1, +- .func = 2, +- .route_offset = 0x50, +- .route_val = BIT(16) | BIT(16 + 1), +- }, { +- /* uart2dbg_rxm1 */ +- .bank_num = 2, +- .pin = 1, +- .func = 1, +- .route_offset = 0x50, +- .route_val = BIT(16) | BIT(16 + 1) | BIT(0), +- }, { +- /* gmac-m1_rxd0 */ +- .bank_num = 1, +- .pin = 11, +- .func = 2, +- .route_offset = 0x50, +- .route_val = BIT(16 + 2) | BIT(2), +- }, { +- /* gmac-m1-optimized_rxd3 */ +- .bank_num = 1, +- .pin = 14, +- .func = 2, +- .route_offset = 0x50, +- .route_val = BIT(16 + 10) | BIT(10), +- }, { +- /* pdm_sdi0m0 */ +- .bank_num = 2, +- .pin = 19, +- .func = 2, +- .route_offset = 0x50, +- .route_val = BIT(16 + 3), +- }, { +- /* pdm_sdi0m1 */ +- .bank_num = 1, +- .pin = 23, +- .func = 3, +- .route_offset = 0x50, +- .route_val = BIT(16 + 3) | BIT(3), +- }, { +- /* spi_rxdm2 */ +- .bank_num = 3, +- .pin = 2, +- .func = 4, +- .route_offset = 0x50, +- .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), +- }, { +- /* i2s2_sdim0 */ +- .bank_num = 1, +- .pin = 24, +- .func = 1, +- .route_offset = 0x50, +- .route_val = BIT(16 + 6), +- }, { +- /* i2s2_sdim1 */ +- .bank_num = 3, +- .pin = 2, +- .func = 6, +- .route_offset = 0x50, +- .route_val = BIT(16 + 6) | BIT(6), +- }, { +- /* card_iom1 */ +- .bank_num = 2, +- .pin = 22, +- .func = 3, +- .route_offset = 0x50, +- .route_val = BIT(16 + 7) | BIT(7), +- }, { +- /* tsp_d5m1 */ +- .bank_num = 2, +- .pin = 16, +- .func = 3, +- .route_offset = 0x50, +- .route_val = BIT(16 + 8) | BIT(8), +- }, { +- /* cif_data5m1 */ +- .bank_num = 2, +- .pin = 16, +- .func = 4, +- .route_offset = 0x50, +- .route_val = BIT(16 + 9) | BIT(9), +- }, ++ RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ ++ RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ ++ RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ ++ RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */ ++ RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */ ++ RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */ ++ RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */ ++ RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */ ++ RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */ ++ RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */ ++ RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */ ++ RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ + }; + + static struct rockchip_mux_route_data rk3399_mux_route_data[] = { +- { +- /* uart2dbga_rx */ +- .bank_num = 4, +- .pin = 8, +- .func = 2, +- .route_offset = 0xe21c, +- .route_val = BIT(16 + 10) | BIT(16 + 11), +- }, { +- /* uart2dbgb_rx */ +- .bank_num = 4, +- .pin = 16, +- .func = 2, +- .route_offset = 0xe21c, +- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), +- }, { +- /* uart2dbgc_rx */ +- .bank_num = 4, +- .pin = 19, +- .func = 1, +- .route_offset = 0xe21c, +- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), +- }, { +- /* pcie_clkreqn */ +- .bank_num = 2, +- .pin = 26, +- .func = 2, +- .route_offset = 0xe21c, +- .route_val = BIT(16 + 14), +- }, { +- /* pcie_clkreqnb */ +- .bank_num = 4, +- .pin = 24, +- .func = 1, +- .route_offset = 0xe21c, +- .route_val = BIT(16 + 14) | BIT(14), +- }, ++ RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ ++ RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ ++ RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ ++ RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */ ++ RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ + }; + + static struct rockchip_mux_route_data rk3568_mux_route_data[] = { +-- +2.31.1 + diff --git a/patches.suse/pinctrl-rockchip-drop-the-gpio-related-codes.patch b/patches.suse/pinctrl-rockchip-drop-the-gpio-related-codes.patch new file mode 100644 index 0000000..71d0de2 --- /dev/null +++ b/patches.suse/pinctrl-rockchip-drop-the-gpio-related-codes.patch @@ -0,0 +1,768 @@ +From: Jianqun Xu +Date: Mon, 16 Aug 2021 09:21:46 +0800 +Subject: pinctrl/rockchip: drop the gpio related codes + +Git-commit: 9ce9a02039de72ec8af1bd4bff14f1780337ffcc +Patch-mainline: v5.15-rc1 +References: bsc#1192217 + +With the patch to separate the gpio driver from the pinctrl driver, now +the pinctrl-rockchip can drop the gpio related codes now. + +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20210816012146.1119289-1-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.c | 643 ------------------------------------- + 1 file changed, 17 insertions(+), 626 deletions(-) + +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -21,8 +21,8 @@ + #include + #include + #include +-#include + #include ++#include + #include + #include + #include +@@ -39,20 +39,6 @@ + #include "pinconf.h" + #include "pinctrl-rockchip.h" + +-/* GPIO control registers */ +-#define GPIO_SWPORT_DR 0x00 +-#define GPIO_SWPORT_DDR 0x04 +-#define GPIO_INTEN 0x30 +-#define GPIO_INTMASK 0x34 +-#define GPIO_INTTYPE_LEVEL 0x38 +-#define GPIO_INT_POLARITY 0x3c +-#define GPIO_INT_STATUS 0x40 +-#define GPIO_INT_RAWSTATUS 0x44 +-#define GPIO_DEBOUNCE 0x48 +-#define GPIO_PORTS_EOI 0x4c +-#define GPIO_EXT_PORT 0x50 +-#define GPIO_LS_SYNC 0x60 +- + /** + * Generate a bitmask for setting a value (v) with a write mask bit in hiword + * register 31:16 area. +@@ -2071,73 +2057,11 @@ static int rockchip_pmx_set(struct pinct + return 0; + } + +-static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +-{ +- struct rockchip_pin_bank *bank = gpiochip_get_data(chip); +- u32 data; +- +- data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); +- +- return !(data & BIT(offset)); +-} +- +-/* +- * The calls to gpio_direction_output() and gpio_direction_input() +- * leads to this function call (via the pinctrl_gpio_direction_{input|output}() +- * function called from the gpiolib interface). +- */ +-static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, +- int pin, bool input) +-{ +- struct rockchip_pin_bank *bank; +- int ret; +- unsigned long flags; +- u32 data; +- +- bank = gpiochip_get_data(chip); +- +- ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); +- if (ret < 0) +- return ret; +- +- raw_spin_lock_irqsave(&bank->slock, flags); +- +- data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); +- /* set bit to 1 for output, 0 for input */ +- if (!input) +- data |= BIT(pin); +- else +- data &= ~BIT(pin); +- writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); +- +- raw_spin_unlock_irqrestore(&bank->slock, flags); +- +- return 0; +-} +- +-static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, +- struct pinctrl_gpio_range *range, +- unsigned offset, bool input) +-{ +- struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); +- struct gpio_chip *chip; +- int pin; +- +- chip = range->gc; +- pin = offset - chip->base; +- dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", +- offset, range->name, pin, input ? "input" : "output"); +- +- return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, +- input); +-} +- + static const struct pinmux_ops rockchip_pmx_ops = { + .get_functions_count = rockchip_pmx_get_funcs_count, + .get_function_name = rockchip_pmx_get_func_name, + .get_function_groups = rockchip_pmx_get_groups, + .set_mux = rockchip_pmx_set, +- .gpio_set_direction = rockchip_pmx_gpio_set_direction, + }; + + /* +@@ -2168,15 +2092,13 @@ static bool rockchip_pinconf_pull_valid( + return false; + } + +-static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); +-static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); +- + /* set the pin config settings for a specified pin */ + static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned num_configs) + { + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct rockchip_pin_bank *bank = pin_to_bank(info, pin); ++ struct gpio_chip *gpio = &bank->gpio_chip; + enum pin_config_param param; + u32 arg; + int i; +@@ -2209,10 +2131,13 @@ static int rockchip_pinconf_set(struct p + return rc; + break; + case PIN_CONFIG_OUTPUT: +- rockchip_gpio_set(&bank->gpio_chip, +- pin - bank->pin_base, arg); +- rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, +- pin - bank->pin_base, false); ++ rc = rockchip_set_mux(bank, pin - bank->pin_base, ++ RK_FUNC_GPIO); ++ if (rc != RK_FUNC_GPIO) ++ return -EINVAL; ++ ++ rc = gpio->direction_output(gpio, pin - bank->pin_base, ++ arg); + if (rc) + return rc; + break; +@@ -2250,6 +2175,7 @@ static int rockchip_pinconf_get(struct p + { + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct rockchip_pin_bank *bank = pin_to_bank(info, pin); ++ struct gpio_chip *gpio = &bank->gpio_chip; + enum pin_config_param param = pinconf_to_config_param(*config); + u16 arg; + int rc; +@@ -2278,7 +2204,7 @@ static int rockchip_pinconf_get(struct p + if (rc != RK_FUNC_GPIO) + return -EINVAL; + +- rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); ++ rc = gpio->get(gpio, pin - bank->pin_base); + if (rc < 0) + return rc; + +@@ -2516,7 +2442,7 @@ static int rockchip_pinctrl_register(str + ctrldesc->npins = info->ctrl->nr_pins; + + pdesc = pindesc; +- for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { ++ for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { + pin_bank = &info->ctrl->pin_banks[bank]; + for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { + pdesc->number = k; +@@ -2536,524 +2462,7 @@ static int rockchip_pinctrl_register(str + return PTR_ERR(info->pctl_dev); + } + +- for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { +- pin_bank = &info->ctrl->pin_banks[bank]; +- pin_bank->grange.name = pin_bank->name; +- pin_bank->grange.id = bank; +- pin_bank->grange.pin_base = pin_bank->pin_base; +- pin_bank->grange.base = pin_bank->gpio_chip.base; +- pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; +- pin_bank->grange.gc = &pin_bank->gpio_chip; +- pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); +- } +- +- return 0; +-} +- +-/* +- * GPIO handling +- */ +- +-static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) +-{ +- struct rockchip_pin_bank *bank = gpiochip_get_data(gc); +- void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; +- unsigned long flags; +- u32 data; +- +- raw_spin_lock_irqsave(&bank->slock, flags); +- +- data = readl(reg); +- data &= ~BIT(offset); +- if (value) +- data |= BIT(offset); +- writel(data, reg); +- +- raw_spin_unlock_irqrestore(&bank->slock, flags); +-} +- +-/* +- * Returns the level of the pin for input direction and setting of the DR +- * register for output gpios. +- */ +-static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) +-{ +- struct rockchip_pin_bank *bank = gpiochip_get_data(gc); +- u32 data; +- +- data = readl(bank->reg_base + GPIO_EXT_PORT); +- data >>= offset; +- data &= 1; +- return data; +-} +- +-/* +- * gpiolib gpio_direction_input callback function. The setting of the pin +- * mux function as 'gpio input' will be handled by the pinctrl subsystem +- * interface. +- */ +-static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) +-{ +- return pinctrl_gpio_direction_input(gc->base + offset); +-} +- +-/* +- * gpiolib gpio_direction_output callback function. The setting of the pin +- * mux function as 'gpio output' will be handled by the pinctrl subsystem +- * interface. +- */ +-static int rockchip_gpio_direction_output(struct gpio_chip *gc, +- unsigned offset, int value) +-{ +- rockchip_gpio_set(gc, offset, value); +- return pinctrl_gpio_direction_output(gc->base + offset); +-} +- +-static void rockchip_gpio_set_debounce(struct gpio_chip *gc, +- unsigned int offset, bool enable) +-{ +- struct rockchip_pin_bank *bank = gpiochip_get_data(gc); +- void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; +- unsigned long flags; +- u32 data; +- +- raw_spin_lock_irqsave(&bank->slock, flags); +- +- data = readl(reg); +- if (enable) +- data |= BIT(offset); +- else +- data &= ~BIT(offset); +- writel(data, reg); +- +- raw_spin_unlock_irqrestore(&bank->slock, flags); +-} +- +-/* +- * gpiolib set_config callback function. The setting of the pin +- * mux function as 'gpio output' will be handled by the pinctrl subsystem +- * interface. +- */ +-static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, +- unsigned long config) +-{ +- enum pin_config_param param = pinconf_to_config_param(config); +- +- switch (param) { +- case PIN_CONFIG_INPUT_DEBOUNCE: +- rockchip_gpio_set_debounce(gc, offset, true); +- /* +- * Rockchip's gpio could only support up to one period +- * of the debounce clock(pclk), which is far away from +- * satisftying the requirement, as pclk is usually near +- * 100MHz shared by all peripherals. So the fact is it +- * has crippled debounce capability could only be useful +- * to prevent any spurious glitches from waking up the system +- * if the gpio is conguired as wakeup interrupt source. Let's +- * still return -ENOTSUPP as before, to make sure the caller +- * of gpiod_set_debounce won't change its behaviour. +- */ +- return -ENOTSUPP; +- default: +- return -ENOTSUPP; +- } +-} +- +-/* +- * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin +- * and a virtual IRQ, if not already present. +- */ +-static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) +-{ +- struct rockchip_pin_bank *bank = gpiochip_get_data(gc); +- unsigned int virq; +- +- if (!bank->domain) +- return -ENXIO; +- +- virq = irq_create_mapping(bank->domain, offset); +- +- return (virq) ? : -ENXIO; +-} +- +-static const struct gpio_chip rockchip_gpiolib_chip = { +- .request = gpiochip_generic_request, +- .free = gpiochip_generic_free, +- .set = rockchip_gpio_set, +- .get = rockchip_gpio_get, +- .get_direction = rockchip_gpio_get_direction, +- .direction_input = rockchip_gpio_direction_input, +- .direction_output = rockchip_gpio_direction_output, +- .set_config = rockchip_gpio_set_config, +- .to_irq = rockchip_gpio_to_irq, +- .owner = THIS_MODULE, +-}; +- +-/* +- * Interrupt handling +- */ +- +-static void rockchip_irq_demux(struct irq_desc *desc) +-{ +- struct irq_chip *chip = irq_desc_get_chip(desc); +- struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); +- u32 pend; +- +- dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); +- +- chained_irq_enter(chip, desc); +- +- pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); +- +- while (pend) { +- unsigned int irq, virq; +- +- irq = __ffs(pend); +- pend &= ~BIT(irq); +- virq = irq_find_mapping(bank->domain, irq); +- +- if (!virq) { +- dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); +- continue; +- } +- +- dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); +- +- /* +- * Triggering IRQ on both rising and falling edge +- * needs manual intervention. +- */ +- if (bank->toggle_edge_mode & BIT(irq)) { +- u32 data, data_old, polarity; +- unsigned long flags; +- +- data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); +- do { +- raw_spin_lock_irqsave(&bank->slock, flags); +- +- polarity = readl_relaxed(bank->reg_base + +- GPIO_INT_POLARITY); +- if (data & BIT(irq)) +- polarity &= ~BIT(irq); +- else +- polarity |= BIT(irq); +- writel(polarity, +- bank->reg_base + GPIO_INT_POLARITY); +- +- raw_spin_unlock_irqrestore(&bank->slock, flags); +- +- data_old = data; +- data = readl_relaxed(bank->reg_base + +- GPIO_EXT_PORT); +- } while ((data & BIT(irq)) != (data_old & BIT(irq))); +- } +- +- generic_handle_irq(virq); +- } +- +- chained_irq_exit(chip, desc); +-} +- +-static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) +-{ +- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); +- struct rockchip_pin_bank *bank = gc->private; +- u32 mask = BIT(d->hwirq); +- u32 polarity; +- u32 level; +- u32 data; +- unsigned long flags; +- int ret; +- +- /* make sure the pin is configured as gpio input */ +- ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); +- if (ret < 0) +- return ret; +- +- raw_spin_lock_irqsave(&bank->slock, flags); +- +- data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); +- data &= ~mask; +- writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); +- +- raw_spin_unlock_irqrestore(&bank->slock, flags); +- +- if (type & IRQ_TYPE_EDGE_BOTH) +- irq_set_handler_locked(d, handle_edge_irq); +- else +- irq_set_handler_locked(d, handle_level_irq); +- +- raw_spin_lock_irqsave(&bank->slock, flags); +- irq_gc_lock(gc); +- +- level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); +- polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); +- +- switch (type) { +- case IRQ_TYPE_EDGE_BOTH: +- bank->toggle_edge_mode |= mask; +- level |= mask; +- +- /* +- * Determine gpio state. If 1 next interrupt should be falling +- * otherwise rising. +- */ +- data = readl(bank->reg_base + GPIO_EXT_PORT); +- if (data & mask) +- polarity &= ~mask; +- else +- polarity |= mask; +- break; +- case IRQ_TYPE_EDGE_RISING: +- bank->toggle_edge_mode &= ~mask; +- level |= mask; +- polarity |= mask; +- break; +- case IRQ_TYPE_EDGE_FALLING: +- bank->toggle_edge_mode &= ~mask; +- level |= mask; +- polarity &= ~mask; +- break; +- case IRQ_TYPE_LEVEL_HIGH: +- bank->toggle_edge_mode &= ~mask; +- level &= ~mask; +- polarity |= mask; +- break; +- case IRQ_TYPE_LEVEL_LOW: +- bank->toggle_edge_mode &= ~mask; +- level &= ~mask; +- polarity &= ~mask; +- break; +- default: +- irq_gc_unlock(gc); +- raw_spin_unlock_irqrestore(&bank->slock, flags); +- return -EINVAL; +- } +- +- writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); +- writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); +- +- irq_gc_unlock(gc); +- raw_spin_unlock_irqrestore(&bank->slock, flags); +- +- return 0; +-} +- +-static void rockchip_irq_suspend(struct irq_data *d) +-{ +- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); +- struct rockchip_pin_bank *bank = gc->private; +- +- bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); +- irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); +-} +- +-static void rockchip_irq_resume(struct irq_data *d) +-{ +- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); +- struct rockchip_pin_bank *bank = gc->private; +- +- irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); +-} +- +-static void rockchip_irq_enable(struct irq_data *d) +-{ +- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); +- struct rockchip_pin_bank *bank = gc->private; +- +- irq_gc_mask_clr_bit(d); +-} +- +-static void rockchip_irq_disable(struct irq_data *d) +-{ +- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); +- struct rockchip_pin_bank *bank = gc->private; +- +- irq_gc_mask_set_bit(d); +-} +- +-static int rockchip_interrupts_register(struct platform_device *pdev, +- struct rockchip_pinctrl *info) +-{ +- struct rockchip_pin_ctrl *ctrl = info->ctrl; +- struct rockchip_pin_bank *bank = ctrl->pin_banks; +- unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; +- struct irq_chip_generic *gc; +- int ret; +- int i; +- +- for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { +- if (!bank->valid) { +- dev_warn(&pdev->dev, "bank %s is not valid\n", +- bank->name); +- continue; +- } +- +- bank->domain = irq_domain_add_linear(bank->of_node, 32, +- &irq_generic_chip_ops, NULL); +- if (!bank->domain) { +- dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", +- bank->name); +- continue; +- } +- +- ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, +- "rockchip_gpio_irq", handle_level_irq, +- clr, 0, 0); +- if (ret) { +- dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", +- bank->name); +- irq_domain_remove(bank->domain); +- continue; +- } +- +- gc = irq_get_domain_generic_chip(bank->domain, 0); +- gc->reg_base = bank->reg_base; +- gc->private = bank; +- gc->chip_types[0].regs.mask = GPIO_INTMASK; +- gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; +- gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; +- gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; +- gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; +- gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; +- gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; +- gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; +- gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; +- gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; +- gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; +- gc->wake_enabled = IRQ_MSK(bank->nr_pins); +- +- /* +- * Linux assumes that all interrupts start out disabled/masked. +- * Our driver only uses the concept of masked and always keeps +- * things enabled, so for us that's all masked and all enabled. +- */ +- writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); +- writel_relaxed(0xffffffff, bank->reg_base + GPIO_PORTS_EOI); +- writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); +- gc->mask_cache = 0xffffffff; +- +- irq_set_chained_handler_and_data(bank->irq, +- rockchip_irq_demux, bank); +- } +- +- return 0; +-} +- +-static int rockchip_gpiolib_register(struct platform_device *pdev, +- struct rockchip_pinctrl *info) +-{ +- struct rockchip_pin_ctrl *ctrl = info->ctrl; +- struct rockchip_pin_bank *bank = ctrl->pin_banks; +- struct gpio_chip *gc; +- int ret; +- int i; +- +- for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { +- if (!bank->valid) { +- dev_warn(&pdev->dev, "bank %s is not valid\n", +- bank->name); +- continue; +- } +- +- bank->gpio_chip = rockchip_gpiolib_chip; +- +- gc = &bank->gpio_chip; +- gc->base = bank->pin_base; +- gc->ngpio = bank->nr_pins; +- gc->parent = &pdev->dev; +- gc->of_node = bank->of_node; +- gc->label = bank->name; +- +- ret = gpiochip_add_data(gc, bank); +- if (ret) { +- dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", +- gc->label, ret); +- goto fail; +- } +- } +- +- rockchip_interrupts_register(pdev, info); +- + return 0; +- +-fail: +- for (--i, --bank; i >= 0; --i, --bank) { +- if (!bank->valid) +- continue; +- gpiochip_remove(&bank->gpio_chip); +- } +- return ret; +-} +- +-static int rockchip_gpiolib_unregister(struct platform_device *pdev, +- struct rockchip_pinctrl *info) +-{ +- struct rockchip_pin_ctrl *ctrl = info->ctrl; +- struct rockchip_pin_bank *bank = ctrl->pin_banks; +- int i; +- +- for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { +- if (!bank->valid) +- continue; +- gpiochip_remove(&bank->gpio_chip); +- } +- +- return 0; +-} +- +-static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, +- struct rockchip_pinctrl *info) +-{ +- struct resource res; +- void __iomem *base; +- +- if (of_address_to_resource(bank->of_node, 0, &res)) { +- dev_err(info->dev, "cannot find IO resource for bank\n"); +- return -ENOENT; +- } +- +- bank->reg_base = devm_ioremap_resource(info->dev, &res); +- if (IS_ERR(bank->reg_base)) +- return PTR_ERR(bank->reg_base); +- +- /* +- * special case, where parts of the pull setting-registers are +- * part of the PMU register space +- */ +- if (of_device_is_compatible(bank->of_node, +- "rockchip,rk3188-gpio-bank0")) { +- struct device_node *node; +- +- node = of_parse_phandle(bank->of_node->parent, +- "rockchip,pmu", 0); +- if (!node) { +- if (of_address_to_resource(bank->of_node, 1, &res)) { +- dev_err(info->dev, "cannot find IO resource for bank\n"); +- return -ENOENT; +- } +- +- base = devm_ioremap_resource(info->dev, &res); +- if (IS_ERR(base)) +- return PTR_ERR(base); +- rockchip_regmap_config.max_register = +- resource_size(&res) - 4; +- rockchip_regmap_config.name = +- "rockchip,rk3188-gpio-bank0-pull"; +- bank->regmap_pull = devm_regmap_init_mmio(info->dev, +- base, +- &rockchip_regmap_config); +- } +- of_node_put(node); +- } +- +- bank->irq = irq_of_parse_and_map(bank->of_node, 0); +- +- bank->clk = of_clk_get(bank->of_node, 0); +- if (IS_ERR(bank->clk)) +- return PTR_ERR(bank->clk); +- +- return clk_prepare_enable(bank->clk); + } + + static const struct of_device_id rockchip_pinctrl_dt_match[]; +@@ -3065,7 +2474,6 @@ static struct rockchip_pin_ctrl *rockchi + { + const struct of_device_id *match; + struct device_node *node = pdev->dev.of_node; +- struct device_node *np; + struct rockchip_pin_ctrl *ctrl; + struct rockchip_pin_bank *bank; + int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; +@@ -3073,23 +2481,6 @@ static struct rockchip_pin_ctrl *rockchi + match = of_match_node(rockchip_pinctrl_dt_match, node); + ctrl = (struct rockchip_pin_ctrl *)match->data; + +- for_each_child_of_node(node, np) { +- if (!of_find_property(np, "gpio-controller", NULL)) +- continue; +- +- bank = ctrl->pin_banks; +- for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { +- if (!strcmp(bank->name, np->name)) { +- bank->of_node = np; +- +- if (!rockchip_get_bank_data(bank, d)) +- bank->valid = true; +- +- break; +- } +- } +- } +- + grf_offs = ctrl->grf_mux_offset; + pmu_offs = ctrl->pmu_mux_offset; + drv_pmu_offs = ctrl->pmu_drv_offset; +@@ -3310,18 +2701,18 @@ static int rockchip_pinctrl_probe(struct + return PTR_ERR(info->regmap_pmu); + } + +- ret = rockchip_gpiolib_register(pdev, info); ++ ret = rockchip_pinctrl_register(pdev, info); + if (ret) + return ret; + +- ret = rockchip_pinctrl_register(pdev, info); ++ platform_set_drvdata(pdev, info); ++ ++ ret = of_platform_populate(np, rockchip_bank_match, NULL, NULL); + if (ret) { +- rockchip_gpiolib_unregister(pdev, info); ++ dev_err(&pdev->dev, "failed to register gpio device\n"); + return ret; + } + +- platform_set_drvdata(pdev, info); +- + return 0; + } + diff --git a/patches.suse/pinctrl-rockchip-enable-gpio-pclk-for-rockchip_gpio_.patch b/patches.suse/pinctrl-rockchip-enable-gpio-pclk-for-rockchip_gpio_.patch new file mode 100644 index 0000000..5258497 --- /dev/null +++ b/patches.suse/pinctrl-rockchip-enable-gpio-pclk-for-rockchip_gpio_.patch @@ -0,0 +1,38 @@ +From: Jianqun Xu +Date: Tue, 13 Oct 2020 14:37:30 +0800 +Subject: pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq + +Git-commit: 63fbf8013b2f6430754526ef9594f229c7219b1f +Patch-mainline: v5.10-rc4 +References: bsc#1192217 + +There need to enable pclk_gpio when do irq_create_mapping, since it will +do access to gpio controller. + +Signed-off-by: Jianqun Xu +Reviewed-by: Heiko Stuebner +Reviewed-by: Kever Yang +Link: https://lore.kernel.org/r/20201013063731.3618-3-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index 0401c1da79dd..7b398ed2113e 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -3155,7 +3155,9 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) + if (!bank->domain) + return -ENXIO; + ++ clk_enable(bank->clk); + virq = irq_create_mapping(bank->domain, offset); ++ clk_disable(bank->clk); + + return (virq) ? : -ENXIO; + } +-- +2.31.1 + diff --git a/patches.suse/pinctrl-rockchip-make-driver-be-tristate-module.patch b/patches.suse/pinctrl-rockchip-make-driver-be-tristate-module.patch new file mode 100644 index 0000000..174d306 --- /dev/null +++ b/patches.suse/pinctrl-rockchip-make-driver-be-tristate-module.patch @@ -0,0 +1,62 @@ +From: Jianqun Xu +Date: Fri, 5 Mar 2021 08:39:07 +0800 +Subject: pinctrl: rockchip: make driver be tristate module + +Git-commit: be786ac5a6c4bf4ef3e4c569a045d302c1e60fe6 +Patch-mainline: v5.13-rc1 +References: bsc#1192217 + +Make pinctrl-rockchip driver to be tristate module, support to build as +a module, this is useful for GKI. + +Reviewed-by: Heiko Stuebner +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20210305003907.1692515-3-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/Kconfig | 2 +- + drivers/pinctrl/pinctrl-rockchip.c | 13 +++++++++++++ + 2 files changed, 14 insertions(+), 1 deletion(-) + +--- a/drivers/pinctrl/Kconfig ++++ b/drivers/pinctrl/Kconfig +@@ -187,7 +187,7 @@ config PINCTRL_OXNAS + select MFD_SYSCON + + config PINCTRL_ROCKCHIP +- bool ++ tristate "Rockchip gpio and pinctrl driver" + select PINMUX + select GENERIC_PINCONF + select GENERIC_IRQ_CHIP +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -16,10 +16,12 @@ + */ + + #include ++#include + #include + #include + #include + #include ++#include + #include + #include + #include +@@ -4257,3 +4259,14 @@ static int __init rockchip_pinctrl_drv_r + return platform_driver_register(&rockchip_pinctrl_driver); + } + postcore_initcall(rockchip_pinctrl_drv_register); ++ ++static void __exit rockchip_pinctrl_drv_unregister(void) ++{ ++ platform_driver_unregister(&rockchip_pinctrl_driver); ++} ++module_exit(rockchip_pinctrl_drv_unregister); ++ ++MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:pinctrl-rockchip"); ++MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); diff --git a/patches.suse/pinctrl-rockchip-return-ENOMEM-instead-of-EINVAL-if-.patch b/patches.suse/pinctrl-rockchip-return-ENOMEM-instead-of-EINVAL-if-.patch new file mode 100644 index 0000000..8dab436 --- /dev/null +++ b/patches.suse/pinctrl-rockchip-return-ENOMEM-instead-of-EINVAL-if-.patch @@ -0,0 +1,45 @@ +From: Dafna Hirschfeld +Date: Wed, 6 May 2020 12:14:24 +0200 +Subject: pinctrl: rockchip: return ENOMEM instead of EINVAL if allocation + fails + +Git-commit: c4f333b758ab4d8d4bc643e8bddac96082e0c379 +Patch-mainline: v5.8-rc1 +References: bsc#1192217 + +The function rockchip_pinctrl_parse_dt returns -EINVAL if +allocation fails. Change the return error to -ENOMEM + +Signed-off-by: Dafna Hirschfeld +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20200506101424.15691-1-dafna.hirschfeld@collabora.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index 098951346339..a9299f0bd21e 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -2940,14 +2940,14 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, + sizeof(struct rockchip_pmx_func), + GFP_KERNEL); + if (!info->functions) +- return -EINVAL; ++ return -ENOMEM; + + info->groups = devm_kcalloc(dev, + info->ngroups, + sizeof(struct rockchip_pin_group), + GFP_KERNEL); + if (!info->groups) +- return -EINVAL; ++ return -ENOMEM; + + i = 0; + +-- +2.31.1 + diff --git a/patches.suse/pinctrl-rockchip-separate-struct-rockchip_pin_bank-t.patch b/patches.suse/pinctrl-rockchip-separate-struct-rockchip_pin_bank-t.patch new file mode 100644 index 0000000..b5c5b7f --- /dev/null +++ b/patches.suse/pinctrl-rockchip-separate-struct-rockchip_pin_bank-t.patch @@ -0,0 +1,533 @@ +From: Jianqun Xu +Date: Mon, 16 Aug 2021 09:19:41 +0800 +Subject: pinctrl/rockchip: separate struct rockchip_pin_bank to a head file + +Git-commit: e1450694e94657458395af886d2467d6ac3355af +Patch-mainline: v5.15-rc1 +References: bsc#1192217 + +Separate struct rockchip_pin_bank to pinctrl-rockchip.h file, which will +be used by gpio-rockchip driver in the future. + +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20210816011948.1118959-3-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/pinctrl/pinctrl-rockchip.c | 226 +------------------------- + drivers/pinctrl/pinctrl-rockchip.h | 245 +++++++++++++++++++++++++++++ + 2 files changed, 246 insertions(+), 225 deletions(-) + create mode 100644 drivers/pinctrl/pinctrl-rockchip.h + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index 650c71c740f0..b99813379918 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -37,6 +37,7 @@ + + #include "core.h" + #include "pinconf.h" ++#include "pinctrl-rockchip.h" + + /* GPIO control registers */ + #define GPIO_SWPORT_DR 0x00 +@@ -52,21 +53,6 @@ + #define GPIO_EXT_PORT 0x50 + #define GPIO_LS_SYNC 0x60 + +-enum rockchip_pinctrl_type { +- PX30, +- RV1108, +- RK2928, +- RK3066B, +- RK3128, +- RK3188, +- RK3288, +- RK3308, +- RK3368, +- RK3399, +- RK3568, +-}; +- +- + /** + * Generate a bitmask for setting a value (v) with a write mask bit in hiword + * register 31:16 area. +@@ -84,103 +70,6 @@ enum rockchip_pinctrl_type { + #define IOMUX_WIDTH_3BIT BIT(4) + #define IOMUX_WIDTH_2BIT BIT(5) + +-/** +- * struct rockchip_iomux +- * @type: iomux variant using IOMUX_* constants +- * @offset: if initialized to -1 it will be autocalculated, by specifying +- * an initial offset value the relevant source offset can be reset +- * to a new value for autocalculating the following iomux registers. +- */ +-struct rockchip_iomux { +- int type; +- int offset; +-}; +- +-/* +- * enum type index corresponding to rockchip_perpin_drv_list arrays index. +- */ +-enum rockchip_pin_drv_type { +- DRV_TYPE_IO_DEFAULT = 0, +- DRV_TYPE_IO_1V8_OR_3V0, +- DRV_TYPE_IO_1V8_ONLY, +- DRV_TYPE_IO_1V8_3V0_AUTO, +- DRV_TYPE_IO_3V3_ONLY, +- DRV_TYPE_MAX +-}; +- +-/* +- * enum type index corresponding to rockchip_pull_list arrays index. +- */ +-enum rockchip_pin_pull_type { +- PULL_TYPE_IO_DEFAULT = 0, +- PULL_TYPE_IO_1V8_ONLY, +- PULL_TYPE_MAX +-}; +- +-/** +- * struct rockchip_drv +- * @drv_type: drive strength variant using rockchip_perpin_drv_type +- * @offset: if initialized to -1 it will be autocalculated, by specifying +- * an initial offset value the relevant source offset can be reset +- * to a new value for autocalculating the following drive strength +- * registers. if used chips own cal_drv func instead to calculate +- * registers offset, the variant could be ignored. +- */ +-struct rockchip_drv { +- enum rockchip_pin_drv_type drv_type; +- int offset; +-}; +- +-/** +- * struct rockchip_pin_bank +- * @reg_base: register base of the gpio bank +- * @regmap_pull: optional separate register for additional pull settings +- * @clk: clock of the gpio bank +- * @irq: interrupt of the gpio bank +- * @saved_masks: Saved content of GPIO_INTEN at suspend time. +- * @pin_base: first pin number +- * @nr_pins: number of pins in this bank +- * @name: name of the bank +- * @bank_num: number of the bank, to account for holes +- * @iomux: array describing the 4 iomux sources of the bank +- * @drv: array describing the 4 drive strength sources of the bank +- * @pull_type: array describing the 4 pull type sources of the bank +- * @valid: is all necessary information present +- * @of_node: dt node of this bank +- * @drvdata: common pinctrl basedata +- * @domain: irqdomain of the gpio bank +- * @gpio_chip: gpiolib chip +- * @grange: gpio range +- * @slock: spinlock for the gpio bank +- * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode +- * @recalced_mask: bit mask to indicate a need to recalulate the mask +- * @route_mask: bits describing the routing pins of per bank +- */ +-struct rockchip_pin_bank { +- void __iomem *reg_base; +- struct regmap *regmap_pull; +- struct clk *clk; +- int irq; +- u32 saved_masks; +- u32 pin_base; +- u8 nr_pins; +- char *name; +- u8 bank_num; +- struct rockchip_iomux iomux[4]; +- struct rockchip_drv drv[4]; +- enum rockchip_pin_pull_type pull_type[4]; +- bool valid; +- struct device_node *of_node; +- struct rockchip_pinctrl *drvdata; +- struct irq_domain *domain; +- struct gpio_chip gpio_chip; +- struct pinctrl_gpio_range grange; +- raw_spinlock_t slock; +- u32 toggle_edge_mode; +- u32 recalced_mask; +- u32 route_mask; +-}; +- + #define PIN_BANK(id, pins, label) \ + { \ + .bank_num = id, \ +@@ -320,119 +209,6 @@ struct rockchip_pin_bank { + #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) + +-/** +- * struct rockchip_mux_recalced_data: represent a pin iomux data. +- * @num: bank number. +- * @pin: pin number. +- * @bit: index at register. +- * @reg: register offset. +- * @mask: mask bit +- */ +-struct rockchip_mux_recalced_data { +- u8 num; +- u8 pin; +- u32 reg; +- u8 bit; +- u8 mask; +-}; +- +-enum rockchip_mux_route_location { +- ROCKCHIP_ROUTE_SAME = 0, +- ROCKCHIP_ROUTE_PMU, +- ROCKCHIP_ROUTE_GRF, +-}; +- +-/** +- * struct rockchip_mux_recalced_data: represent a pin iomux data. +- * @bank_num: bank number. +- * @pin: index at register or used to calc index. +- * @func: the min pin. +- * @route_location: the mux route location (same, pmu, grf). +- * @route_offset: the max pin. +- * @route_val: the register offset. +- */ +-struct rockchip_mux_route_data { +- u8 bank_num; +- u8 pin; +- u8 func; +- enum rockchip_mux_route_location route_location; +- u32 route_offset; +- u32 route_val; +-}; +- +-struct rockchip_pin_ctrl { +- struct rockchip_pin_bank *pin_banks; +- u32 nr_banks; +- u32 nr_pins; +- char *label; +- enum rockchip_pinctrl_type type; +- int grf_mux_offset; +- int pmu_mux_offset; +- int grf_drv_offset; +- int pmu_drv_offset; +- struct rockchip_mux_recalced_data *iomux_recalced; +- u32 niomux_recalced; +- struct rockchip_mux_route_data *iomux_routes; +- u32 niomux_routes; +- +- void (*pull_calc_reg)(struct rockchip_pin_bank *bank, +- int pin_num, struct regmap **regmap, +- int *reg, u8 *bit); +- void (*drv_calc_reg)(struct rockchip_pin_bank *bank, +- int pin_num, struct regmap **regmap, +- int *reg, u8 *bit); +- int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, +- int pin_num, struct regmap **regmap, +- int *reg, u8 *bit); +-}; +- +-struct rockchip_pin_config { +- unsigned int func; +- unsigned long *configs; +- unsigned int nconfigs; +-}; +- +-/** +- * struct rockchip_pin_group: represent group of pins of a pinmux function. +- * @name: name of the pin group, used to lookup the group. +- * @pins: the pins included in this group. +- * @npins: number of pins included in this group. +- * @data: local pin configuration +- */ +-struct rockchip_pin_group { +- const char *name; +- unsigned int npins; +- unsigned int *pins; +- struct rockchip_pin_config *data; +-}; +- +-/** +- * struct rockchip_pmx_func: represent a pin function. +- * @name: name of the pin function, used to lookup the function. +- * @groups: one or more names of pin groups that provide this function. +- * @ngroups: number of groups included in @groups. +- */ +-struct rockchip_pmx_func { +- const char *name; +- const char **groups; +- u8 ngroups; +-}; +- +-struct rockchip_pinctrl { +- struct regmap *regmap_base; +- int reg_size; +- struct regmap *regmap_pull; +- struct regmap *regmap_pmu; +- struct device *dev; +- struct rockchip_pin_ctrl *ctrl; +- struct pinctrl_desc pctl; +- struct pinctrl_dev *pctl_dev; +- struct rockchip_pin_group *groups; +- unsigned int ngroups; +- struct rockchip_pmx_func *functions; +- unsigned int nfunctions; +-}; +- + static struct regmap_config rockchip_regmap_config = { + .reg_bits = 32, + .val_bits = 32, +diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h +new file mode 100644 +index 000000000000..dba9e9540633 +--- /dev/null ++++ b/drivers/pinctrl/pinctrl-rockchip.h +@@ -0,0 +1,245 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd. ++ * ++ * Copyright (c) 2013 MundoReader S.L. ++ * Author: Heiko Stuebner ++ * ++ * With some ideas taken from pinctrl-samsung: ++ * Copyright (c) 2012 Samsung Electronics Co., Ltd. ++ * http://www.samsung.com ++ * Copyright (c) 2012 Linaro Ltd ++ * https://www.linaro.org ++ * ++ * and pinctrl-at91: ++ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD ++ */ ++ ++#ifndef _PINCTRL_ROCKCHIP_H ++#define _PINCTRL_ROCKCHIP_H ++ ++enum rockchip_pinctrl_type { ++ PX30, ++ RV1108, ++ RK2928, ++ RK3066B, ++ RK3128, ++ RK3188, ++ RK3288, ++ RK3308, ++ RK3368, ++ RK3399, ++ RK3568, ++}; ++ ++/** ++ * struct rockchip_iomux ++ * @type: iomux variant using IOMUX_* constants ++ * @offset: if initialized to -1 it will be autocalculated, by specifying ++ * an initial offset value the relevant source offset can be reset ++ * to a new value for autocalculating the following iomux registers. ++ */ ++struct rockchip_iomux { ++ int type; ++ int offset; ++}; ++ ++/* ++ * enum type index corresponding to rockchip_perpin_drv_list arrays index. ++ */ ++enum rockchip_pin_drv_type { ++ DRV_TYPE_IO_DEFAULT = 0, ++ DRV_TYPE_IO_1V8_OR_3V0, ++ DRV_TYPE_IO_1V8_ONLY, ++ DRV_TYPE_IO_1V8_3V0_AUTO, ++ DRV_TYPE_IO_3V3_ONLY, ++ DRV_TYPE_MAX ++}; ++ ++/* ++ * enum type index corresponding to rockchip_pull_list arrays index. ++ */ ++enum rockchip_pin_pull_type { ++ PULL_TYPE_IO_DEFAULT = 0, ++ PULL_TYPE_IO_1V8_ONLY, ++ PULL_TYPE_MAX ++}; ++ ++/** ++ * struct rockchip_drv ++ * @drv_type: drive strength variant using rockchip_perpin_drv_type ++ * @offset: if initialized to -1 it will be autocalculated, by specifying ++ * an initial offset value the relevant source offset can be reset ++ * to a new value for autocalculating the following drive strength ++ * registers. if used chips own cal_drv func instead to calculate ++ * registers offset, the variant could be ignored. ++ */ ++struct rockchip_drv { ++ enum rockchip_pin_drv_type drv_type; ++ int offset; ++}; ++ ++/** ++ * struct rockchip_pin_bank ++ * @reg_base: register base of the gpio bank ++ * @regmap_pull: optional separate register for additional pull settings ++ * @clk: clock of the gpio bank ++ * @irq: interrupt of the gpio bank ++ * @saved_masks: Saved content of GPIO_INTEN at suspend time. ++ * @pin_base: first pin number ++ * @nr_pins: number of pins in this bank ++ * @name: name of the bank ++ * @bank_num: number of the bank, to account for holes ++ * @iomux: array describing the 4 iomux sources of the bank ++ * @drv: array describing the 4 drive strength sources of the bank ++ * @pull_type: array describing the 4 pull type sources of the bank ++ * @valid: is all necessary information present ++ * @of_node: dt node of this bank ++ * @drvdata: common pinctrl basedata ++ * @domain: irqdomain of the gpio bank ++ * @gpio_chip: gpiolib chip ++ * @grange: gpio range ++ * @slock: spinlock for the gpio bank ++ * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode ++ * @recalced_mask: bit mask to indicate a need to recalulate the mask ++ * @route_mask: bits describing the routing pins of per bank ++ */ ++struct rockchip_pin_bank { ++ void __iomem *reg_base; ++ struct regmap *regmap_pull; ++ struct clk *clk; ++ int irq; ++ u32 saved_masks; ++ u32 pin_base; ++ u8 nr_pins; ++ char *name; ++ u8 bank_num; ++ struct rockchip_iomux iomux[4]; ++ struct rockchip_drv drv[4]; ++ enum rockchip_pin_pull_type pull_type[4]; ++ bool valid; ++ struct device_node *of_node; ++ struct rockchip_pinctrl *drvdata; ++ struct irq_domain *domain; ++ struct gpio_chip gpio_chip; ++ struct pinctrl_gpio_range grange; ++ raw_spinlock_t slock; ++ u32 toggle_edge_mode; ++ u32 recalced_mask; ++ u32 route_mask; ++}; ++ ++/** ++ * struct rockchip_mux_recalced_data: represent a pin iomux data. ++ * @num: bank number. ++ * @pin: pin number. ++ * @bit: index at register. ++ * @reg: register offset. ++ * @mask: mask bit ++ */ ++struct rockchip_mux_recalced_data { ++ u8 num; ++ u8 pin; ++ u32 reg; ++ u8 bit; ++ u8 mask; ++}; ++ ++enum rockchip_mux_route_location { ++ ROCKCHIP_ROUTE_SAME = 0, ++ ROCKCHIP_ROUTE_PMU, ++ ROCKCHIP_ROUTE_GRF, ++}; ++ ++/** ++ * struct rockchip_mux_recalced_data: represent a pin iomux data. ++ * @bank_num: bank number. ++ * @pin: index at register or used to calc index. ++ * @func: the min pin. ++ * @route_location: the mux route location (same, pmu, grf). ++ * @route_offset: the max pin. ++ * @route_val: the register offset. ++ */ ++struct rockchip_mux_route_data { ++ u8 bank_num; ++ u8 pin; ++ u8 func; ++ enum rockchip_mux_route_location route_location; ++ u32 route_offset; ++ u32 route_val; ++}; ++ ++struct rockchip_pin_ctrl { ++ struct rockchip_pin_bank *pin_banks; ++ u32 nr_banks; ++ u32 nr_pins; ++ char *label; ++ enum rockchip_pinctrl_type type; ++ int grf_mux_offset; ++ int pmu_mux_offset; ++ int grf_drv_offset; ++ int pmu_drv_offset; ++ struct rockchip_mux_recalced_data *iomux_recalced; ++ u32 niomux_recalced; ++ struct rockchip_mux_route_data *iomux_routes; ++ u32 niomux_routes; ++ ++ void (*pull_calc_reg)(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit); ++ void (*drv_calc_reg)(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit); ++ int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit); ++}; ++ ++struct rockchip_pin_config { ++ unsigned int func; ++ unsigned long *configs; ++ unsigned int nconfigs; ++}; ++ ++/** ++ * struct rockchip_pin_group: represent group of pins of a pinmux function. ++ * @name: name of the pin group, used to lookup the group. ++ * @pins: the pins included in this group. ++ * @npins: number of pins included in this group. ++ * @data: local pin configuration ++ */ ++struct rockchip_pin_group { ++ const char *name; ++ unsigned int npins; ++ unsigned int *pins; ++ struct rockchip_pin_config *data; ++}; ++ ++/** ++ * struct rockchip_pmx_func: represent a pin function. ++ * @name: name of the pin function, used to lookup the function. ++ * @groups: one or more names of pin groups that provide this function. ++ * @ngroups: number of groups included in @groups. ++ */ ++struct rockchip_pmx_func { ++ const char *name; ++ const char **groups; ++ u8 ngroups; ++}; ++ ++struct rockchip_pinctrl { ++ struct regmap *regmap_base; ++ int reg_size; ++ struct regmap *regmap_pull; ++ struct regmap *regmap_pmu; ++ struct device *dev; ++ struct rockchip_pin_ctrl *ctrl; ++ struct pinctrl_desc pctl; ++ struct pinctrl_dev *pctl_dev; ++ struct rockchip_pin_group *groups; ++ unsigned int ngroups; ++ struct rockchip_pmx_func *functions; ++ unsigned int nfunctions; ++}; ++ ++#endif +-- +2.31.1 + diff --git a/patches.suse/printk-console-Allow-to-disable-console-output-by-us.patch b/patches.suse/printk-console-Allow-to-disable-console-output-by-us.patch new file mode 100644 index 0000000..5b497e2 --- /dev/null +++ b/patches.suse/printk-console-Allow-to-disable-console-output-by-us.patch @@ -0,0 +1,66 @@ +From 3cffa06aeef7ece30f6b5ac0ea51f264e8fea4d0 Mon Sep 17 00:00:00 2001 +From: Petr Mladek +Date: Wed, 11 Nov 2020 14:54:50 +0100 +Subject: [PATCH] printk/console: Allow to disable console output by using + console="" or console=null +Git-commit: 3cffa06aeef7ece30f6b5ac0ea51f264e8fea4d0 +Patch-mainline: v5.11-rc1 +References: bsc#1192753 + +The commit 48021f98130880dd74 ("printk: handle blank console arguments +passed in.") prevented crash caused by empty console= parameter value. + +Unfortunately, this value is widely used on Chromebooks to disable +the console output. The above commit caused performance regression +because the messages were pushed on slow console even though nobody +was watching it. + +Use ttynull driver explicitly for console="" and console=null +parameters. It has been created for exactly this purpose. + +It causes that preferred_console is set. As a result, ttySX and ttyX +are not used as a fallback. And only ttynull console gets registered by +default. + +It still allows to register other consoles either by additional console= +parameters or SPCR. It prevents regression because it worked this way even +before. Also it is a sane semantic. Preventing output on all consoles +should be done another way, for example, by introducing mute_console +parameter. + +Link: https://lore.kernel.org/r/20201006025935.GA597@jagdpanzerIV.localdomain +Suggested-by: Sergey Senozhatsky +Reviewed-by: Guenter Roeck +Tested-by: Guenter Roeck +Acked-by: Sergey Senozhatsky +Signed-off-by: Petr Mladek +Link: https://lore.kernel.org/r/20201111135450.11214-3-pmladek@suse.com + +--- + kernel/printk/printk.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c +index fe64a49344bf..ac440b879a2c 100644 +--- a/kernel/printk/printk.c ++++ b/kernel/printk/printk.c +@@ -2189,8 +2189,15 @@ static int __init console_setup(char *str) + char *s, *options, *brl_options = NULL; + int idx; + +- if (str[0] == 0) ++ /* ++ * console="" or console=null have been suggested as a way to ++ * disable console output. Use ttynull that has been created ++ * for exacly this purpose. ++ */ ++ if (str[0] == 0 || strcmp(str, "null") == 0) { ++ __add_preferred_console("ttynull", 0, NULL, NULL); + return 1; ++ } + + if (_braille_console_setup(&str, &brl_options)) + return 1; +-- +2.26.2 + diff --git a/patches.suse/printk-handle-blank-console-arguments-passed-in.patch b/patches.suse/printk-handle-blank-console-arguments-passed-in.patch new file mode 100644 index 0000000..34afe8b --- /dev/null +++ b/patches.suse/printk-handle-blank-console-arguments-passed-in.patch @@ -0,0 +1,44 @@ +From 48021f98130880dd74286459a1ef48b5e9bc374f Mon Sep 17 00:00:00 2001 +From: Shreyas Joshi +Date: Fri, 22 May 2020 16:53:06 +1000 +Subject: [PATCH] printk: handle blank console arguments passed in. +Git-commit: 48021f98130880dd74286459a1ef48b5e9bc374f +Patch-mainline: v5.8-rc1 +References: bsc#1192753 + +If uboot passes a blank string to console_setup then it results in +a trashed memory. Ultimately, the kernel crashes during freeing up +the memory. + +This fix checks if there is a blank parameter being +passed to console_setup from uboot. In case it detects that +the console parameter is blank then it doesn't setup the serial +device and it gracefully exits. + +Link: https://lore.kernel.org/r/20200522065306.83-1-shreyas.joshi@biamp.com +Signed-off-by: Shreyas Joshi +Acked-by: Sergey Senozhatsky +[pmladek@suse.com: Better format the commit message and code, remove unnecessary brackets.] +Signed-off-by: Petr Mladek + +--- + kernel/printk/printk.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c +index 35cc5f548860..a3990505abdf 100644 +--- a/kernel/printk/printk.c ++++ b/kernel/printk/printk.c +@@ -2200,6 +2200,9 @@ static int __init console_setup(char *str) + char *s, *options, *brl_options = NULL; + int idx; + ++ if (str[0] == 0) ++ return 1; ++ + if (_braille_console_setup(&str, &brl_options)) + return 1; + +-- +2.26.2 + diff --git a/patches.suse/pstore_disable_efi_backend_by_default.patch b/patches.suse/pstore_disable_efi_backend_by_default.patch index 19bf711..7354b0c 100644 --- a/patches.suse/pstore_disable_efi_backend_by_default.patch +++ b/patches.suse/pstore_disable_efi_backend_by_default.patch @@ -1,7 +1,7 @@ From: Thomas Renninger Subject: Disable efi pstore by default References: bnc#804482 -Patch-Mainline: no, probably never in this form +Patch-Mainline: Never, considered obsolete, dropped in master On broken BIOSes the memory area which pstore (and others) use for storing non volatile data may not be correctly passed to the OS. diff --git a/patches.suse/r8152-Add-macpassthru-support-for-ThinkPad-Thunderbo.patch b/patches.suse/r8152-Add-macpassthru-support-for-ThinkPad-Thunderbo.patch new file mode 100644 index 0000000..986d735 --- /dev/null +++ b/patches.suse/r8152-Add-macpassthru-support-for-ThinkPad-Thunderbo.patch @@ -0,0 +1,146 @@ +From 9647722befbedcd6735e00655ffec392c05f0c56 Mon Sep 17 00:00:00 2001 +From: Kai-Heng Feng +Date: Tue, 5 Nov 2019 19:24:52 +0800 +Subject: [PATCH] r8152: Add macpassthru support for ThinkPad Thunderbolt 3 + Dock Gen 2 +Git-commit: 9647722befbedcd6735e00655ffec392c05f0c56 +References: git-fixes +Patch-mainline: v5.5-rc1 + +ThinkPad Thunderbolt 3 Dock Gen 2 is another docking station that uses +RTL8153 based USB ethernet. + +The device supports macpassthru, but it failed to pass the test of -AD, +-BND and -BD. Simply bypass these tests since the device supports this +feature just fine. + +Also the ACPI objects have some differences between Dell's and Lenovo's, +so make those ACPI infos no longer hardcoded. + +BugLink: https://bugs.launchpad.net/bugs/1827961 +Signed-off-by: Kai-Heng Feng +Acked-by: Hayes Wang +Signed-off-by: David S. Miller +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/cdc_ether.c | 7 +++++ + drivers/net/usb/r8152.c | 58 +++++++++++++++++++++++++++++--------------- + 2 files changed, 46 insertions(+), 19 deletions(-) + +--- a/drivers/net/usb/cdc_ether.c ++++ b/drivers/net/usb/cdc_ether.c +@@ -766,6 +766,13 @@ static const struct usb_device_id produc + .driver_info = 0, + }, + ++/* ThinkPad Thunderbolt 3 Dock Gen 2 (based on Realtek RTL8153) */ ++{ ++ USB_DEVICE_AND_INTERFACE_INFO(LENOVO_VENDOR_ID, 0x3082, USB_CLASS_COMM, ++ USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), ++ .driver_info = 0, ++}, ++ + /* Lenovo Thinkpad USB 3.0 Ethernet Adapters (based on Realtek RTL8153) */ + { + USB_DEVICE_AND_INTERFACE_INFO(LENOVO_VENDOR_ID, 0x7205, USB_CLASS_COMM, +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -619,6 +619,7 @@ enum rtl8152_flags { + SCHEDULE_TASKLET, + GREEN_ETHERNET, + DELL_TB_RX_AGG_BUG, ++ LENOVO_MACPASSTHRU, + }; + + /* Define these values to match your device */ +@@ -1191,38 +1192,52 @@ static int vendor_mac_passthru_addr_read + int ret = -EINVAL; + u32 ocp_data; + unsigned char buf[6]; +- +- /* test for -AD variant of RTL8153 */ +- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); +- if ((ocp_data & AD_MASK) == 0x1000) { +- /* test for MAC address pass-through bit */ +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); +- if ((ocp_data & PASS_THRU_MASK) != 1) { +- netif_dbg(tp, probe, tp->netdev, +- "No efuse for RTL8153-AD MAC pass through\n"); +- return -ENODEV; +- } ++ char *mac_obj_name; ++ acpi_object_type mac_obj_type; ++ int mac_strlen; ++ ++ if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) { ++ mac_obj_name = "\\MACA"; ++ mac_obj_type = ACPI_TYPE_STRING; ++ mac_strlen = 0x16; + } else { +- /* test for RTL8153-BND and RTL8153-BD */ +- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); +- if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { +- netif_dbg(tp, probe, tp->netdev, +- "Invalid variant for MAC pass through\n"); +- return -ENODEV; ++ /* test for -AD variant of RTL8153 */ ++ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); ++ if ((ocp_data & AD_MASK) == 0x1000) { ++ /* test for MAC address pass-through bit */ ++ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); ++ if ((ocp_data & PASS_THRU_MASK) != 1) { ++ netif_dbg(tp, probe, tp->netdev, ++ "No efuse for RTL8153-AD MAC pass through\n"); ++ return -ENODEV; ++ } ++ } else { ++ /* test for RTL8153-BND and RTL8153-BD */ ++ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); ++ if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { ++ netif_dbg(tp, probe, tp->netdev, ++ "Invalid variant for MAC pass through\n"); ++ return -ENODEV; ++ } + } ++ ++ mac_obj_name = "\\_SB.AMAC"; ++ mac_obj_type = ACPI_TYPE_BUFFER; ++ mac_strlen = 0x17; + } + + /* returns _AUXMAC_#AABBCCDDEEFF# */ +- status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); ++ status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer); + obj = (union acpi_object *)buffer.pointer; + if (!ACPI_SUCCESS(status)) + return -ENODEV; +- if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { ++ if (obj->type != mac_obj_type || obj->string.length != mac_strlen) { + netif_warn(tp, probe, tp->netdev, + "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", + obj->type, obj->string.length); + goto amacout; + } ++ + if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || + strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { + netif_warn(tp, probe, tp->netdev, +@@ -5370,6 +5385,10 @@ static int rtl8152_probe(struct usb_inte + netdev->hw_features &= ~NETIF_F_RXCSUM; + } + ++ if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO && ++ le16_to_cpu(udev->descriptor.idProduct) == 0x3082) ++ set_bit(LENOVO_MACPASSTHRU, &tp->flags); ++ + if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && + (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) { + dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); +@@ -5481,6 +5500,7 @@ static const struct usb_device_id rtl815 + {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, + {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, + {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, ++ {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082)}, + {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, + {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, + {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, diff --git a/patches.suse/r8152-Disable-PLA-MCU-clock-speed-down.patch b/patches.suse/r8152-Disable-PLA-MCU-clock-speed-down.patch new file mode 100644 index 0000000..095eeae --- /dev/null +++ b/patches.suse/r8152-Disable-PLA-MCU-clock-speed-down.patch @@ -0,0 +1,76 @@ +From 08997b5eec08a2c29367f19a74abdea54b299406 Mon Sep 17 00:00:00 2001 +From: Hayes Wang +Date: Wed, 22 Jan 2020 16:02:09 +0800 +Subject: [PATCH] r8152: Disable PLA MCU clock speed down +Git-commit: 08997b5eec08a2c29367f19a74abdea54b299406 +References: git-fixes +Patch-mainline: v5.5 + +PLA MCU clock speed down could only be enabled when tx/rx are disabled. +Otherwise, the packet loss may occur. + +Signed-off-by: Hayes Wang +Signed-off-by: David S. Miller +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/r8152.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -310,6 +310,7 @@ + #define MAC_CLK_SPDWN_EN BIT(15) + + /* PLA_MAC_PWR_CTRL3 */ ++#define PLA_MCU_SPDWN_EN BIT(14) + #define PKT_AVAIL_SPDWN_EN 0x0100 + #define SUSPEND_SPDWN_EN 0x0004 + #define U1U2_SPDWN_EN 0x0002 +@@ -3910,6 +3911,8 @@ static void rtl8153_down(struct r8152 *t + + static void rtl8153b_up(struct r8152 *tp) + { ++ u32 ocp_data; ++ + if (test_bit(RTL8152_UNPLUG, &tp->flags)) + return; + +@@ -3920,17 +3923,27 @@ static void rtl8153b_up(struct r8152 *tp + r8153_first_init(tp); + ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); + ++ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); ++ ocp_data &= ~PLA_MCU_SPDWN_EN; ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); ++ + r8153b_aldps_en(tp, true); + r8153b_u1u2en(tp, true); + } + + static void rtl8153b_down(struct r8152 *tp) + { ++ u32 ocp_data; ++ + if (test_bit(RTL8152_UNPLUG, &tp->flags)) { + rtl_drop_queued_tx(tp); + return; + } + ++ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); ++ ocp_data |= PLA_MCU_SPDWN_EN; ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); ++ + r8153b_u1u2en(tp, false); + r8153_u2p3en(tp, false); + r8153b_power_cut_en(tp, false); +@@ -4409,6 +4422,10 @@ static void r8153b_init(struct r8152 *tp + ocp_data |= MAC_CLK_SPDWN_EN; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); + ++ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); ++ ocp_data &= ~PLA_MCU_SPDWN_EN; ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); ++ + set_bit(GREEN_ETHERNET, &tp->flags); + + /* rx aggregation */ diff --git a/patches.suse/r8152-Re-order-napi_disable-in-rtl8152_close.patch b/patches.suse/r8152-Re-order-napi_disable-in-rtl8152_close.patch index 1a7da47..3c94db9 100644 --- a/patches.suse/r8152-Re-order-napi_disable-in-rtl8152_close.patch +++ b/patches.suse/r8152-Re-order-napi_disable-in-rtl8152_close.patch @@ -35,10 +35,10 @@ Acked-by: Thomas Bogendoerfer --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c -@@ -4021,10 +4021,10 @@ static int rtl8152_close(struct net_devi - #ifdef CONFIG_PM_SLEEP +@@ -4097,10 +4097,10 @@ static int rtl8152_close(struct net_devi unregister_pm_notifier(&tp->pm_notifier); #endif + tasklet_disable(&tp->tx_tl); - napi_disable(&tp->napi); clear_bit(WORK_ENABLE, &tp->flags); usb_kill_urb(tp->intr_urb); diff --git a/patches.suse/r8152-add-a-helper-function-about-setting-EEE.patch b/patches.suse/r8152-add-a-helper-function-about-setting-EEE.patch new file mode 100644 index 0000000..577b118 --- /dev/null +++ b/patches.suse/r8152-add-a-helper-function-about-setting-EEE.patch @@ -0,0 +1,273 @@ +From e7bde56b7446ccda351a216ff55af09a96fea940 Mon Sep 17 00:00:00 2001 +From: Hayes Wang +Date: Fri, 23 Aug 2019 15:33:41 +0800 +Subject: [PATCH] r8152: add a helper function about setting EEE +Git-commit: e7bde56b7446ccda351a216ff55af09a96fea940 +References: git-fixes +Patch-mainline: v5.4-rc1 + +Add a helper function "rtl_eee_enable" for setting EEE. Besides, I +move r8153_eee_en() and r8153b_eee_en(). And, I remove r8152b_enable_eee(), +r8153_set_eee(), and r8153b_set_eee(). + +Signed-off-by: Hayes Wang +Signed-off-by: David S. Miller +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/r8152.c | 168 ++++++++++++++++++---------------------- + 1 file changed, 77 insertions(+), 91 deletions(-) + +diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c +index a7aa48bee732..17f0e9e98697 100644 +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -3202,14 +3202,75 @@ static void r8152_eee_en(struct r8152 *tp, bool enable) + ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); + } + +-static void r8152b_enable_eee(struct r8152 *tp) ++static void r8153_eee_en(struct r8152 *tp, bool enable) + { +- if (tp->eee_en) { +- r8152_eee_en(tp, true); +- r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, tp->eee_adv); ++ u32 ocp_data; ++ u16 config; ++ ++ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); ++ config = ocp_reg_read(tp, OCP_EEE_CFG); ++ ++ if (enable) { ++ ocp_data |= EEE_RX_EN | EEE_TX_EN; ++ config |= EEE10_EN; + } else { +- r8152_eee_en(tp, false); +- r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); ++ ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); ++ config &= ~EEE10_EN; ++ } ++ ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); ++ ocp_reg_write(tp, OCP_EEE_CFG, config); ++} ++ ++static void r8153b_eee_en(struct r8152 *tp, bool enable) ++{ ++ r8153_eee_en(tp, enable); ++ ++ if (enable) ++ r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); ++ else ++ r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); ++} ++ ++static void rtl_eee_enable(struct r8152 *tp, bool enable) ++{ ++ switch (tp->version) { ++ case RTL_VER_01: ++ case RTL_VER_02: ++ case RTL_VER_07: ++ if (enable) { ++ r8152_eee_en(tp, true); ++ r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, ++ tp->eee_adv); ++ } else { ++ r8152_eee_en(tp, false); ++ r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); ++ } ++ break; ++ case RTL_VER_03: ++ case RTL_VER_04: ++ case RTL_VER_05: ++ case RTL_VER_06: ++ if (enable) { ++ r8153_eee_en(tp, true); ++ ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); ++ } else { ++ r8153_eee_en(tp, false); ++ ocp_reg_write(tp, OCP_EEE_ADV, 0); ++ } ++ break; ++ case RTL_VER_08: ++ case RTL_VER_09: ++ if (enable) { ++ r8153b_eee_en(tp, true); ++ ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); ++ } else { ++ r8153b_eee_en(tp, false); ++ ocp_reg_write(tp, OCP_EEE_ADV, 0); ++ } ++ break; ++ default: ++ break; + } + } + +@@ -3231,7 +3292,7 @@ static void rtl8152_disable(struct r8152 *tp) + + static void r8152b_hw_phy_cfg(struct r8152 *tp) + { +- r8152b_enable_eee(tp); ++ rtl_eee_enable(tp, tp->eee_en); + r8152_aldps_en(tp, true); + r8152b_enable_fc(tp); + +@@ -3425,36 +3486,6 @@ static void r8153b_aldps_en(struct r8152 *tp, bool enable) + r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS); + } + +-static void r8153_eee_en(struct r8152 *tp, bool enable) +-{ +- u32 ocp_data; +- u16 config; +- +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); +- config = ocp_reg_read(tp, OCP_EEE_CFG); +- +- if (enable) { +- ocp_data |= EEE_RX_EN | EEE_TX_EN; +- config |= EEE10_EN; +- } else { +- ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); +- config &= ~EEE10_EN; +- } +- +- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); +- ocp_reg_write(tp, OCP_EEE_CFG, config); +-} +- +-static void r8153b_eee_en(struct r8152 *tp, bool enable) +-{ +- r8153_eee_en(tp, enable); +- +- if (enable) +- r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); +- else +- r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); +-} +- + static void r8153b_enable_fc(struct r8152 *tp) + { + r8152b_enable_fc(tp); +@@ -3470,8 +3501,7 @@ static void r8153_hw_phy_cfg(struct r8152 *tp) + r8153_aldps_en(tp, false); + + /* disable EEE before updating the PHY parameters */ +- r8153_eee_en(tp, false); +- ocp_reg_write(tp, OCP_EEE_ADV, 0); ++ rtl_eee_enable(tp, false); + + if (tp->version == RTL_VER_03) { + data = ocp_reg_read(tp, OCP_EEE_CFG); +@@ -3502,10 +3532,8 @@ static void r8153_hw_phy_cfg(struct r8152 *tp) + sram_write(tp, SRAM_10M_AMP1, 0x00af); + sram_write(tp, SRAM_10M_AMP2, 0x0208); + +- if (tp->eee_en) { +- r8153_eee_en(tp, true); +- ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); +- } ++ if (tp->eee_en) ++ rtl_eee_enable(tp, true); + + r8153_aldps_en(tp, true); + r8152b_enable_fc(tp); +@@ -3545,8 +3573,7 @@ static void r8153b_hw_phy_cfg(struct r8152 *tp) + r8153b_aldps_en(tp, false); + + /* disable EEE before updating the PHY parameters */ +- r8153b_eee_en(tp, false); +- ocp_reg_write(tp, OCP_EEE_ADV, 0); ++ rtl_eee_enable(tp, false); + + r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); + +@@ -3608,10 +3635,8 @@ static void r8153b_hw_phy_cfg(struct r8152 *tp) + + r8153b_ups_flags_w1w0(tp, ups_flags, 0); + +- if (tp->eee_en) { +- r8153b_eee_en(tp, true); +- ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); +- } ++ if (tp->eee_en) ++ rtl_eee_enable(tp, true); + + r8153b_aldps_en(tp, true); + r8153b_enable_fc(tp); +@@ -4930,12 +4955,7 @@ static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) + tp->eee_en = eee->eee_enabled; + tp->eee_adv = val; + +- r8152_eee_en(tp, eee->eee_enabled); +- +- if (eee->eee_enabled) +- r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); +- else +- r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); ++ rtl_eee_enable(tp, tp->eee_en); + + return 0; + } +@@ -4963,40 +4983,6 @@ static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) + return 0; + } + +-static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) +-{ +- u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); +- +- tp->eee_en = eee->eee_enabled; +- tp->eee_adv = val; +- +- r8153_eee_en(tp, eee->eee_enabled); +- +- if (eee->eee_enabled) +- ocp_reg_write(tp, OCP_EEE_ADV, val); +- else +- ocp_reg_write(tp, OCP_EEE_ADV, 0); +- +- return 0; +-} +- +-static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee) +-{ +- u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); +- +- tp->eee_en = eee->eee_enabled; +- tp->eee_adv = val; +- +- r8153b_eee_en(tp, eee->eee_enabled); +- +- if (eee->eee_enabled) +- ocp_reg_write(tp, OCP_EEE_ADV, val); +- else +- ocp_reg_write(tp, OCP_EEE_ADV, 0); +- +- return 0; +-} +- + static int + rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) + { +@@ -5382,7 +5368,7 @@ static int rtl_ops_init(struct r8152 *tp) + ops->down = rtl8153_down; + ops->unload = rtl8153_unload; + ops->eee_get = r8153_get_eee; +- ops->eee_set = r8153_set_eee; ++ ops->eee_set = r8152_set_eee; + ops->in_nway = rtl8153_in_nway; + ops->hw_phy_cfg = r8153_hw_phy_cfg; + ops->autosuspend_en = rtl8153_runtime_enable; +@@ -5400,7 +5386,7 @@ static int rtl_ops_init(struct r8152 *tp) + ops->down = rtl8153b_down; + ops->unload = rtl8153b_unload; + ops->eee_get = r8153_get_eee; +- ops->eee_set = r8153b_set_eee; ++ ops->eee_set = r8152_set_eee; + ops->in_nway = rtl8153_in_nway; + ops->hw_phy_cfg = r8153b_hw_phy_cfg; + ops->autosuspend_en = rtl8153b_runtime_enable; +-- +2.26.2 + diff --git a/patches.suse/r8152-avoid-to-call-napi_disable-twice.patch b/patches.suse/r8152-avoid-to-call-napi_disable-twice.patch index 21d1bf5..41a591a 100644 --- a/patches.suse/r8152-avoid-to-call-napi_disable-twice.patch +++ b/patches.suse/r8152-avoid-to-call-napi_disable-twice.patch @@ -25,10 +25,10 @@ Acked-by: Thomas Bogendoerfer --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c -@@ -4289,10 +4289,10 @@ static int rtl8152_pre_reset(struct usb_ - return 0; +@@ -4366,10 +4366,10 @@ static int rtl8152_pre_reset(struct usb_ netif_stop_queue(netdev); + tasklet_disable(&tp->tx_tl); - napi_disable(&tp->napi); clear_bit(WORK_ENABLE, &tp->flags); usb_kill_urb(tp->intr_urb); @@ -37,7 +37,7 @@ Acked-by: Thomas Bogendoerfer if (netif_carrier_ok(netdev)) { mutex_lock(&tp->control); tp->rtl_ops.disable(tp); -@@ -4409,7 +4409,7 @@ static int rtl8152_system_resume(struct +@@ -4487,7 +4487,7 @@ static int rtl8152_system_resume(struct netif_device_attach(netdev); diff --git a/patches.suse/r8152-disable-U2P3-for-RTL8153B.patch b/patches.suse/r8152-disable-U2P3-for-RTL8153B.patch new file mode 100644 index 0000000..4c7fe76 --- /dev/null +++ b/patches.suse/r8152-disable-U2P3-for-RTL8153B.patch @@ -0,0 +1,43 @@ +From 809a7fc6593f288d6f820ef6cc57b9d69b5f9474 Mon Sep 17 00:00:00 2001 +From: Hayes Wang +Date: Wed, 22 Jan 2020 16:02:08 +0800 +Subject: [PATCH] r8152: disable U2P3 for RTL8153B +Git-commit: 809a7fc6593f288d6f820ef6cc57b9d69b5f9474 +References: git-fixes +Patch-mainline: v5.5 + +Enable U2P3 may miss zero packet for bulk-in. + +Signed-off-by: Hayes Wang +Signed-off-by: David S. Miller +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/r8152.c | 3 --- + 1 file changed, 3 deletions(-) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -3021,7 +3021,6 @@ static void rtl8153b_runtime_enable(stru + r8153b_ups_en(tp, false); + r8153_queue_wake(tp, false); + rtl_runtime_suspend_enable(tp, false); +- r8153_u2p3en(tp, true); + r8153b_u1u2en(tp, true); + } + } +@@ -3578,7 +3577,6 @@ static void r8153b_hw_phy_cfg(struct r81 + + r8153b_aldps_en(tp, true); + r8153b_enable_fc(tp); +- r8153_u2p3en(tp, true); + + set_bit(PHY_RESET, &tp->flags); + } +@@ -3923,7 +3921,6 @@ static void rtl8153b_up(struct r8152 *tp + ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); + + r8153b_aldps_en(tp, true); +- r8153_u2p3en(tp, true); + r8153b_u1u2en(tp, true); + } + diff --git a/patches.suse/r8152-disable-test-IO-for-RTL8153B.patch b/patches.suse/r8152-disable-test-IO-for-RTL8153B.patch index 9703944..aaf8b08 100644 --- a/patches.suse/r8152-disable-test-IO-for-RTL8153B.patch +++ b/patches.suse/r8152-disable-test-IO-for-RTL8153B.patch @@ -19,7 +19,7 @@ Acked-by: Takashi Iwai --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c -@@ -297,6 +297,7 @@ +@@ -298,6 +298,7 @@ /* PLA_PHY_PWR */ #define TX_10M_IDLE_EN 0x0080 #define PFM_PWM_SWITCH 0x0040 @@ -27,9 +27,9 @@ Acked-by: Takashi Iwai /* PLA_MAC_PWR_CTRL */ #define D3_CLK_GATED_EN 0x00004000 -@@ -4264,6 +4265,15 @@ static void r8153b_init(struct r8152 *tp - ocp_data |= MAC_CLK_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); +@@ -4426,6 +4427,15 @@ static void r8153b_init(struct r8152 *tp + ocp_data &= ~PLA_MCU_SPDWN_EN; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); + if (tp->version == RTL_VER_09) { + /* Disable Test IO for 32QFN */ diff --git a/patches.suse/r8152-divide-the-tx-and-rx-bottom-functions.patch b/patches.suse/r8152-divide-the-tx-and-rx-bottom-functions.patch new file mode 100644 index 0000000..a85d859 --- /dev/null +++ b/patches.suse/r8152-divide-the-tx-and-rx-bottom-functions.patch @@ -0,0 +1,200 @@ +From d2187f8e445403b7aeb08e64c1528761154e9ab3 Mon Sep 17 00:00:00 2001 +From: Hayes Wang +Date: Mon, 19 Aug 2019 14:40:36 +0800 +Subject: [PATCH] r8152: divide the tx and rx bottom functions +Git-commit: d2187f8e445403b7aeb08e64c1528761154e9ab3 +References: git-fixes +Patch-mainline: v5.4-rc1 + +Move the tx bottom function from NAPI to a new tasklet. Then, for +multi-cores, the bottom functions of tx and rx may be run at same +time with different cores. This is used to improve performance. + +On x86, Tx/Rx 943/943 Mbits/sec -> 945/944. +For arm platform, Tx/Rx: 917/917 Mbits/sec -> 933/933. + +Signed-off-by: Hayes Wang +Signed-off-by: David S. Miller +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/r8152.c | 39 ++++++++++++++++++++++++++------------- + 1 file changed, 26 insertions(+), 13 deletions(-) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -616,7 +616,7 @@ enum rtl8152_flags { + RTL8152_LINK_CHG, + SELECTIVE_SUSPEND, + PHY_RESET, +- SCHEDULE_NAPI, ++ SCHEDULE_TASKLET, + GREEN_ETHERNET, + DELL_TB_RX_AGG_BUG, + }; +@@ -730,6 +730,7 @@ struct r8152 { + #ifdef CONFIG_PM_SLEEP + struct notifier_block pm_notifier; + #endif ++ struct tasklet_struct tx_tl; + + struct rtl_ops { + void (*init)(struct r8152 *); +@@ -1398,7 +1399,7 @@ static void write_bulk_callback(struct u + return; + + if (!skb_queue_empty(&tp->tx_queue)) +- napi_schedule(&tp->napi); ++ tasklet_schedule(&tp->tx_tl); + } + + static void intr_callback(struct urb *urb) +@@ -2105,8 +2106,12 @@ static void tx_bottom(struct r8152 *tp) + } while (res == 0); + } + +-static void bottom_half(struct r8152 *tp) ++static void bottom_half(unsigned long data) + { ++ struct r8152 *tp; ++ ++ tp = (struct r8152 *)data; ++ + if (test_bit(RTL8152_UNPLUG, &tp->flags)) + return; + +@@ -2118,7 +2123,7 @@ static void bottom_half(struct r8152 *tp + if (!netif_carrier_ok(tp->netdev)) + return; + +- clear_bit(SCHEDULE_NAPI, &tp->flags); ++ clear_bit(SCHEDULE_TASKLET, &tp->flags); + + tx_bottom(tp); + } +@@ -2129,16 +2134,12 @@ static int r8152_poll(struct napi_struct + int work_done; + + work_done = rx_bottom(tp, budget); +- bottom_half(tp); + + if (work_done < budget) { + if (!napi_complete_done(napi, work_done)) + goto out; + if (!list_empty(&tp->rx_done)) + napi_schedule(napi); +- else if (!skb_queue_empty(&tp->tx_queue) && +- !list_empty(&tp->tx_free)) +- napi_schedule(napi); + } + + out: +@@ -2292,11 +2293,11 @@ static netdev_tx_t rtl8152_start_xmit(st + + if (!list_empty(&tp->tx_free)) { + if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { +- set_bit(SCHEDULE_NAPI, &tp->flags); ++ set_bit(SCHEDULE_TASKLET, &tp->flags); + schedule_delayed_work(&tp->schedule, 0); + } else { + usb_mark_last_busy(tp->udev); +- napi_schedule(&tp->napi); ++ tasklet_schedule(&tp->tx_tl); + } + } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { + netif_stop_queue(netdev); +@@ -3930,9 +3931,11 @@ static void set_carrier(struct r8152 *tp + } else { + if (netif_carrier_ok(netdev)) { + netif_carrier_off(netdev); ++ tasklet_disable(&tp->tx_tl); + napi_disable(napi); + tp->rtl_ops.disable(tp); + napi_enable(napi); ++ tasklet_enable(&tp->tx_tl); + netif_info(tp, link, netdev, "carrier off\n"); + } + } +@@ -3965,10 +3968,10 @@ static void rtl_work_func_t(struct work_ + if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) + _rtl8152_set_rx_mode(tp->netdev); + +- /* don't schedule napi before linking */ +- if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && ++ /* don't schedule tasket before linking */ ++ if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) && + netif_carrier_ok(tp->netdev)) +- napi_schedule(&tp->napi); ++ tasklet_schedule(&tp->tx_tl); + + mutex_unlock(&tp->control); + +@@ -4054,6 +4057,7 @@ static int rtl8152_open(struct net_devic + goto out_unlock; + } + napi_enable(&tp->napi); ++ tasklet_enable(&tp->tx_tl); + + mutex_unlock(&tp->control); + +@@ -4081,6 +4085,7 @@ static int rtl8152_close(struct net_devi + #ifdef CONFIG_PM_SLEEP + unregister_pm_notifier(&tp->pm_notifier); + #endif ++ tasklet_disable(&tp->tx_tl); + napi_disable(&tp->napi); + clear_bit(WORK_ENABLE, &tp->flags); + usb_kill_urb(tp->intr_urb); +@@ -4349,6 +4354,7 @@ static int rtl8152_pre_reset(struct usb_ + return 0; + + netif_stop_queue(netdev); ++ tasklet_disable(&tp->tx_tl); + napi_disable(&tp->napi); + clear_bit(WORK_ENABLE, &tp->flags); + usb_kill_urb(tp->intr_urb); +@@ -4392,6 +4398,7 @@ static int rtl8152_post_reset(struct usb + } + + napi_enable(&tp->napi); ++ tasklet_enable(&tp->tx_tl); + netif_wake_queue(netdev); + usb_submit_urb(tp->intr_urb, GFP_KERNEL); + +@@ -4545,10 +4552,12 @@ static int rtl8152_system_suspend(struct + + clear_bit(WORK_ENABLE, &tp->flags); + usb_kill_urb(tp->intr_urb); ++ tasklet_disable(&tp->tx_tl); + napi_disable(napi); + cancel_delayed_work_sync(&tp->schedule); + tp->rtl_ops.down(tp); + napi_enable(napi); ++ tasklet_enable(&tp->tx_tl); + } + + return 0; +@@ -5333,6 +5342,8 @@ static int rtl8152_probe(struct usb_inte + mutex_init(&tp->control); + INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); + INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); ++ tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp); ++ tasklet_disable(&tp->tx_tl); + + netdev->netdev_ops = &rtl8152_netdev_ops; + netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; +@@ -5415,6 +5426,7 @@ static int rtl8152_probe(struct usb_inte + return 0; + + out1: ++ tasklet_kill(&tp->tx_tl); + usb_set_intfdata(intf, NULL); + out: + free_netdev(netdev); +@@ -5430,6 +5442,7 @@ static void rtl8152_disconnect(struct us + rtl_set_unplug(tp); + + unregister_netdev(tp->netdev); ++ tasklet_kill(&tp->tx_tl); + cancel_delayed_work_sync(&tp->hw_phy_work); + tp->rtl_ops.unload(tp); + free_netdev(tp->netdev); diff --git a/patches.suse/r8152-don-t-enable-U1U2-with-USB_SPEED_HIGH-for-RTL8.patch b/patches.suse/r8152-don-t-enable-U1U2-with-USB_SPEED_HIGH-for-RTL8.patch new file mode 100644 index 0000000..2acf8f2 --- /dev/null +++ b/patches.suse/r8152-don-t-enable-U1U2-with-USB_SPEED_HIGH-for-RTL8.patch @@ -0,0 +1,51 @@ +From a0246dafe684a6d5ad31ccd59af0334ccf0cc7b2 Mon Sep 17 00:00:00 2001 +From: Hayes Wang +Date: Wed, 22 Jan 2020 16:02:11 +0800 +Subject: [PATCH] r8152: don't enable U1U2 with USB_SPEED_HIGH for RTL8153B +Git-commit: a0246dafe684a6d5ad31ccd59af0334ccf0cc7b2 +References: git-fixes +Patch-mainline: v5.5 + +For certain platforms, it causes USB reset periodically. + +Signed-off-by: Hayes Wang +Signed-off-by: David S. Miller +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/r8152.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -3023,7 +3023,8 @@ static void rtl8153b_runtime_enable(stru + r8153b_ups_en(tp, false); + r8153_queue_wake(tp, false); + rtl_runtime_suspend_enable(tp, false); +- r8153b_u1u2en(tp, true); ++ if (tp->udev->speed != USB_SPEED_HIGH) ++ r8153b_u1u2en(tp, true); + } + } + +@@ -3929,7 +3930,9 @@ static void rtl8153b_up(struct r8152 *tp + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); + + r8153b_aldps_en(tp, true); +- r8153b_u1u2en(tp, true); ++ ++ if (tp->udev->speed != USB_SPEED_HIGH) ++ r8153b_u1u2en(tp, true); + } + + static void rtl8153b_down(struct r8152 *tp) +@@ -4415,7 +4418,9 @@ static void r8153b_init(struct r8152 *tp + ocp_data &= ~CUR_LINK_OK; + ocp_data |= POLL_LINK_CHG; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); +- r8153b_u1u2en(tp, true); ++ ++ if (tp->udev->speed != USB_SPEED_HIGH) ++ r8153b_u1u2en(tp, true); + usb_enable_lpm(tp->udev); + + /* MAC clock speed down */ diff --git a/patches.suse/r8152-fix-runtime-resume-for-linking-change.patch b/patches.suse/r8152-fix-runtime-resume-for-linking-change.patch new file mode 100644 index 0000000..d9499a7 --- /dev/null +++ b/patches.suse/r8152-fix-runtime-resume-for-linking-change.patch @@ -0,0 +1,73 @@ +From a39142728d0e60a76b67db3cbc187d61fde7b46d Mon Sep 17 00:00:00 2001 +From: Hayes Wang +Date: Wed, 22 Jan 2020 16:02:05 +0800 +Subject: [PATCH] r8152: fix runtime resume for linking change +Git-commit: a39142728d0e60a76b67db3cbc187d61fde7b46d +References: git-fixes +Patch-mainline: v5.5 + +Fix the runtime resume doesn't work normally for linking change. + +1. Reset the settings and status of runtime suspend. +2. Sync the linking status. +3. Poll the linking change. + +Signed-off-by: Hayes Wang +Signed-off-by: David S. Miller +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/r8152.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -347,7 +347,9 @@ + #define UPCOMING_RUNTIME_D3 BIT(0) + + /* PLA_EXTRA_STATUS */ ++#define CUR_LINK_OK BIT(15) + #define LINK_CHANGE_FLAG BIT(8) ++#define POLL_LINK_CHG BIT(0) + + /* USB_USB2PHY */ + #define USB2PHY_SUSPEND 0x0001 +@@ -4275,6 +4277,16 @@ static void r8153_init(struct r8152 *tp) + else + ocp_data |= DYNAMIC_BURST; + ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); ++ ++ r8153_queue_wake(tp, false); ++ ++ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); ++ if (rtl8152_get_speed(tp) & LINK_STATUS) ++ ocp_data |= CUR_LINK_OK; ++ else ++ ocp_data &= ~CUR_LINK_OK; ++ ocp_data |= POLL_LINK_CHG; ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); + } + + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); +@@ -4304,6 +4316,7 @@ static void r8153_init(struct r8152 *tp) + ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); + + r8153_power_cut_en(tp, false); ++ rtl_runtime_suspend_enable(tp, false); + r8153_u1u2en(tp, true); + r8153_mac_clk_spd(tp, false); + usb_enable_lpm(tp->udev); +@@ -4372,6 +4385,14 @@ static void r8153b_init(struct r8152 *tp + r8153b_ups_en(tp, false); + r8153_queue_wake(tp, false); + rtl_runtime_suspend_enable(tp, false); ++ ++ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); ++ if (rtl8152_get_speed(tp) & LINK_STATUS) ++ ocp_data |= CUR_LINK_OK; ++ else ++ ocp_data &= ~CUR_LINK_OK; ++ ocp_data |= POLL_LINK_CHG; ++ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); + r8153b_u1u2en(tp, true); + usb_enable_lpm(tp->udev); + diff --git a/patches.suse/r8152-limit-the-RX-buffer-size-of-RTL8153A-for-USB-2.patch b/patches.suse/r8152-limit-the-RX-buffer-size-of-RTL8153A-for-USB-2.patch new file mode 100644 index 0000000..6ab845f --- /dev/null +++ b/patches.suse/r8152-limit-the-RX-buffer-size-of-RTL8153A-for-USB-2.patch @@ -0,0 +1,49 @@ +From f91a50d8b51b5c8ef1cfb08115a005bba4250507 Mon Sep 17 00:00:00 2001 +From: Hayes Wang +Date: Fri, 19 Mar 2021 15:37:21 +0800 +Subject: [PATCH] r8152: limit the RX buffer size of RTL8153A for USB 2.0 +Git-commit: f91a50d8b51b5c8ef1cfb08115a005bba4250507 +References: git-fixes +Patch-mainline: v5.12-rc5 + +If the USB host controller is EHCI, the throughput is reduced from +300Mb/s to 60Mb/s, when the rx buffer size is modified from 16K to +32K. + +According to the EHCI spec, the maximum size of the qTD is 20K. +Therefore, when the driver uses more than 20K buffer, the latency +time of EHCI would be increased. And, it let the RTL8153A get worse +throughput. + +However, the driver uses alloc_pages() for rx buffer, so I limit +the rx buffer to 16K rather than 20K. + +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=205923 +Fixes: ec5791c202ac ("r8152: separate the rx buffer size") +Reported-by: Robert Davies +Signed-off-by: Hayes Wang +Signed-off-by: David S. Miller +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/r8152.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c +index 90f1c0200042..20fb5638ac65 100644 +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -6553,7 +6553,10 @@ static int rtl_ops_init(struct r8152 *tp) + ops->in_nway = rtl8153_in_nway; + ops->hw_phy_cfg = r8153_hw_phy_cfg; + ops->autosuspend_en = rtl8153_runtime_enable; +- tp->rx_buf_sz = 32 * 1024; ++ if (tp->udev->speed < USB_SPEED_SUPER) ++ tp->rx_buf_sz = 16 * 1024; ++ else ++ tp->rx_buf_sz = 32 * 1024; + tp->eee_en = true; + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; + break; +-- +2.26.2 + diff --git a/patches.suse/r8152-replace-array-with-linking-list-for-rx-informa.patch b/patches.suse/r8152-replace-array-with-linking-list-for-rx-informa.patch new file mode 100644 index 0000000..ac41c6c --- /dev/null +++ b/patches.suse/r8152-replace-array-with-linking-list-for-rx-informa.patch @@ -0,0 +1,292 @@ +From 252df8b86667fe4640a2d9fb5cfc705ad285d578 Mon Sep 17 00:00:00 2001 +From: Hayes Wang +Date: Tue, 13 Aug 2019 11:42:06 +0800 +Subject: [PATCH] r8152: replace array with linking list for rx information +Git-commit: 252df8b86667fe4640a2d9fb5cfc705ad285d578 +References: git-fixes +Patch-mainline: v5.4-rc1 + +The original method uses an array to store the rx information. The +new one uses a list to link each rx structure. Then, it is possible +to increase/decrease the number of rx structure dynamically. + +Signed-off-by: Hayes Wang +Signed-off-by: Jakub Kicinski +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/r8152.c | 182 +++++++++++++++++++++++++++------------- + 1 file changed, 125 insertions(+), 57 deletions(-) + +diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c +index 94da79028a65..d063c9b358e5 100644 +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -22,6 +22,7 @@ + #include + #include + #include ++#include + #include + + /* Information for net-next */ +@@ -694,7 +695,7 @@ struct tx_desc { + struct r8152; + + struct rx_agg { +- struct list_head list; ++ struct list_head list, info_list; + struct urb *urb; + struct r8152 *context; + void *buffer; +@@ -719,7 +720,7 @@ struct r8152 { + struct net_device *netdev; + struct urb *intr_urb; + struct tx_agg tx_info[RTL8152_MAX_TX]; +- struct rx_agg rx_info[RTL8152_MAX_RX]; ++ struct list_head rx_info; + struct list_head rx_done, tx_free; + struct sk_buff_head tx_queue, rx_queue; + spinlock_t rx_lock, tx_lock; +@@ -744,6 +745,8 @@ struct r8152 { + void (*autosuspend_en)(struct r8152 *tp, bool enable); + } rtl_ops; + ++ atomic_t rx_count; ++ + int intr_interval; + u32 saved_wolopts; + u32 msg_enable; +@@ -1468,18 +1471,81 @@ static inline void *tx_agg_align(void *data) + return (void *)ALIGN((uintptr_t)data, TX_ALIGN); + } + ++static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg) ++{ ++ list_del(&agg->info_list); ++ ++ usb_free_urb(agg->urb); ++ kfree(agg->buffer); ++ kfree(agg); ++ ++ atomic_dec(&tp->rx_count); ++} ++ ++static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags) ++{ ++ struct net_device *netdev = tp->netdev; ++ int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; ++ struct rx_agg *rx_agg; ++ unsigned long flags; ++ u8 *buf; ++ ++ rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node); ++ if (!rx_agg) ++ return NULL; ++ ++ buf = kmalloc_node(tp->rx_buf_sz, mflags, node); ++ if (!buf) ++ goto free_rx; ++ ++ if (buf != rx_agg_align(buf)) { ++ kfree(buf); ++ buf = kmalloc_node(tp->rx_buf_sz + RX_ALIGN, mflags, ++ node); ++ if (!buf) ++ goto free_rx; ++ } ++ ++ rx_agg->buffer = buf; ++ rx_agg->head = rx_agg_align(buf); ++ ++ rx_agg->urb = usb_alloc_urb(0, mflags); ++ if (!rx_agg->urb) ++ goto free_buf; ++ ++ rx_agg->context = tp; ++ ++ INIT_LIST_HEAD(&rx_agg->list); ++ INIT_LIST_HEAD(&rx_agg->info_list); ++ spin_lock_irqsave(&tp->rx_lock, flags); ++ list_add_tail(&rx_agg->info_list, &tp->rx_info); ++ spin_unlock_irqrestore(&tp->rx_lock, flags); ++ ++ atomic_inc(&tp->rx_count); ++ ++ return rx_agg; ++ ++free_buf: ++ kfree(rx_agg->buffer); ++free_rx: ++ kfree(rx_agg); ++ return NULL; ++} ++ + static void free_all_mem(struct r8152 *tp) + { ++ struct rx_agg *agg, *agg_next; ++ unsigned long flags; + int i; + +- for (i = 0; i < RTL8152_MAX_RX; i++) { +- usb_free_urb(tp->rx_info[i].urb); +- tp->rx_info[i].urb = NULL; ++ spin_lock_irqsave(&tp->rx_lock, flags); + +- kfree(tp->rx_info[i].buffer); +- tp->rx_info[i].buffer = NULL; +- tp->rx_info[i].head = NULL; +- } ++ list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list) ++ free_rx_agg(tp, agg); ++ ++ spin_unlock_irqrestore(&tp->rx_lock, flags); ++ ++ WARN_ON(atomic_read(&tp->rx_count)); + + for (i = 0; i < RTL8152_MAX_TX; i++) { + usb_free_urb(tp->tx_info[i].urb); +@@ -1503,46 +1569,28 @@ static int alloc_all_mem(struct r8152 *tp) + struct usb_interface *intf = tp->intf; + struct usb_host_interface *alt = intf->cur_altsetting; + struct usb_host_endpoint *ep_intr = alt->endpoint + 2; +- struct urb *urb; + int node, i; +- u8 *buf; + + node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; + + spin_lock_init(&tp->rx_lock); + spin_lock_init(&tp->tx_lock); ++ INIT_LIST_HEAD(&tp->rx_info); + INIT_LIST_HEAD(&tp->tx_free); + INIT_LIST_HEAD(&tp->rx_done); + skb_queue_head_init(&tp->tx_queue); + skb_queue_head_init(&tp->rx_queue); ++ atomic_set(&tp->rx_count, 0); + + for (i = 0; i < RTL8152_MAX_RX; i++) { +- buf = kmalloc_node(tp->rx_buf_sz, GFP_KERNEL, node); +- if (!buf) ++ if (!alloc_rx_agg(tp, GFP_KERNEL)) + goto err1; +- +- if (buf != rx_agg_align(buf)) { +- kfree(buf); +- buf = kmalloc_node(tp->rx_buf_sz + RX_ALIGN, GFP_KERNEL, +- node); +- if (!buf) +- goto err1; +- } +- +- urb = usb_alloc_urb(0, GFP_KERNEL); +- if (!urb) { +- kfree(buf); +- goto err1; +- } +- +- INIT_LIST_HEAD(&tp->rx_info[i].list); +- tp->rx_info[i].context = tp; +- tp->rx_info[i].urb = urb; +- tp->rx_info[i].buffer = buf; +- tp->rx_info[i].head = rx_agg_align(buf); + } + + for (i = 0; i < RTL8152_MAX_TX; i++) { ++ struct urb *urb; ++ u8 *buf; ++ + buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); + if (!buf) + goto err1; +@@ -2331,44 +2379,64 @@ static void rxdy_gated_en(struct r8152 *tp, bool enable) + + static int rtl_start_rx(struct r8152 *tp) + { +- int i, ret = 0; ++ struct rx_agg *agg, *agg_next; ++ struct list_head tmp_list; ++ unsigned long flags; ++ int ret = 0; + +- INIT_LIST_HEAD(&tp->rx_done); +- for (i = 0; i < RTL8152_MAX_RX; i++) { +- INIT_LIST_HEAD(&tp->rx_info[i].list); +- ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); +- if (ret) +- break; +- } ++ INIT_LIST_HEAD(&tmp_list); + +- if (ret && ++i < RTL8152_MAX_RX) { +- struct list_head rx_queue; +- unsigned long flags; ++ spin_lock_irqsave(&tp->rx_lock, flags); + +- INIT_LIST_HEAD(&rx_queue); ++ INIT_LIST_HEAD(&tp->rx_done); + +- do { +- struct rx_agg *agg = &tp->rx_info[i++]; +- struct urb *urb = agg->urb; ++ list_splice_init(&tp->rx_info, &tmp_list); + +- urb->actual_length = 0; +- list_add_tail(&agg->list, &rx_queue); +- } while (i < RTL8152_MAX_RX); ++ spin_unlock_irqrestore(&tp->rx_lock, flags); + +- spin_lock_irqsave(&tp->rx_lock, flags); +- list_splice_tail(&rx_queue, &tp->rx_done); +- spin_unlock_irqrestore(&tp->rx_lock, flags); ++ list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { ++ INIT_LIST_HEAD(&agg->list); ++ ++ if (ret < 0) ++ list_add_tail(&agg->list, &tp->rx_done); ++ else ++ ret = r8152_submit_rx(tp, agg, GFP_KERNEL); + } + ++ spin_lock_irqsave(&tp->rx_lock, flags); ++ WARN_ON(!list_empty(&tp->rx_info)); ++ list_splice(&tmp_list, &tp->rx_info); ++ spin_unlock_irqrestore(&tp->rx_lock, flags); ++ + return ret; + } + + static int rtl_stop_rx(struct r8152 *tp) + { +- int i; ++ struct rx_agg *agg, *agg_next; ++ struct list_head tmp_list; ++ unsigned long flags; ++ ++ INIT_LIST_HEAD(&tmp_list); ++ ++ /* The usb_kill_urb() couldn't be used in atomic. ++ * Therefore, move the list of rx_info to a tmp one. ++ * Then, list_for_each_entry_safe could be used without ++ * spin lock. ++ */ ++ ++ spin_lock_irqsave(&tp->rx_lock, flags); ++ list_splice_init(&tp->rx_info, &tmp_list); ++ spin_unlock_irqrestore(&tp->rx_lock, flags); ++ ++ list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) ++ usb_kill_urb(agg->urb); + +- for (i = 0; i < RTL8152_MAX_RX; i++) +- usb_kill_urb(tp->rx_info[i].urb); ++ /* Move back the list of temp to the rx_info */ ++ spin_lock_irqsave(&tp->rx_lock, flags); ++ WARN_ON(!list_empty(&tp->rx_info)); ++ list_splice(&tmp_list, &tp->rx_info); ++ spin_unlock_irqrestore(&tp->rx_lock, flags); + + while (!skb_queue_empty(&tp->rx_queue)) + dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); +-- +2.26.2 + diff --git a/patches.suse/r8152-reset-flow-control-patch-when-linking-on-for-R.patch b/patches.suse/r8152-reset-flow-control-patch-when-linking-on-for-R.patch new file mode 100644 index 0000000..35c862d --- /dev/null +++ b/patches.suse/r8152-reset-flow-control-patch-when-linking-on-for-R.patch @@ -0,0 +1,56 @@ +From f99cd20eda12b1920ffc284a736437c016b3a5a2 Mon Sep 17 00:00:00 2001 +From: Hayes Wang +Date: Wed, 22 Jan 2020 16:02:06 +0800 +Subject: [PATCH] r8152: reset flow control patch when linking on for RTL8153B +Git-commit: f99cd20eda12b1920ffc284a736437c016b3a5a2 +References: git-fixes +Patch-mainline: v5.5 + +When linking ON, the patch of flow control has to be reset. This +makes sure the patch works normally. + +Signed-off-by: Hayes Wang +Signed-off-by: David S. Miller +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/r8152.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -126,6 +126,7 @@ + #define USB_LPM_CTRL 0xd41a + #define USB_BMU_RESET 0xd4b0 + #define USB_U1U2_TIMER 0xd4da ++#define USB_FW_TASK 0xd4e8 /* RTL8153B */ + #define USB_UPS_CTRL 0xd800 + #define USB_POWER_CUT 0xd80a + #define USB_MISC_0 0xd81a +@@ -394,6 +395,9 @@ + #define OWN_UPDATE BIT(0) + #define OWN_CLEAR BIT(1) + ++/* USB_FW_TASK */ ++#define FC_PATCH_TASK BIT(1) ++ + /* USB_UPS_CTRL */ + #define POWER_CUT 0x0100 + +@@ -2561,6 +2565,17 @@ static int rtl8153_enable(struct r8152 * + r8153_set_rx_early_timeout(tp); + r8153_set_rx_early_size(tp); + ++ if (tp->version == RTL_VER_09) { ++ u32 ocp_data; ++ ++ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); ++ ocp_data &= ~FC_PATCH_TASK; ++ ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); ++ usleep_range(1000, 2000); ++ ocp_data |= FC_PATCH_TASK; ++ ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); ++ } ++ + return rtl_enable(tp); + } + diff --git a/patches.suse/r8152-saving-the-settings-of-EEE.patch b/patches.suse/r8152-saving-the-settings-of-EEE.patch new file mode 100644 index 0000000..33ed62a --- /dev/null +++ b/patches.suse/r8152-saving-the-settings-of-EEE.patch @@ -0,0 +1,214 @@ +From f4a93be689dfc887d73cdaf4245a8a7d031aa912 Mon Sep 17 00:00:00 2001 +From: Hayes Wang +Date: Fri, 23 Aug 2019 15:33:40 +0800 +Subject: [PATCH] r8152: saving the settings of EEE +Git-commit: f4a93be689dfc887d73cdaf4245a8a7d031aa912 +References: git-fixes +Patch-mainline: v5.4-rc1 + +Saving the settings of EEE to avoid they become the default settings +after reset_resume(). + +Signed-off-by: Hayes Wang +Signed-off-by: David S. Miller +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/r8152.c | 80 ++++++++++++++++++++++++++++++------------------ + 1 file changed, 50 insertions(+), 30 deletions(-) + +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -747,6 +747,7 @@ struct r8152 { + + atomic_t rx_count; + ++ bool eee_en; + int intr_interval; + u32 saved_wolopts; + u32 msg_enable; +@@ -755,6 +756,7 @@ struct r8152 { + u32 rx_buf_sz; + u16 ocp_base; + u16 speed; ++ u16 eee_adv; + u8 *intr_buff; + u8 version; + u8 duplex; +@@ -3111,8 +3113,13 @@ static void r8152_eee_en(struct r8152 *t + + static void r8152b_enable_eee(struct r8152 *tp) + { +- r8152_eee_en(tp, true); +- r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); ++ if (tp->eee_en) { ++ r8152_eee_en(tp, true); ++ r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, tp->eee_adv); ++ } else { ++ r8152_eee_en(tp, false); ++ r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); ++ } + } + + static void r8152b_enable_fc(struct r8152 *tp) +@@ -3404,8 +3411,10 @@ static void r8153_hw_phy_cfg(struct r815 + sram_write(tp, SRAM_10M_AMP1, 0x00af); + sram_write(tp, SRAM_10M_AMP2, 0x0208); + +- r8153_eee_en(tp, true); +- ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); ++ if (tp->eee_en) { ++ r8153_eee_en(tp, true); ++ ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); ++ } + + r8153_aldps_en(tp, true); + r8152b_enable_fc(tp); +@@ -3508,8 +3517,10 @@ static void r8153b_hw_phy_cfg(struct r81 + + r8153b_ups_flags_w1w0(tp, ups_flags, 0); + +- r8153b_eee_en(tp, true); +- ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); ++ if (tp->eee_en) { ++ r8153b_eee_en(tp, true); ++ ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); ++ } + + r8153b_aldps_en(tp, true); + r8153b_enable_fc(tp); +@@ -4791,7 +4802,7 @@ static void rtl8152_get_strings(struct n + + static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) + { +- u32 ocp_data, lp, adv, supported = 0; ++ u32 lp, adv, supported = 0; + u16 val; + + val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); +@@ -4803,13 +4814,10 @@ static int r8152_get_eee(struct r8152 *t + val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); + lp = mmd_eee_adv_to_ethtool_adv_t(val); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); +- ocp_data &= EEE_RX_EN | EEE_TX_EN; +- +- eee->eee_enabled = !!ocp_data; ++ eee->eee_enabled = tp->eee_en; + eee->eee_active = !!(supported & adv & lp); + eee->supported = supported; +- eee->advertised = adv; ++ eee->advertised = tp->eee_adv; + eee->lp_advertised = lp; + + return 0; +@@ -4819,19 +4827,22 @@ static int r8152_set_eee(struct r8152 *t + { + u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); + +- r8152_eee_en(tp, eee->eee_enabled); ++ tp->eee_en = eee->eee_enabled; ++ tp->eee_adv = val; + +- if (!eee->eee_enabled) +- val = 0; ++ r8152_eee_en(tp, eee->eee_enabled); + +- r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); ++ if (eee->eee_enabled) ++ r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); ++ else ++ r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); + + return 0; + } + + static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) + { +- u32 ocp_data, lp, adv, supported = 0; ++ u32 lp, adv, supported = 0; + u16 val; + + val = ocp_reg_read(tp, OCP_EEE_ABLE); +@@ -4843,13 +4854,10 @@ static int r8153_get_eee(struct r8152 *t + val = ocp_reg_read(tp, OCP_EEE_LPABLE); + lp = mmd_eee_adv_to_ethtool_adv_t(val); + +- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); +- ocp_data &= EEE_RX_EN | EEE_TX_EN; +- +- eee->eee_enabled = !!ocp_data; ++ eee->eee_enabled = tp->eee_en; + eee->eee_active = !!(supported & adv & lp); + eee->supported = supported; +- eee->advertised = adv; ++ eee->advertised = tp->eee_adv; + eee->lp_advertised = lp; + + return 0; +@@ -4859,12 +4867,15 @@ static int r8153_set_eee(struct r8152 *t + { + u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); + +- r8153_eee_en(tp, eee->eee_enabled); ++ tp->eee_en = eee->eee_enabled; ++ tp->eee_adv = val; + +- if (!eee->eee_enabled) +- val = 0; ++ r8153_eee_en(tp, eee->eee_enabled); + +- ocp_reg_write(tp, OCP_EEE_ADV, val); ++ if (eee->eee_enabled) ++ ocp_reg_write(tp, OCP_EEE_ADV, val); ++ else ++ ocp_reg_write(tp, OCP_EEE_ADV, 0); + + return 0; + } +@@ -4873,12 +4884,15 @@ static int r8153b_set_eee(struct r8152 * + { + u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); + +- r8153b_eee_en(tp, eee->eee_enabled); ++ tp->eee_en = eee->eee_enabled; ++ tp->eee_adv = val; + +- if (!eee->eee_enabled) +- val = 0; ++ r8153b_eee_en(tp, eee->eee_enabled); + +- ocp_reg_write(tp, OCP_EEE_ADV, val); ++ if (eee->eee_enabled) ++ ocp_reg_write(tp, OCP_EEE_ADV, val); ++ else ++ ocp_reg_write(tp, OCP_EEE_ADV, 0); + + return 0; + } +@@ -5178,6 +5192,8 @@ static int rtl_ops_init(struct r8152 *tp + ops->hw_phy_cfg = r8152b_hw_phy_cfg; + ops->autosuspend_en = rtl_runtime_suspend_enable; + tp->rx_buf_sz = 16 * 1024; ++ tp->eee_en = true; ++ tp->eee_adv = MDIO_EEE_100TX; + break; + + case RTL_VER_03: +@@ -5196,6 +5212,8 @@ static int rtl_ops_init(struct r8152 *tp + ops->hw_phy_cfg = r8153_hw_phy_cfg; + ops->autosuspend_en = rtl8153_runtime_enable; + tp->rx_buf_sz = 32 * 1024; ++ tp->eee_en = true; ++ tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; + break; + + case RTL_VER_08: +@@ -5212,6 +5230,8 @@ static int rtl_ops_init(struct r8152 *tp + ops->hw_phy_cfg = r8153b_hw_phy_cfg; + ops->autosuspend_en = rtl8153b_runtime_enable; + tp->rx_buf_sz = 32 * 1024; ++ tp->eee_en = true; ++ tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; + break; + + default: diff --git a/patches.suse/r8152-separate-the-rx-buffer-size.patch b/patches.suse/r8152-separate-the-rx-buffer-size.patch new file mode 100644 index 0000000..54a0b9e --- /dev/null +++ b/patches.suse/r8152-separate-the-rx-buffer-size.patch @@ -0,0 +1,91 @@ +From ec5791c202aca90c1b3b99dff268a995cf2d6aa1 Mon Sep 17 00:00:00 2001 +From: Hayes Wang +Date: Tue, 13 Aug 2019 11:42:05 +0800 +Subject: [PATCH] r8152: separate the rx buffer size +Git-commit: ec5791c202aca90c1b3b99dff268a995cf2d6aa1 +References: git-fixes +Patch-mainline: v5.4-rc1 + +The different chips may accept different rx buffer sizes. The RTL8152 +supports 16K bytes, and RTL8153 support 32K bytes. + +Signed-off-by: Hayes Wang +Signed-off-by: Jakub Kicinski +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/r8152.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c +index 0cc03a9ff545..94da79028a65 100644 +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -749,6 +749,7 @@ struct r8152 { + u32 msg_enable; + u32 tx_qlen; + u32 coalesce; ++ u32 rx_buf_sz; + u16 ocp_base; + u16 speed; + u8 *intr_buff; +@@ -1516,13 +1517,13 @@ static int alloc_all_mem(struct r8152 *tp) + skb_queue_head_init(&tp->rx_queue); + + for (i = 0; i < RTL8152_MAX_RX; i++) { +- buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); ++ buf = kmalloc_node(tp->rx_buf_sz, GFP_KERNEL, node); + if (!buf) + goto err1; + + if (buf != rx_agg_align(buf)) { + kfree(buf); +- buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, ++ buf = kmalloc_node(tp->rx_buf_sz + RX_ALIGN, GFP_KERNEL, + node); + if (!buf) + goto err1; +@@ -2113,7 +2114,7 @@ int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) + return 0; + + usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), +- agg->head, agg_buf_sz, ++ agg->head, tp->rx_buf_sz, + (usb_complete_t)read_bulk_callback, agg); + + ret = usb_submit_urb(agg->urb, mem_flags); +@@ -2447,7 +2448,7 @@ static void r8153_set_rx_early_timeout(struct r8152 *tp) + + static void r8153_set_rx_early_size(struct r8152 *tp) + { +- u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu); ++ u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu); + + switch (tp->version) { + case RTL_VER_03: +@@ -5115,6 +5116,7 @@ static int rtl_ops_init(struct r8152 *tp) + ops->in_nway = rtl8152_in_nway; + ops->hw_phy_cfg = r8152b_hw_phy_cfg; + ops->autosuspend_en = rtl_runtime_suspend_enable; ++ tp->rx_buf_sz = 16 * 1024; + break; + + case RTL_VER_03: +@@ -5132,6 +5134,7 @@ static int rtl_ops_init(struct r8152 *tp) + ops->in_nway = rtl8153_in_nway; + ops->hw_phy_cfg = r8153_hw_phy_cfg; + ops->autosuspend_en = rtl8153_runtime_enable; ++ tp->rx_buf_sz = 32 * 1024; + break; + + case RTL_VER_08: +@@ -5147,6 +5150,7 @@ static int rtl_ops_init(struct r8152 *tp) + ops->in_nway = rtl8153_in_nway; + ops->hw_phy_cfg = r8153b_hw_phy_cfg; + ops->autosuspend_en = rtl8153b_runtime_enable; ++ tp->rx_buf_sz = 32 * 1024; + break; + + default: +-- +2.26.2 + diff --git a/patches.suse/r8152-use-alloc_pages-for-rx-buffer.patch b/patches.suse/r8152-use-alloc_pages-for-rx-buffer.patch new file mode 100644 index 0000000..959c4e1 --- /dev/null +++ b/patches.suse/r8152-use-alloc_pages-for-rx-buffer.patch @@ -0,0 +1,114 @@ +From d55d70894c6d4709b9ae61109a9fa7c319586b53 Mon Sep 17 00:00:00 2001 +From: Hayes Wang +Date: Tue, 13 Aug 2019 11:42:07 +0800 +Subject: [PATCH] r8152: use alloc_pages for rx buffer +Git-commit: d55d70894c6d4709b9ae61109a9fa7c319586b53 +References: git-fixes +Patch-mainline: v5.4-rc1 + +Replace kmalloc_node() with alloc_pages() for rx buffer. + +Signed-off-by: Hayes Wang +Signed-off-by: Jakub Kicinski +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/r8152.c | 31 +++++++++++-------------------- + 1 file changed, 11 insertions(+), 20 deletions(-) + +diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c +index d063c9b358e5..f41cb728e999 100644 +--- a/drivers/net/usb/r8152.c ++++ b/drivers/net/usb/r8152.c +@@ -698,8 +698,8 @@ struct rx_agg { + struct list_head list, info_list; + struct urb *urb; + struct r8152 *context; ++ struct page *page; + void *buffer; +- void *head; + }; + + struct tx_agg { +@@ -1476,7 +1476,7 @@ static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg) + list_del(&agg->info_list); + + usb_free_urb(agg->urb); +- kfree(agg->buffer); ++ __free_pages(agg->page, get_order(tp->rx_buf_sz)); + kfree(agg); + + atomic_dec(&tp->rx_count); +@@ -1486,28 +1486,19 @@ static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags) + { + struct net_device *netdev = tp->netdev; + int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; ++ unsigned int order = get_order(tp->rx_buf_sz); + struct rx_agg *rx_agg; + unsigned long flags; +- u8 *buf; + + rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node); + if (!rx_agg) + return NULL; + +- buf = kmalloc_node(tp->rx_buf_sz, mflags, node); +- if (!buf) ++ rx_agg->page = alloc_pages(mflags, order); ++ if (!rx_agg->page) + goto free_rx; + +- if (buf != rx_agg_align(buf)) { +- kfree(buf); +- buf = kmalloc_node(tp->rx_buf_sz + RX_ALIGN, mflags, +- node); +- if (!buf) +- goto free_rx; +- } +- +- rx_agg->buffer = buf; +- rx_agg->head = rx_agg_align(buf); ++ rx_agg->buffer = page_address(rx_agg->page); + + rx_agg->urb = usb_alloc_urb(0, mflags); + if (!rx_agg->urb) +@@ -1526,7 +1517,7 @@ static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags) + return rx_agg; + + free_buf: +- kfree(rx_agg->buffer); ++ __free_pages(rx_agg->page, order); + free_rx: + kfree(rx_agg); + return NULL; +@@ -2003,8 +1994,8 @@ static int rx_bottom(struct r8152 *tp, int budget) + if (urb->actual_length < ETH_ZLEN) + goto submit; + +- rx_desc = agg->head; +- rx_data = agg->head; ++ rx_desc = agg->buffer; ++ rx_data = agg->buffer; + len_used += sizeof(struct rx_desc); + + while (urb->actual_length > len_used) { +@@ -2051,7 +2042,7 @@ static int rx_bottom(struct r8152 *tp, int budget) + find_next_rx: + rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); + rx_desc = (struct rx_desc *)rx_data; +- len_used = (int)(rx_data - (u8 *)agg->head); ++ len_used = (int)(rx_data - (u8 *)agg->buffer); + len_used += sizeof(struct rx_desc); + } + +@@ -2162,7 +2153,7 @@ int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) + return 0; + + usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), +- agg->head, tp->rx_buf_sz, ++ agg->buffer, tp->rx_buf_sz, + (usb_complete_t)read_bulk_callback, agg); + + ret = usb_submit_urb(agg->urb, mem_flags); +-- +2.26.2 + diff --git a/patches.suse/random-fix-crash-on-multiple-early-calls-to-add_bootloader_randomness.patch b/patches.suse/random-fix-crash-on-multiple-early-calls-to-add_bootloader_randomness.patch new file mode 100644 index 0000000..94b6c6a --- /dev/null +++ b/patches.suse/random-fix-crash-on-multiple-early-calls-to-add_bootloader_randomness.patch @@ -0,0 +1,65 @@ +From: Dominik Brodowski +Date: Fri, 5 Nov 2021 07:04:36 +0100 +Subject: random: fix crash on multiple early calls to + add_bootloader_randomness() +Patch-mainline: Not yet, in maintainer queue. +References: bsc#1184924 + +If add_bootloader_randomness() or add_hwgenerator_randomness() is +called for the first time during early boot, crng_init equals 0. Then, +crng_fast_load() gets called -- which is safe to do even if the input +pool is not yet properly set up. + +If the added entropy suffices to increase crng_init to 1, future calls +to add_bootloader_randomness() or add_hwgenerator_randomness() used to +progress to credit_entropy_bits(). However, if the input pool is not yet +properly set up, the cmpxchg call within that function can lead to an +infinite recursion. This is not only a hypothetical problem, as qemu +on arm64 may provide bootloader entropy via EFI and via devicetree. + +As crng_global_init_time is set to != 0 once the input pool is properly +set up, check (also) for this condition to determine which branch to take. + +Calls to crng_fast_load() do not modify the input pool; therefore, the +entropy_count for the input pool must not be modified at that early +stage. + +Reported-by: Ivan T. Ivanov +Fixes: 18b915ac6b0a ("efi/random: Treat EFI_RNG_PROTOCOL output as bootloader randomness") +Tested-by: Ivan T. Ivanov +Signed-off-by: Dominik Brodowski +Acked-by: Ivan T. Ivanov +--- + drivers/char/random.c | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +diff --git a/drivers/char/random.c b/drivers/char/random.c +index 605969ed0f96..18fe804c1bf8 100644 +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -1763,8 +1763,8 @@ static void __init init_std_data(struct entropy_store *r) + } + + /* +- * Note that setup_arch() may call add_device_randomness() +- * long before we get here. This allows seeding of the pools ++ * add_device_randomness() or add_bootloader_randomness() may be ++ * called long before we get here. This allows seeding of the pools + * with some platform dependent data very early in the boot + * process. But it limits our options here. We must use + * statically allocated structures that already have all +@@ -2274,7 +2274,12 @@ void add_hwgenerator_randomness(const char *buffer, size_t count, + { + struct entropy_store *poolp = &input_pool; + +- if (unlikely(crng_init == 0)) { ++ /* We cannot do much with the input pool until it is set up in ++ * rand_initalize(); therefore just mix into the crng state. ++ * As this does not affect the input pool, we cannot credit ++ * entropy for this. ++ */ ++ if (unlikely(crng_init == 0 || crng_global_init_time == 0)) { + crng_fast_load(buffer, count); + return; + } + diff --git a/patches.suse/rndis_host-set-proper-input-size-for-OID_GEN_PHYSICA.patch b/patches.suse/rndis_host-set-proper-input-size-for-OID_GEN_PHYSICA.patch new file mode 100644 index 0000000..6de38d3 --- /dev/null +++ b/patches.suse/rndis_host-set-proper-input-size-for-OID_GEN_PHYSICA.patch @@ -0,0 +1,44 @@ +From e56b3d94d939f52d46209b9e1b6700c5bfff3123 Mon Sep 17 00:00:00 2001 +From: Andrey Zhizhikin +Date: Fri, 8 Jan 2021 09:58:39 +0000 +Subject: [PATCH] rndis_host: set proper input size for OID_GEN_PHYSICAL_MEDIUM + request +Git-commit: e56b3d94d939f52d46209b9e1b6700c5bfff3123 +References: git-fixes +Patch-mainline: v5.11-rc4 + +MSFT ActiveSync implementation requires that the size of the response for +incoming query is to be provided in the request input length. Failure to +set the input size proper results in failed request transfer, where the +ActiveSync counterpart reports the NDIS_STATUS_INVALID_LENGTH (0xC0010014L) +error. + +Set the input size for OID_GEN_PHYSICAL_MEDIUM query to the expected size +of the response in order for the ActiveSync to properly respond to the +request. + +Fixes: 039ee17d1baa ("rndis_host: Add RNDIS physical medium checking into generic_rndis_bind()") +Signed-off-by: Andrey Zhizhikin +Link: https://lore.kernel.org/r/20210108095839.3335-1-andrey.zhizhikin@leica-geosystems.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Oliver Neukum +--- + drivers/net/usb/rndis_host.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/usb/rndis_host.c b/drivers/net/usb/rndis_host.c +index 6609d21ef894..f813ca9dec53 100644 +--- a/drivers/net/usb/rndis_host.c ++++ b/drivers/net/usb/rndis_host.c +@@ -387,7 +387,7 @@ generic_rndis_bind(struct usbnet *dev, struct usb_interface *intf, int flags) + reply_len = sizeof *phym; + retval = rndis_query(dev, intf, u.buf, + RNDIS_OID_GEN_PHYSICAL_MEDIUM, +- 0, (void **) &phym, &reply_len); ++ reply_len, (void **)&phym, &reply_len); + if (retval != 0 || !phym) { + /* OID is optional so don't fail here. */ + phym_unspec = cpu_to_le32(RNDIS_PHYSICAL_MEDIUM_UNSPECIFIED); +-- +2.26.2 + diff --git a/patches.suse/s390-dasd-fix-use-after-free-in-dasd-path-handling b/patches.suse/s390-dasd-fix-use-after-free-in-dasd-path-handling new file mode 100644 index 0000000..1c9e5c3 --- /dev/null +++ b/patches.suse/s390-dasd-fix-use-after-free-in-dasd-path-handling @@ -0,0 +1,64 @@ +From: Stefan Haberland +Date: Wed, 4 Aug 2021 17:18:00 +0200 +Subject: s390/dasd: fix use after free in dasd path handling +Git-commit: 952835edb4fdad49361d5330da918be8b765b787 +Patch-mainline: v5.14-rc5 +References: git-fixes + +When new configuration data is obtained after a path event it is stored +in the per path array. The old data needs to be freed. +The first valid configuration data is also referenced in the device +private structure to identify the device. +When the old per path configuration data was freed the device still +pointed to the already freed data leading to a use after free. + +Fix by replacing also the device configuration data with the newly +obtained one before the old data gets freed. + +Fixes: 460181217a24 ("s390/dasd: Store path configuration data during path handling") +Cc: stable@vger.kernel.org # 5.11+ +Signed-off-by: Stefan Haberland +Reviewed-by: Jan Hoeppner +Link: https://lore.kernel.org/r/20210804151800.4031761-2-sth@linux.ibm.com +Signed-off-by: Jens Axboe +Acked-by: Petr Tesarik +--- + drivers/s390/block/dasd_eckd.c | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +--- a/drivers/s390/block/dasd_eckd.c ++++ b/drivers/s390/block/dasd_eckd.c +@@ -1004,15 +1004,23 @@ static unsigned char dasd_eckd_path_acce + static void dasd_eckd_store_conf_data(struct dasd_device *device, + struct dasd_conf_data *conf_data, int chp) + { ++ struct dasd_eckd_private *private = device->private; + struct channel_path_desc_fmt0 *chp_desc; + struct subchannel_id sch_id; ++ void *cdp; + +- ccw_device_get_schid(device->cdev, &sch_id); + /* + * path handling and read_conf allocate data + * free it before replacing the pointer ++ * also replace the old private->conf_data pointer ++ * with the new one if this points to the same data + */ +- kfree(device->path[chp].conf_data); ++ cdp = device->path[chp].conf_data; ++ if (private->conf_data == cdp) { ++ private->conf_data = (void *)conf_data; ++ dasd_eckd_identify_conf_parts(private); ++ } ++ ccw_device_get_schid(device->cdev, &sch_id); + device->path[chp].conf_data = conf_data; + device->path[chp].cssid = sch_id.cssid; + device->path[chp].ssid = sch_id.ssid; +@@ -1020,6 +1028,7 @@ static void dasd_eckd_store_conf_data(st + if (chp_desc) + device->path[chp].chpid = chp_desc->chpid; + kfree(chp_desc); ++ kfree(cdp); + } + + static void dasd_eckd_clear_conf_data(struct dasd_device *device) diff --git a/patches.suse/s390-export-symbols-for-crash-kmp.patch b/patches.suse/s390-export-symbols-for-crash-kmp.patch index e7f23b2..3127846 100644 --- a/patches.suse/s390-export-symbols-for-crash-kmp.patch +++ b/patches.suse/s390-export-symbols-for-crash-kmp.patch @@ -4,7 +4,7 @@ Date: Wed, 16 Aug 2017 13:28:58 +0200 Subject: [PATCH] s390: export symbols for crash-kmp References: bsc#1053915 -Patch-mainline: no, not needed +Patch-mainline: Never, not needed any more but dropping would break kABI Export xlate_dev_mem_ptr and unxlate_dev_mem_ptr diff --git a/patches.suse/s390-pci-fix-use-after-free-of-zpci_dev b/patches.suse/s390-pci-fix-use-after-free-of-zpci_dev new file mode 100644 index 0000000..7ab4bac --- /dev/null +++ b/patches.suse/s390-pci-fix-use-after-free-of-zpci_dev @@ -0,0 +1,80 @@ +From: Niklas Schnelle +Date: Fri, 6 Aug 2021 12:11:16 +0200 +Subject: s390/pci: fix use after free of zpci_dev +Git-commit: 2a671f77ee49f3e78997b77fdee139467ff6a598 +Patch-mainline: v5.14-rc7 +References: git-fixes + +The struct pci_dev uses reference counting but zPCI assumed erroneously +that the last reference would always be the local reference after +calling pci_stop_and_remove_bus_device(). This is usually the case but +not how reference counting works and thus inherently fragile. + +In fact one case where this causes a NULL pointer dereference when on an +SRIOV device the function 0 was hot unplugged before another function of +the same multi-function device. In this case the second function's +pdev->sriov->dev reference keeps the struct pci_dev of function 0 alive +even after the unplug. This bug was previously hidden by the fact that +we were leaking the struct pci_dev which in turn means that it always +outlived the struct zpci_dev. This was fixed in commit 0b13525c20fe +("s390/pci: fix leak of PCI device structure") exposing the broken +behavior. + +Fix this by accounting for the long living reference a struct pci_dev +has to its underlying struct zpci_dev via the zbus->function[] array and +only release that in pcibios_release_device() ensuring that the struct +pci_dev is not left with a dangling reference. This is a minimal fix in +the future it would probably better to use fine grained reference +counting for struct zpci_dev. + +Fixes: 05bc1be6db4b2 ("s390/pci: create zPCI bus") +Cc: stable@vger.kernel.org +Reviewed-by: Matthew Rosato +Signed-off-by: Niklas Schnelle +Signed-off-by: Vasily Gorbik +Acked-by: Petr Tesarik +--- + arch/s390/pci/pci.c | 6 ++++++ + arch/s390/pci/pci_bus.h | 5 +++++ + 2 files changed, 11 insertions(+) + +--- a/arch/s390/pci/pci.c ++++ b/arch/s390/pci/pci.c +@@ -550,9 +550,12 @@ static void zpci_cleanup_bus_resources(s + + int pcibios_add_device(struct pci_dev *pdev) + { ++ struct zpci_dev *zdev = to_zpci(pdev); + struct resource *res; + int i; + ++ /* The pdev has a reference to the zdev via its bus */ ++ zpci_zdev_get(zdev); + if (pdev->is_physfn) + pdev->no_vf_scan = 1; + +@@ -572,7 +575,10 @@ int pcibios_add_device(struct pci_dev *p + + void pcibios_release_device(struct pci_dev *pdev) + { ++ struct zpci_dev *zdev = to_zpci(pdev); ++ + zpci_unmap_resources(pdev); ++ zpci_zdev_put(zdev); + } + + int pcibios_enable_device(struct pci_dev *pdev, int mask) +--- a/arch/s390/pci/pci_bus.h ++++ b/arch/s390/pci/pci_bus.h +@@ -17,6 +17,11 @@ static inline void zpci_zdev_put(struct + kref_put(&zdev->kref, zpci_release_device); + } + ++static inline void zpci_zdev_get(struct zpci_dev *zdev) ++{ ++ kref_get(&zdev->kref); ++} ++ + int zpci_alloc_domain(int domain); + void zpci_free_domain(int domain); + int zpci_setup_bus_resources(struct zpci_dev *zdev, diff --git a/patches.suse/s390-pci-fix-zpci_zdev_put-on-reserve b/patches.suse/s390-pci-fix-zpci_zdev_put-on-reserve new file mode 100644 index 0000000..64bc254 --- /dev/null +++ b/patches.suse/s390-pci-fix-zpci_zdev_put-on-reserve @@ -0,0 +1,168 @@ +From: Niklas Schnelle +Date: Wed, 22 Sep 2021 15:55:12 +0200 +Subject: s390/pci: fix zpci_zdev_put() on reserve +Git-commit: a46044a92add6a400f4dada7b943b30221f7cc80 +Patch-mainline: v5.15-rc5 +References: git-fixes + +Since commit 2a671f77ee49 ("s390/pci: fix use after free of zpci_dev") +the reference count of a zpci_dev is incremented between +pcibios_add_device() and pcibios_release_device() which was supposed to +prevent the zpci_dev from being freed while the common PCI code has +access to it. It was missed however that the handling of zPCI +availability events assumed that once zpci_zdev_put() was called no +later availability event would still see the device. With the previously +mentioned commit however this assumption no longer holds and we must +make sure that we only drop the initial long-lived reference the zPCI +subsystem holds exactly once. + +Do so by introducing a zpci_device_reserved() function that handles when +a device is reserved. Here we make sure the zpci_dev will not be +considered for further events by removing it from the zpci_list. + +This also means that the device actually stays in the +ZPCI_FN_STATE_RESERVED state between the time we know it has been +reserved and the final reference going away. We thus need to consider it +a real state instead of just a conceptual state after the removal. The +final cleanup of PCI resources, removal from zbus, and destruction of +the IOMMU stays in zpci_release_device() to make sure holders of the +reference do see valid data until the release. + +Fixes: 2a671f77ee49 ("s390/pci: fix use after free of zpci_dev") +Cc: stable@vger.kernel.org +Signed-off-by: Niklas Schnelle +Signed-off-by: Vasily Gorbik +[ ptesarik: Adapted, because SLE15-SP3 does not contain mainline + commit dee60c0dbc837ddca8abcb868e53ca3e9d11ea4c and follow-up fixes. ] +Signed-off-by: Petr Tesarik +--- + arch/s390/include/asm/pci.h | 2 + + arch/s390/pci/pci.c | 45 ++++++++++++++++++++++++++++++++----- + arch/s390/pci/pci_event.c | 4 +-- + drivers/pci/hotplug/s390_pci_hpc.c | 9 ------- + 4 files changed, 45 insertions(+), 15 deletions(-) + +--- a/arch/s390/include/asm/pci.h ++++ b/arch/s390/include/asm/pci.h +@@ -204,6 +204,8 @@ int zpci_create_device(struct zpci_dev * + void zpci_remove_device(struct zpci_dev *zdev, bool set_error); + int zpci_enable_device(struct zpci_dev *); + int zpci_disable_device(struct zpci_dev *); ++void zpci_device_reserved(struct zpci_dev *zdev); ++bool zpci_is_device_configured(struct zpci_dev *zdev); + int zpci_register_ioat(struct zpci_dev *, u8, u64, u64, u64); + int zpci_unregister_ioat(struct zpci_dev *, u8); + void zpci_remove_reserved_devices(void); +--- a/arch/s390/pci/pci.c ++++ b/arch/s390/pci/pci.c +@@ -90,7 +90,7 @@ void zpci_remove_reserved_devices(void) + spin_unlock(&zpci_list_lock); + + list_for_each_entry_safe(zdev, tmp, &remove, entry) +- zpci_zdev_put(zdev); ++ zpci_device_reserved(zdev); + } + + int pci_domain_nr(struct pci_bus *bus) +@@ -796,6 +796,39 @@ out: + return rc; + } + ++bool zpci_is_device_configured(struct zpci_dev *zdev) ++{ ++ enum zpci_state state = zdev->state; ++ ++ return state != ZPCI_FN_STATE_RESERVED && ++ state != ZPCI_FN_STATE_STANDBY; ++} ++ ++/** ++ * zpci_device_reserved() - Mark device as resverved ++ * @zdev: the zpci_dev that was reserved ++ * ++ * Handle the case that a given zPCI function was reserved by another system. ++ * After a call to this function the zpci_dev can not be found via ++ * get_zdev_by_fid() anymore but may still be accessible via existing ++ * references though it will not be functional anymore. ++ */ ++void zpci_device_reserved(struct zpci_dev *zdev) ++{ ++ if (zdev->has_hp_slot) ++ zpci_exit_slot(zdev); ++ /* ++ * Remove device from zpci_list as it is going away. This also ++ * makes sure we ignore subsequent zPCI events for this device. ++ */ ++ spin_lock(&zpci_list_lock); ++ list_del(&zdev->entry); ++ spin_unlock(&zpci_list_lock); ++ zdev->state = ZPCI_FN_STATE_RESERVED; ++ zpci_dbg(3, "rsv fid:%x\n", zdev->fid); ++ zpci_zdev_put(zdev); ++} ++ + void zpci_release_device(struct kref *kref) + { + struct zpci_dev *zdev = container_of(kref, struct zpci_dev, kref); +@@ -811,6 +844,12 @@ void zpci_release_device(struct kref *kr + case ZPCI_FN_STATE_STANDBY: + if (zdev->has_hp_slot) + zpci_exit_slot(zdev); ++ spin_lock(&zpci_list_lock); ++ list_del(&zdev->entry); ++ spin_unlock(&zpci_list_lock); ++ zpci_dbg(3, "rsv fid:%x\n", zdev->fid); ++ fallthrough; ++ case ZPCI_FN_STATE_RESERVED: + zpci_cleanup_bus_resources(zdev); + zpci_bus_device_unregister(zdev); + zpci_destroy_iommu(zdev); +@@ -818,10 +857,6 @@ void zpci_release_device(struct kref *kr + default: + break; + } +- +- spin_lock(&zpci_list_lock); +- list_del(&zdev->entry); +- spin_unlock(&zpci_list_lock); + zpci_dbg(3, "rem fid:%x\n", zdev->fid); + kfree(zdev); + } +--- a/arch/s390/pci/pci_event.c ++++ b/arch/s390/pci/pci_event.c +@@ -146,7 +146,7 @@ static void __zpci_event_availability(st + zdev->state = ZPCI_FN_STATE_STANDBY; + if (!clp_get_state(ccdf->fid, &state) && + state == ZPCI_FN_STATE_RESERVED) { +- zpci_zdev_put(zdev); ++ zpci_device_reserved(zdev); + } + break; + case 0x0306: /* 0x308 or 0x302 for multiple devices */ +@@ -155,7 +155,7 @@ static void __zpci_event_availability(st + case 0x0308: /* Standby -> Reserved */ + if (!zdev) + break; +- zpci_zdev_put(zdev); ++ zpci_device_reserved(zdev); + break; + default: + break; +--- a/drivers/pci/hotplug/s390_pci_hpc.c ++++ b/drivers/pci/hotplug/s390_pci_hpc.c +@@ -109,14 +109,7 @@ static int get_power_status(struct hotpl + struct zpci_dev *zdev = container_of(hotplug_slot, struct zpci_dev, + hotplug_slot); + +- switch (zdev->state) { +- case ZPCI_FN_STATE_STANDBY: +- *value = 0; +- break; +- default: +- *value = 1; +- break; +- } ++ *value = zpci_is_device_configured(zdev) ? 1 : 0; + return 0; + } + diff --git a/patches.suse/s390-qeth-Fix-deadlock-in-remove_discipline b/patches.suse/s390-qeth-Fix-deadlock-in-remove_discipline new file mode 100644 index 0000000..fdedf10 --- /dev/null +++ b/patches.suse/s390-qeth-Fix-deadlock-in-remove_discipline @@ -0,0 +1,112 @@ +From: Alexandra Winter +Date: Tue, 21 Sep 2021 16:52:16 +0200 +Subject: s390/qeth: Fix deadlock in remove_discipline +Git-commit: ee909d0b1dac8632eeb78cbf17661d6c7674bbd0 +Patch-mainline: v5.15-rc3 +References: git-fixes + +Problem: qeth_close_dev_handler is a worker that tries to acquire +card->discipline_mutex via drv->set_offline() in ccwgroup_set_offline(). +Since commit b41b554c1ee7 +("s390/qeth: fix locking for discipline setup / removal") +qeth_remove_discipline() is called under card->discipline_mutex and +cancels the work and waits for it to finish. + +STOPLAN reception with reason code IPA_RC_VEPA_TO_VEB_TRANSITION is the +only situation that schedules close_dev_work. In that situation scheduling +qeth recovery will also result in an offline interface, when resetting the +isolation mode fails, if the external switch is still set to VEB. +And since commit 0b9902c1fcc5 ("s390/qeth: fix deadlock during recovery") +qeth recovery does not aquire card->discipline_mutex anymore. + +So we accept the longer pathlength of qeth_schedule_recovery in this +error situation and re-use the existing function. + +As a side-benefit this changes the hwtrap to behave like during recovery +instead of like during a user-triggered set_offline. + +Fixes: b41b554c1ee7 ("s390/qeth: fix locking for discipline setup / removal") +Signed-off-by: Alexandra Winter +Acked-by: Julian Wiedmann +Signed-off-by: Julian Wiedmann +Signed-off-by: Jakub Kicinski +Acked-by: Petr Tesarik +--- + drivers/s390/net/qeth_core.h | 1 - + drivers/s390/net/qeth_core_main.c | 16 ++++------------ + drivers/s390/net/qeth_l2_main.c | 1 - + drivers/s390/net/qeth_l3_main.c | 1 - + 4 files changed, 4 insertions(+), 15 deletions(-) + +--- a/drivers/s390/net/qeth_core.h ++++ b/drivers/s390/net/qeth_core.h +@@ -857,7 +857,6 @@ struct qeth_card { + struct napi_struct napi; + struct qeth_rx rx; + struct delayed_work buffer_reclaim_work; +- struct work_struct close_dev_work; + }; + + static inline bool qeth_card_hw_is_reachable(struct qeth_card *card) +--- a/drivers/s390/net/qeth_core_main.c ++++ b/drivers/s390/net/qeth_core_main.c +@@ -73,15 +73,6 @@ static void qeth_notify_skbs(struct qeth + enum iucv_tx_notify notification); + static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *, int); + +-static void qeth_close_dev_handler(struct work_struct *work) +-{ +- struct qeth_card *card; +- +- card = container_of(work, struct qeth_card, close_dev_work); +- QETH_CARD_TEXT(card, 2, "cldevhdl"); +- ccwgroup_set_offline(card->gdev); +-} +- + static const char *qeth_get_cardname(struct qeth_card *card) + { + if (IS_VM_NIC(card)) { +@@ -888,10 +888,12 @@ static struct qeth_ipa_cmd *qeth_check_i + case IPA_CMD_STOPLAN: + if (cmd->hdr.return_code == IPA_RC_VEPA_TO_VEB_TRANSITION) { + dev_err(&card->gdev->dev, +- "Interface %s is down because the adjacent port is no longer in reflective relay mode\n", ++ "Adjacent port of interface %s is no longer in reflective relay mode, trigger recovery\n", + netdev_name(card->dev)); +- schedule_work(&card->close_dev_work); ++ /* Set offline, then probably fail to set online: */ ++ qeth_schedule_recovery(card); + } else { ++ /* stay online for subsequent STARTLAN */ + dev_warn(&card->gdev->dev, + "The link for interface %s on CHPID 0x%X failed\n", + netdev_name(card->dev), card->info.chpid); +@@ -1627,7 +1629,6 @@ static void qeth_setup_card(struct qeth_ + INIT_LIST_HEAD(&card->ipato.entries); + qeth_init_qdio_info(card); + INIT_DELAYED_WORK(&card->buffer_reclaim_work, qeth_buffer_reclaim_work); +- INIT_WORK(&card->close_dev_work, qeth_close_dev_handler); + hash_init(card->rx_mode_addrs); + hash_init(card->local_addrs4); + hash_init(card->local_addrs6); +static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr) +--- a/drivers/s390/net/qeth_l2_main.c ++++ b/drivers/s390/net/qeth_l2_main.c +@@ -2207,7 +2207,6 @@ static void qeth_l2_remove_device(struct + if (gdev->state == CCWGROUP_ONLINE) + qeth_set_offline(card, card->discipline, false); + +- cancel_work_sync(&card->close_dev_work); + if (card->dev->reg_state == NETREG_REGISTERED) + unregister_netdev(card->dev); + } +--- a/drivers/s390/net/qeth_l3_main.c ++++ b/drivers/s390/net/qeth_l3_main.c +@@ -1976,7 +1976,6 @@ static void qeth_l3_remove_device(struct + if (cgdev->state == CCWGROUP_ONLINE) + qeth_set_offline(card, card->discipline, false); + +- cancel_work_sync(&card->close_dev_work); + if (card->dev->reg_state == NETREG_REGISTERED) + unregister_netdev(card->dev); + diff --git a/patches.suse/s390-qeth-fix-NULL-deref-in-qeth_clear_working_pool_list b/patches.suse/s390-qeth-fix-NULL-deref-in-qeth_clear_working_pool_list new file mode 100644 index 0000000..1651c9c --- /dev/null +++ b/patches.suse/s390-qeth-fix-NULL-deref-in-qeth_clear_working_pool_list @@ -0,0 +1,53 @@ +From: Julian Wiedmann +Date: Tue, 21 Sep 2021 16:52:15 +0200 +Subject: s390/qeth: fix NULL deref in qeth_clear_working_pool_list() +Git-commit: 248f064af222a1f97ee02c84a98013dfbccad386 +Patch-mainline: v5.15-rc3 +References: git-fixes + +When qeth_set_online() calls qeth_clear_working_pool_list() to roll +back after an error exit from qeth_hardsetup_card(), we are at risk of +accessing card->qdio.in_q before it was allocated by +qeth_alloc_qdio_queues() via qeth_mpc_initialize(). + +qeth_clear_working_pool_list() then dereferences NULL, and by writing to +queue->bufs[i].pool_entry scribbles all over the CPU's lowcore. +Resulting in a crash when those lowcore areas are used next (eg. on +the next machine-check interrupt). + +Such a scenario would typically happen when the device is first set +online and its queues aren't allocated yet. An early IO error or certain +misconfigs (eg. mismatched transport mode, bad portno) then cause us to +error out from qeth_hardsetup_card() with card->qdio.in_q still being +NULL. + +Fix it by checking the pointer for NULL before accessing it. + +Note that we also have (rare) paths inside qeth_mpc_initialize() where +a configuration change can cause us to free the existing queues, +expecting that subsequent code will allocate them again. If we then +error out before that re-allocation happens, the same bug occurs. + +Fixes: eff73e16ee11 ("s390/qeth: tolerate pre-filled RX buffer") +Reported-by: Stefan Raspl +Root-caused-by: Heiko Carstens +Signed-off-by: Julian Wiedmann +Reviewed-by: Alexandra Winter +Signed-off-by: Jakub Kicinski +Acked-by: Petr Tesarik +--- + drivers/s390/net/qeth_core_main.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/s390/net/qeth_core_main.c ++++ b/drivers/s390/net/qeth_core_main.c +@@ -211,6 +211,9 @@ static void qeth_clear_working_pool_list + &card->qdio.in_buf_pool.entry_list, list) + list_del(&pool_entry->list); + ++ if (!queue) ++ return; ++ + for (i = 0; i < ARRAY_SIZE(queue->bufs); i++) + queue->bufs[i].pool_entry = NULL; + } diff --git a/patches.suse/s390-qeth-fix-deadlock-during-failing-recovery b/patches.suse/s390-qeth-fix-deadlock-during-failing-recovery new file mode 100644 index 0000000..1f4a9be --- /dev/null +++ b/patches.suse/s390-qeth-fix-deadlock-during-failing-recovery @@ -0,0 +1,96 @@ +From: Alexandra Winter +Date: Tue, 21 Sep 2021 16:52:17 +0200 +Subject: s390/qeth: fix deadlock during failing recovery +Git-commit: d2b59bd4b06d84a4eadb520b0f71c62fe8ec0a62 +Patch-mainline: v5.15-rc3 +References: git-fixes + +Commit 0b9902c1fcc5 ("s390/qeth: fix deadlock during recovery") removed +taking discipline_mutex inside qeth_do_reset(), fixing potential +deadlocks. An error path was missed though, that still takes +discipline_mutex and thus has the original deadlock potential. + +Intermittent deadlocks were seen when a qeth channel path is configured +offline, causing a race between qeth_do_reset and ccwgroup_remove. +Call qeth_set_offline() directly in the qeth_do_reset() error case and +then a new variant of ccwgroup_set_offline(), without taking +discipline_mutex. + +Fixes: b41b554c1ee7 ("s390/qeth: fix locking for discipline setup / removal") +Signed-off-by: Alexandra Winter +Reviewed-by: Julian Wiedmann +Signed-off-by: Julian Wiedmann +Signed-off-by: Jakub Kicinski +Acked-by: Petr Tesarik +--- + arch/s390/include/asm/ccwgroup.h | 2 +- + drivers/s390/cio/ccwgroup.c | 10 ++++++++-- + drivers/s390/net/qeth_core_main.c | 3 ++- + 3 files changed, 11 insertions(+), 4 deletions(-) + +--- a/arch/s390/include/asm/ccwgroup.h ++++ b/arch/s390/include/asm/ccwgroup.h +@@ -68,7 +68,7 @@ struct ccwgroup_device *get_ccwgroupdev_ + char *bus_id); + + extern int ccwgroup_set_online(struct ccwgroup_device *gdev); +-extern int ccwgroup_set_offline(struct ccwgroup_device *gdev); ++int ccwgroup_set_offline(struct ccwgroup_device *gdev, bool call_gdrv); + + extern int ccwgroup_probe_ccwdev(struct ccw_device *cdev); + extern void ccwgroup_remove_ccwdev(struct ccw_device *cdev); +--- a/drivers/s390/cio/ccwgroup.c ++++ b/drivers/s390/cio/ccwgroup.c +@@ -98,12 +98,13 @@ EXPORT_SYMBOL(ccwgroup_set_online); + /** + * ccwgroup_set_offline() - disable a ccwgroup device + * @gdev: target ccwgroup device ++ * @call_gdrv: Call the registered gdrv set_offline function + * + * This function attempts to put the ccwgroup device into the offline state. + * Returns: + * %0 on success and a negative error value on failure. + */ +-int ccwgroup_set_offline(struct ccwgroup_device *gdev) ++int ccwgroup_set_offline(struct ccwgroup_device *gdev, bool call_gdrv) + { + struct ccwgroup_driver *gdrv = to_ccwgroupdrv(gdev->dev.driver); + int ret = -EINVAL; +@@ -112,11 +113,16 @@ int ccwgroup_set_offline(struct ccwgroup + return -EAGAIN; + if (gdev->state == CCWGROUP_OFFLINE) + goto out; ++ if (!call_gdrv) { ++ ret = 0; ++ goto offline; ++ } + if (gdrv->set_offline) + ret = gdrv->set_offline(gdev); + if (ret) + goto out; + ++offline: + gdev->state = CCWGROUP_OFFLINE; + out: + atomic_set(&gdev->onoff, 0); +@@ -145,7 +151,7 @@ static ssize_t ccwgroup_online_store(str + if (value == 1) + ret = ccwgroup_set_online(gdev); + else if (value == 0) +- ret = ccwgroup_set_offline(gdev); ++ ret = ccwgroup_set_offline(gdev, true); + else + ret = -EINVAL; + out: +--- a/drivers/s390/net/qeth_core_main.c ++++ b/drivers/s390/net/qeth_core_main.c +@@ -5174,7 +5174,8 @@ static int qeth_do_reset(void *data) + dev_info(&card->gdev->dev, + "Device successfully recovered!\n"); + } else { +- ccwgroup_set_offline(card->gdev); ++ qeth_set_offline(card, disc, true); ++ ccwgroup_set_offline(card->gdev, false); + dev_warn(&card->gdev->dev, + "The qeth device driver failed to recover an error on the device\n"); + } diff --git a/patches.suse/s390-topology-clear-thread-group-maps-for-offline-cpus b/patches.suse/s390-topology-clear-thread-group-maps-for-offline-cpus new file mode 100644 index 0000000..91236a6 --- /dev/null +++ b/patches.suse/s390-topology-clear-thread-group-maps-for-offline-cpus @@ -0,0 +1,78 @@ +From: Sven Schnelle +Date: Tue, 15 Jun 2021 15:05:22 +0200 +Subject: s390/topology: clear thread/group maps for offline cpus +Git-commit: 9e3d62d55bf455d4f9fdf2ede5c8756410c64102 +Patch-mainline: v5.13 +References: git-fixes + +The current code doesn't clear the thread/group maps for offline +CPUs. This may cause kernel crashes like the one bewlow in common +code that assumes if a CPU has sibblings it is online. + +Unable to handle kernel pointer dereference in virtual kernel address space + +Call Trace: + [<000000013a4b8c3c>] blk_mq_map_swqueue+0x10c/0x388 +([<000000013a4b8bcc>] blk_mq_map_swqueue+0x9c/0x388) + [<000000013a4b9300>] blk_mq_init_allocated_queue+0x448/0x478 + [<000000013a4b9416>] blk_mq_init_queue+0x4e/0x90 + [<000003ff8019d3e6>] loop_add+0x106/0x278 [loop] + [<000003ff801b8148>] loop_init+0x148/0x1000 [loop] + [<0000000139de4924>] do_one_initcall+0x3c/0x1e0 + [<0000000139ef449a>] do_init_module+0x6a/0x2a0 + [<0000000139ef61bc>] __do_sys_finit_module+0xa4/0xc0 + [<0000000139de9e6e>] do_syscall+0x7e/0xd0 + [<000000013a8e0aec>] __do_syscall+0xbc/0x110 + [<000000013a8ee2e8>] system_call+0x78/0xa0 + +Fixes: 52aeda7accb6 ("s390/topology: remove offline CPUs from CPU topology masks") +Cc: # 5.7+ +Reported-by: Marius Hillenbrand +Signed-off-by: Sven Schnelle +Reviewed-by: Heiko Carstens +Signed-off-by: Vasily Gorbik +[ ptesarik: Adapted, because SLE15-SP3 does not contain upstream + commit da6d2c289dbe8871f1977bf7c348309d37b867b0. ] +Signed-off-by: Petr Tesarik +--- + arch/s390/kernel/topology.c | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +--- a/arch/s390/kernel/topology.c ++++ b/arch/s390/kernel/topology.c +@@ -69,7 +69,10 @@ static cpumask_t cpu_group_map(struct ma + { + cpumask_t mask; + +- cpumask_copy(&mask, cpumask_of(cpu)); ++ cpumask_clear(&mask); ++ if (!cpu_online(cpu)) ++ goto out; ++ cpumask_set_cpu(cpu, &mask); + switch (topology_mode) { + case TOPOLOGY_MODE_HW: + while (info) { +@@ -88,10 +91,10 @@ static cpumask_t cpu_group_map(struct ma + default: + /* fallthrough */ + case TOPOLOGY_MODE_SINGLE: +- cpumask_copy(&mask, cpumask_of(cpu)); + break; + } + cpumask_and(&mask, &mask, cpu_online_mask); ++out: + return mask; + } + +@@ -100,7 +103,10 @@ static cpumask_t cpu_thread_map(unsigned + cpumask_t mask; + int i; + +- cpumask_copy(&mask, cpumask_of(cpu)); ++ cpumask_clear(&mask); ++ if (!cpu_online(cpu)) ++ return mask; ++ cpumask_set_cpu(cpu, &mask); + if (topology_mode != TOPOLOGY_MODE_HW) + return mask; + cpu -= cpu % (smp_cpu_mtid + 1); diff --git a/patches.suse/scsi-BusLogic-Fix-missing-pr_cont-use b/patches.suse/scsi-BusLogic-Fix-missing-pr_cont-use new file mode 100644 index 0000000..ec0d288 --- /dev/null +++ b/patches.suse/scsi-BusLogic-Fix-missing-pr_cont-use @@ -0,0 +1,109 @@ +From: "Maciej W. Rozycki" +Date: Tue, 20 Apr 2021 20:01:47 +0200 +Subject: scsi: BusLogic: Fix missing pr_cont() use +Git-commit: 44d01fc86d952f5a8b8b32bdb4841504d5833d95 +Patch-mainline: v5.15-rc1 +References: git-fixes + +Update BusLogic driver's messaging system to use pr_cont() for continuation +lines, bringing messy output: + +pci 0000:00:13.0: PCI->APIC IRQ transform: INT A -> IRQ 17 +scsi: ***** BusLogic SCSI Driver Version 2.1.17 of 12 September 2013 ***** +scsi: Copyright 1995-1998 by Leonard N. Zubkoff +scsi0: Configuring BusLogic Model BT-958 PCI Wide Ultra SCSI Host Adapter +scsi0: Firmware Version: 5.07B, I/O Address: 0x7000, IRQ Channel: 17/Level +scsi0: PCI Bus: 0, Device: 19, Address: +0xE0012000, +Host Adapter SCSI ID: 7 +scsi0: Parity Checking: Enabled, Extended Translation: Enabled +scsi0: Synchronous Negotiation: Ultra, Wide Negotiation: Enabled +scsi0: Disconnect/Reconnect: Enabled, Tagged Queuing: Enabled +scsi0: Scatter/Gather Limit: 128 of 8192 segments, Mailboxes: 211 +scsi0: Driver Queue Depth: 211, Host Adapter Queue Depth: 192 +scsi0: Tagged Queue Depth: +Automatic +, Untagged Queue Depth: 3 +scsi0: SCSI Bus Termination: Both Enabled +, SCAM: Disabled + +scsi0: *** BusLogic BT-958 Initialized Successfully *** +scsi host0: BusLogic BT-958 + +back to order: + +pci 0000:00:13.0: PCI->APIC IRQ transform: INT A -> IRQ 17 +scsi: ***** BusLogic SCSI Driver Version 2.1.17 of 12 September 2013 ***** +scsi: Copyright 1995-1998 by Leonard N. Zubkoff +scsi0: Configuring BusLogic Model BT-958 PCI Wide Ultra SCSI Host Adapter +scsi0: Firmware Version: 5.07B, I/O Address: 0x7000, IRQ Channel: 17/Level +scsi0: PCI Bus: 0, Device: 19, Address: 0xE0012000, Host Adapter SCSI ID: 7 +scsi0: Parity Checking: Enabled, Extended Translation: Enabled +scsi0: Synchronous Negotiation: Ultra, Wide Negotiation: Enabled +scsi0: Disconnect/Reconnect: Enabled, Tagged Queuing: Enabled +scsi0: Scatter/Gather Limit: 128 of 8192 segments, Mailboxes: 211 +scsi0: Driver Queue Depth: 211, Host Adapter Queue Depth: 192 +scsi0: Tagged Queue Depth: Automatic, Untagged Queue Depth: 3 +scsi0: SCSI Bus Termination: Both Enabled, SCAM: Disabled +scsi0: *** BusLogic BT-958 Initialized Successfully *** +scsi host0: BusLogic BT-958 + +Also diagnostic output such as with the BusLogic=TraceConfiguration +parameter is affected and becomes vertical and therefore hard to read. +This has now been corrected, e.g.: + +pci 0000:00:13.0: PCI->APIC IRQ transform: INT A -> IRQ 17 +blogic_cmd(86) Status = 30: 4 ==> 4: FF 05 93 00 +blogic_cmd(95) Status = 28: (Modify I/O Address) +blogic_cmd(91) Status = 30: 1 ==> 1: 01 +blogic_cmd(04) Status = 30: 4 ==> 4: 41 41 35 30 +blogic_cmd(8D) Status = 30: 14 ==> 14: 45 DC 00 20 00 00 00 00 00 40 30 37 42 1D +scsi: ***** BusLogic SCSI Driver Version 2.1.17 of 12 September 2013 ***** +scsi: Copyright 1995-1998 by Leonard N. Zubkoff +blogic_cmd(04) Status = 30: 4 ==> 4: 41 41 35 30 +blogic_cmd(0B) Status = 30: 3 ==> 3: 00 08 07 +blogic_cmd(0D) Status = 30: 34 ==> 34: 03 01 07 04 00 00 00 00 00 00 00 00 00 00 00 00 FF 42 44 46 FF 00 00 00 00 00 00 00 00 00 FF 00 FF 00 +blogic_cmd(8D) Status = 30: 14 ==> 14: 45 DC 00 20 00 00 00 00 00 40 30 37 42 1D +blogic_cmd(84) Status = 30: 1 ==> 1: 37 +blogic_cmd(8B) Status = 30: 5 ==> 5: 39 35 38 20 20 +blogic_cmd(85) Status = 30: 1 ==> 1: 42 +blogic_cmd(86) Status = 30: 4 ==> 4: FF 05 93 00 +blogic_cmd(91) Status = 30: 64 ==> 64: 41 46 3E 20 39 35 38 20 20 00 C4 00 04 01 07 2F 07 04 35 FF FF FF FF FF FF FF FF FF FF 01 00 FE FF 08 FF FF 00 00 00 00 00 00 00 01 00 01 00 00 FF FF 00 00 00 00 00 00 00 00 00 00 00 00 00 FC +scsi0: Configuring BusLogic Model BT-958 PCI Wide Ultra SCSI Host Adapter + +etc. + +Link: https://lore.kernel.org/r/alpine.DEB.2.21.2104201940430.44318@angie.orcam.me.uk +Fixes: 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") +Cc: stable@vger.kernel.org # v4.9+ +Acked-by: Khalid Aziz +Signed-off-by: Maciej W. Rozycki +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/BusLogic.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/scsi/BusLogic.c b/drivers/scsi/BusLogic.c +index adddcd589941..4d8556fb5c68 100644 +--- a/drivers/scsi/BusLogic.c ++++ b/drivers/scsi/BusLogic.c +@@ -3451,7 +3451,7 @@ static void blogic_msg(enum blogic_msglevel msglevel, char *fmt, + if (buf[0] != '\n' || len > 1) + printk("%sscsi%d: %s", blogic_msglevelmap[msglevel], adapter->host_no, buf); + } else +- printk("%s", buf); ++ pr_cont("%s", buf); + } else { + if (begin) { + if (adapter != NULL && adapter->adapter_initd) +@@ -3459,7 +3459,7 @@ static void blogic_msg(enum blogic_msglevel msglevel, char *fmt, + else + printk("%s%s", blogic_msglevelmap[msglevel], buf); + } else +- printk("%s", buf); ++ pr_cont("%s", buf); + } + begin = (buf[len - 1] == '\n'); + } + diff --git a/patches.suse/scsi-FlashPoint-Rename-si_flags-field b/patches.suse/scsi-FlashPoint-Rename-si_flags-field new file mode 100644 index 0000000..c550913 --- /dev/null +++ b/patches.suse/scsi-FlashPoint-Rename-si_flags-field @@ -0,0 +1,159 @@ +From: Randy Dunlap +Date: Sat, 29 May 2021 16:48:57 -0700 +Subject: scsi: FlashPoint: Rename si_flags field +Git-commit: 4d431153e751caa93f3b7e6f6313446974e92253 +Patch-mainline: v5.14-rc1 +References: git-fixes + +The BusLogic driver has build errors on ia64 due to a name collision (in +the #included FlashPoint.c file). Rename the struct field in struct +sccb_mgr_info from si_flags to si_mflags (manager flags) to mend the build. + +This is the first problem. There are 50+ others after this one: + +In file included from ../include/uapi/linux/signal.h:6, + from ../include/linux/signal_types.h:10, + from ../include/linux/sched.h:29, + from ../include/linux/hardirq.h:9, + from ../include/linux/interrupt.h:11, + from ../drivers/scsi/BusLogic.c:27: +../arch/ia64/include/uapi/asm/siginfo.h:15:27: error: expected ':', ',', ';', '}' or '__attribute__' before '.' token + 15 | #define si_flags _sifields._sigfault._flags + | ^ +../drivers/scsi/FlashPoint.c:43:6: note: in expansion of macro 'si_flags' + 43 | u16 si_flags; + | ^~~~~~~~ +In file included from ../drivers/scsi/BusLogic.c:51: +../drivers/scsi/FlashPoint.c: In function 'FlashPoint_ProbeHostAdapter': +../drivers/scsi/FlashPoint.c:1076:11: error: 'struct sccb_mgr_info' has no member named '_sifields' + 1076 | pCardInfo->si_flags = 0x0000; + | ^~ +../drivers/scsi/FlashPoint.c:1079:12: error: 'struct sccb_mgr_info' has no member named '_sifields' + +Link: https://lore.kernel.org/r/20210529234857.6870-1-rdunlap@infradead.org +Fixes: 391e2f25601e ("[SCSI] BusLogic: Port driver to 64-bit.") +Cc: "James E.J. Bottomley" +Cc: "Martin K. Petersen" +Cc: Christoph Hellwig +Cc: Jens Axboe +Cc: Hannes Reinecke +Cc: Khalid Aziz +Cc: Khalid Aziz +Reported-by: kernel test robot +Reviewed-by: Hannes Reinecke +Signed-off-by: Randy Dunlap +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/FlashPoint.c | 32 ++++++++++++++++---------------- + 1 file changed, 16 insertions(+), 16 deletions(-) + +diff --git a/drivers/scsi/FlashPoint.c b/drivers/scsi/FlashPoint.c +index 0464e37c806a..2e25ef67825a 100644 +--- a/drivers/scsi/FlashPoint.c ++++ b/drivers/scsi/FlashPoint.c +@@ -40,7 +40,7 @@ struct sccb_mgr_info { + u16 si_per_targ_ultra_nego; + u16 si_per_targ_no_disc; + u16 si_per_targ_wide_nego; +- u16 si_flags; ++ u16 si_mflags; + unsigned char si_card_family; + unsigned char si_bustype; + unsigned char si_card_model[3]; +@@ -1073,22 +1073,22 @@ static int FlashPoint_ProbeHostAdapter(struct sccb_mgr_info *pCardInfo) + ScamFlg = + (unsigned char)FPT_utilEERead(ioport, SCAM_CONFIG / 2); + +- pCardInfo->si_flags = 0x0000; ++ pCardInfo->si_mflags = 0x0000; + + if (i & 0x01) +- pCardInfo->si_flags |= SCSI_PARITY_ENA; ++ pCardInfo->si_mflags |= SCSI_PARITY_ENA; + + if (!(i & 0x02)) +- pCardInfo->si_flags |= SOFT_RESET; ++ pCardInfo->si_mflags |= SOFT_RESET; + + if (i & 0x10) +- pCardInfo->si_flags |= EXTENDED_TRANSLATION; ++ pCardInfo->si_mflags |= EXTENDED_TRANSLATION; + + if (ScamFlg & SCAM_ENABLED) +- pCardInfo->si_flags |= FLAG_SCAM_ENABLED; ++ pCardInfo->si_mflags |= FLAG_SCAM_ENABLED; + + if (ScamFlg & SCAM_LEVEL2) +- pCardInfo->si_flags |= FLAG_SCAM_LEVEL2; ++ pCardInfo->si_mflags |= FLAG_SCAM_LEVEL2; + + j = (RD_HARPOON(ioport + hp_bm_ctrl) & ~SCSI_TERM_ENA_L); + if (i & 0x04) { +@@ -1104,7 +1104,7 @@ static int FlashPoint_ProbeHostAdapter(struct sccb_mgr_info *pCardInfo) + + if (!(RD_HARPOON(ioport + hp_page_ctrl) & NARROW_SCSI_CARD)) + +- pCardInfo->si_flags |= SUPPORT_16TAR_32LUN; ++ pCardInfo->si_mflags |= SUPPORT_16TAR_32LUN; + + pCardInfo->si_card_family = HARPOON_FAMILY; + pCardInfo->si_bustype = BUSTYPE_PCI; +@@ -1140,15 +1140,15 @@ static int FlashPoint_ProbeHostAdapter(struct sccb_mgr_info *pCardInfo) + + if (pCardInfo->si_card_model[1] == '3') { + if (RD_HARPOON(ioport + hp_ee_ctrl) & BIT(7)) +- pCardInfo->si_flags |= LOW_BYTE_TERM; ++ pCardInfo->si_mflags |= LOW_BYTE_TERM; + } else if (pCardInfo->si_card_model[2] == '0') { + temp = RD_HARPOON(ioport + hp_xfer_pad); + WR_HARPOON(ioport + hp_xfer_pad, (temp & ~BIT(4))); + if (RD_HARPOON(ioport + hp_ee_ctrl) & BIT(7)) +- pCardInfo->si_flags |= LOW_BYTE_TERM; ++ pCardInfo->si_mflags |= LOW_BYTE_TERM; + WR_HARPOON(ioport + hp_xfer_pad, (temp | BIT(4))); + if (RD_HARPOON(ioport + hp_ee_ctrl) & BIT(7)) +- pCardInfo->si_flags |= HIGH_BYTE_TERM; ++ pCardInfo->si_mflags |= HIGH_BYTE_TERM; + WR_HARPOON(ioport + hp_xfer_pad, temp); + } else { + temp = RD_HARPOON(ioport + hp_ee_ctrl); +@@ -1166,9 +1166,9 @@ static int FlashPoint_ProbeHostAdapter(struct sccb_mgr_info *pCardInfo) + WR_HARPOON(ioport + hp_ee_ctrl, temp); + WR_HARPOON(ioport + hp_xfer_pad, temp2); + if (!(temp3 & BIT(7))) +- pCardInfo->si_flags |= LOW_BYTE_TERM; ++ pCardInfo->si_mflags |= LOW_BYTE_TERM; + if (!(temp3 & BIT(6))) +- pCardInfo->si_flags |= HIGH_BYTE_TERM; ++ pCardInfo->si_mflags |= HIGH_BYTE_TERM; + } + + ARAM_ACCESS(ioport); +@@ -1275,7 +1275,7 @@ static void *FlashPoint_HardwareResetHostAdapter(struct sccb_mgr_info + WR_HARPOON(ioport + hp_arb_id, pCardInfo->si_id); + CurrCard->ourId = pCardInfo->si_id; + +- i = (unsigned char)pCardInfo->si_flags; ++ i = (unsigned char)pCardInfo->si_mflags; + if (i & SCSI_PARITY_ENA) + WR_HARPOON(ioport + hp_portctrl_1, (HOST_MODE8 | CHK_SCSI_P)); + +@@ -1289,14 +1289,14 @@ static void *FlashPoint_HardwareResetHostAdapter(struct sccb_mgr_info + j |= SCSI_TERM_ENA_H; + WR_HARPOON(ioport + hp_ee_ctrl, j); + +- if (!(pCardInfo->si_flags & SOFT_RESET)) { ++ if (!(pCardInfo->si_mflags & SOFT_RESET)) { + + FPT_sresb(ioport, thisCard); + + FPT_scini(thisCard, pCardInfo->si_id, 0); + } + +- if (pCardInfo->si_flags & POST_ALL_UNDERRRUNS) ++ if (pCardInfo->si_mflags & POST_ALL_UNDERRRUNS) + CurrCard->globalFlags |= F_NO_FILTER; + + if (pCurrNvRam) { + diff --git a/patches.suse/scsi-be2iscsi-Fix-an-error-handling-path-in-beiscsi_dev_probe b/patches.suse/scsi-be2iscsi-Fix-an-error-handling-path-in-beiscsi_dev_probe new file mode 100644 index 0000000..c3d38b2 --- /dev/null +++ b/patches.suse/scsi-be2iscsi-Fix-an-error-handling-path-in-beiscsi_dev_probe @@ -0,0 +1,33 @@ +From: Christophe JAILLET +Date: Sat, 12 Jun 2021 09:18:34 +0200 +Subject: scsi: be2iscsi: Fix an error handling path in beiscsi_dev_probe() +Git-commit: 030e4138d11fced3b831c2761e4cecf347bae99c +Patch-mainline: v5.14-rc1 +References: git-fixes + +If an error occurs after a pci_enable_pcie_error_reporting() call, it must +be undone by a corresponding pci_disable_pcie_error_reporting() call, as +already done in the remove function. + +Link: https://lore.kernel.org/r/77adb02cfea7f1364e5603ecf3930d8597ae356e.1623482155.git.christophe.jaillet@wanadoo.fr +Fixes: 3567f36a09d1 ("[SCSI] be2iscsi: Fix AER handling in driver") +Signed-off-by: Christophe JAILLET +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/be2iscsi/be_main.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/scsi/be2iscsi/be_main.c b/drivers/scsi/be2iscsi/be_main.c +index 310b801c6c87..b89a7db477c7 100644 +--- a/drivers/scsi/be2iscsi/be_main.c ++++ b/drivers/scsi/be2iscsi/be_main.c +@@ -5743,6 +5743,7 @@ static int beiscsi_dev_probe(struct pci_dev *pcidev, + pci_disable_msix(phba->pcidev); + pci_dev_put(phba->pcidev); + iscsi_host_free(phba->shost); ++ pci_disable_pcie_error_reporting(pcidev); + pci_set_drvdata(pcidev, NULL); + disable_pci: + pci_release_regions(pcidev); + diff --git a/patches.suse/scsi-core-Fix-spelling-in-a-source-code-comment b/patches.suse/scsi-core-Fix-spelling-in-a-source-code-comment new file mode 100644 index 0000000..9d8f61a --- /dev/null +++ b/patches.suse/scsi-core-Fix-spelling-in-a-source-code-comment @@ -0,0 +1,34 @@ +From: Bart Van Assche +Date: Wed, 29 Sep 2021 11:23:18 -0700 +Subject: scsi: core: Fix spelling in a source code comment +Git-commit: e9076e7f23aa087f8b7257f3be9e9586f341e3b1 +Patch-mainline: v5.16-rc1 +References: git-fixes + +The typo in this source code comment makes the comment confusing. Clear up +the confusion by fixing the typo. + +Link: https://lore.kernel.org/r/20210929182318.2060489-1-bvanassche@acm.org +Fixes: bc85dc500f9d ("scsi: remove scsi_end_request") +Cc: Christoph Hellwig +Signed-off-by: Bart Van Assche +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/scsi_lib.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c +index dcf105287a76..5f5ad22512f5 100644 +--- a/drivers/scsi/scsi_lib.c ++++ b/drivers/scsi/scsi_lib.c +@@ -949,7 +949,7 @@ void scsi_io_completion(struct scsi_cmnd *cmd, unsigned int good_bytes) + + /* + * If there had been no error, but we have leftover bytes in the +- * requeues just queue the command up again. ++ * request just queue the command up again. + */ + if (likely(result == 0)) + scsi_io_completion_reprep(cmd, q); + diff --git a/patches.suse/scsi-csiostor-Add-module-softdep-on-cxgb4 b/patches.suse/scsi-csiostor-Add-module-softdep-on-cxgb4 new file mode 100644 index 0000000..749139c --- /dev/null +++ b/patches.suse/scsi-csiostor-Add-module-softdep-on-cxgb4 @@ -0,0 +1,40 @@ +From: Rahul Lakkireddy +Date: Mon, 27 Sep 2021 21:44:08 +0530 +Subject: scsi: csiostor: Add module softdep on cxgb4 +Git-commit: 79a7482249a7353bc86aff8127954d5febf02472 +Patch-mainline: v5.15-rc4 +References: git-fixes + +Both cxgb4 and csiostor drivers run on their own independent Physical +Function. But when cxgb4 and csiostor are both being loaded in parallel via +modprobe, there is a race when firmware upgrade is attempted by both the +drivers. + +When the cxgb4 driver initiates the firmware upgrade, it halts the firmware +and the chip until upgrade is complete. When the csiostor driver is coming +up in parallel, the firmware mailbox communication fails with timeouts and +the csiostor driver probe fails. + +Add a module soft dependency on cxgb4 driver to ensure loading csiostor +triggers cxgb4 to load first when available to avoid the firmware upgrade +race. + +Link: https://lore.kernel.org/r/1632759248-15382-1-git-send-email-rahul.lakkireddy@chelsio.com +Fixes: a3667aaed569 ("[SCSI] csiostor: Chelsio FCoE offload driver") +Signed-off-by: Rahul Lakkireddy +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/csiostor/csio_init.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/scsi/csiostor/csio_init.c b/drivers/scsi/csiostor/csio_init.c +index 390b07bf92b9..ccbded3353bd 100644 +--- a/drivers/scsi/csiostor/csio_init.c ++++ b/drivers/scsi/csiostor/csio_init.c +@@ -1254,3 +1254,4 @@ MODULE_DEVICE_TABLE(pci, csio_pci_tbl); + MODULE_VERSION(CSIO_DRV_VERSION); + MODULE_FIRMWARE(FW_FNAME_T5); + MODULE_FIRMWARE(FW_FNAME_T6); ++MODULE_SOFTDEP("pre: cxgb4"); + diff --git a/patches.suse/scsi-csiostor-Uninitialized-data-in-csio_ln_vnp_read_cbfn b/patches.suse/scsi-csiostor-Uninitialized-data-in-csio_ln_vnp_read_cbfn new file mode 100644 index 0000000..0e02493 --- /dev/null +++ b/patches.suse/scsi-csiostor-Uninitialized-data-in-csio_ln_vnp_read_cbfn @@ -0,0 +1,36 @@ +From: Dan Carpenter +Date: Wed, 6 Oct 2021 10:32:43 +0300 +Subject: scsi: csiostor: Uninitialized data in csio_ln_vnp_read_cbfn() +Git-commit: f4875d509a0a78ad294a1a538d534b5ba94e685a +Patch-mainline: v5.16-rc1 +References: git-fixes + +This variable is just a temporary variable, used to do an endian +conversion. The problem is that the last byte is not initialized. After +the conversion is completely done, the last byte is discarded so it doesn't +cause a problem. But static checkers and the KMSan runtime checker can +detect the uninitialized read and will complain about it. + +Link: https://lore.kernel.org/r/20211006073242.GA8404@kili +Fixes: 5036f0a0ecd3 ("[SCSI] csiostor: Fix sparse warnings.") +Signed-off-by: Dan Carpenter +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/csiostor/csio_lnode.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/scsi/csiostor/csio_lnode.c b/drivers/scsi/csiostor/csio_lnode.c +index dc98f51f466f..d5ac93897023 100644 +--- a/drivers/scsi/csiostor/csio_lnode.c ++++ b/drivers/scsi/csiostor/csio_lnode.c +@@ -619,7 +619,7 @@ csio_ln_vnp_read_cbfn(struct csio_hw *hw, struct csio_mb *mbp) + struct fc_els_csp *csp; + struct fc_els_cssp *clsp; + enum fw_retval retval; +- __be32 nport_id; ++ __be32 nport_id = 0; + + retval = FW_CMD_RETVAL_G(ntohl(rsp->alloc_to_len16)); + if (retval != FW_SUCCESS) { + diff --git a/patches.suse/scsi-dc395-Fix-error-case-unwinding b/patches.suse/scsi-dc395-Fix-error-case-unwinding new file mode 100644 index 0000000..3ddb301 --- /dev/null +++ b/patches.suse/scsi-dc395-Fix-error-case-unwinding @@ -0,0 +1,39 @@ +From: Tong Zhang +Date: Mon, 6 Sep 2021 21:07:02 -0700 +Subject: scsi: dc395: Fix error case unwinding +Git-commit: cbd9a3347c757383f3d2b50cf7cfd03eb479c481 +Patch-mainline: v5.16-rc1 +References: git-fixes + +dc395x_init_one()->adapter_init() might fail. In this case, the acb is +already cleaned up by adapter_init(), no need to do that in +adapter_uninit(acb) again. + +[ 1.252251] dc395x: adapter init failed +[ 1.254900] RIP: 0010:adapter_uninit+0x94/0x170 [dc395x] +[ 1.260307] Call Trace: +[ 1.260442] dc395x_init_one.cold+0x72a/0x9bb [dc395x] + +Link: https://lore.kernel.org/r/20210907040702.1846409-1-ztong0001@gmail.com +Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") +Reviewed-by: Finn Thain +Signed-off-by: Tong Zhang +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/dc395x.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/scsi/dc395x.c b/drivers/scsi/dc395x.c +index 24c7cefb0b78..1c79e6c27163 100644 +--- a/drivers/scsi/dc395x.c ++++ b/drivers/scsi/dc395x.c +@@ -4618,6 +4618,7 @@ static int dc395x_init_one(struct pci_dev *dev, const struct pci_device_id *id) + /* initialise the adapter and everything we need */ + if (adapter_init(acb, io_port_base, io_port_len, irq)) { + dprintkl(KERN_INFO, "adapter init failed\n"); ++ acb = NULL; + goto fail; + } + + diff --git a/patches.suse/scsi-fdomain-Fix-error-return-code-in-fdomain_probe b/patches.suse/scsi-fdomain-Fix-error-return-code-in-fdomain_probe new file mode 100644 index 0000000..28b7c0a --- /dev/null +++ b/patches.suse/scsi-fdomain-Fix-error-return-code-in-fdomain_probe @@ -0,0 +1,37 @@ +From: Wei Li +Date: Thu, 15 Jul 2021 11:26:25 +0800 +Subject: scsi: fdomain: Fix error return code in fdomain_probe() +Git-commit: 632c4ae6da1d629eddf9da1e692d7617c568c256 +Patch-mainline: v5.15-rc1 +References: git-fixes + +If request_region() fails the return value is not set. Return -EBUSY on +error. + +Link: https://lore.kernel.org/r/20210715032625.1395495-1-liwei391@huawei.com +Fixes: 8674a8aa2c39 ("scsi: fdomain: Add PCMCIA support") +Reported-by: Hulk Robot +Signed-off-by: Wei Li +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/pcmcia/fdomain_cs.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/scsi/pcmcia/fdomain_cs.c b/drivers/scsi/pcmcia/fdomain_cs.c +index e42acf314d06..33df6a9ba9b5 100644 +--- a/drivers/scsi/pcmcia/fdomain_cs.c ++++ b/drivers/scsi/pcmcia/fdomain_cs.c +@@ -45,8 +45,10 @@ static int fdomain_probe(struct pcmcia_device *link) + goto fail_disable; + + if (!request_region(link->resource[0]->start, FDOMAIN_REGION_SIZE, +- "fdomain_cs")) ++ "fdomain_cs")) { ++ ret = -EBUSY; + goto fail_disable; ++ } + + sh = fdomain_create(link->resource[0]->start, link->irq, 7, &link->dev); + if (!sh) { + diff --git a/patches.suse/scsi-iscsi-Fix-iface-sysfs-attr-detection b/patches.suse/scsi-iscsi-Fix-iface-sysfs-attr-detection new file mode 100644 index 0000000..0229113 --- /dev/null +++ b/patches.suse/scsi-iscsi-Fix-iface-sysfs-attr-detection @@ -0,0 +1,142 @@ +From: Mike Christie +Date: Wed, 30 Jun 2021 19:25:59 -0500 +Subject: scsi: iscsi: Fix iface sysfs attr detection +Git-commit: e746f3451ec7f91dcc9fd67a631239c715850a34 +Patch-mainline: v5.14-rc3 +References: git-fixes + +A ISCSI_IFACE_PARAM can have the same value as a ISCSI_NET_PARAM so when +iscsi_iface_attr_is_visible tries to figure out the type by just checking +the value, we can collide and return the wrong type. When we call into the +driver we might not match and return that we don't want attr visible in +sysfs. The patch fixes this by setting the type when we figure out what the +param is. + +Link: https://lore.kernel.org/r/20210701002559.89533-1-michael.christie@oracle.com +Fixes: 3e0f65b34cc9 ("[SCSI] iscsi_transport: Additional parameters for network settings") +Signed-off-by: Mike Christie +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/scsi_transport_iscsi.c | 90 ++++++++++++++----------------------- + 1 file changed, 34 insertions(+), 56 deletions(-) + +diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c +index b07105ae7c91..d8b05d8b5470 100644 +--- a/drivers/scsi/scsi_transport_iscsi.c ++++ b/drivers/scsi/scsi_transport_iscsi.c +@@ -439,39 +439,10 @@ static umode_t iscsi_iface_attr_is_visible(struct kobject *kobj, + struct device *dev = container_of(kobj, struct device, kobj); + struct iscsi_iface *iface = iscsi_dev_to_iface(dev); + struct iscsi_transport *t = iface->transport; +- int param; +- int param_type; ++ int param = -1; + + if (attr == &dev_attr_iface_enabled.attr) + param = ISCSI_NET_PARAM_IFACE_ENABLE; +- else if (attr == &dev_attr_iface_vlan_id.attr) +- param = ISCSI_NET_PARAM_VLAN_ID; +- else if (attr == &dev_attr_iface_vlan_priority.attr) +- param = ISCSI_NET_PARAM_VLAN_PRIORITY; +- else if (attr == &dev_attr_iface_vlan_enabled.attr) +- param = ISCSI_NET_PARAM_VLAN_ENABLED; +- else if (attr == &dev_attr_iface_mtu.attr) +- param = ISCSI_NET_PARAM_MTU; +- else if (attr == &dev_attr_iface_port.attr) +- param = ISCSI_NET_PARAM_PORT; +- else if (attr == &dev_attr_iface_ipaddress_state.attr) +- param = ISCSI_NET_PARAM_IPADDR_STATE; +- else if (attr == &dev_attr_iface_delayed_ack_en.attr) +- param = ISCSI_NET_PARAM_DELAYED_ACK_EN; +- else if (attr == &dev_attr_iface_tcp_nagle_disable.attr) +- param = ISCSI_NET_PARAM_TCP_NAGLE_DISABLE; +- else if (attr == &dev_attr_iface_tcp_wsf_disable.attr) +- param = ISCSI_NET_PARAM_TCP_WSF_DISABLE; +- else if (attr == &dev_attr_iface_tcp_wsf.attr) +- param = ISCSI_NET_PARAM_TCP_WSF; +- else if (attr == &dev_attr_iface_tcp_timer_scale.attr) +- param = ISCSI_NET_PARAM_TCP_TIMER_SCALE; +- else if (attr == &dev_attr_iface_tcp_timestamp_en.attr) +- param = ISCSI_NET_PARAM_TCP_TIMESTAMP_EN; +- else if (attr == &dev_attr_iface_cache_id.attr) +- param = ISCSI_NET_PARAM_CACHE_ID; +- else if (attr == &dev_attr_iface_redirect_en.attr) +- param = ISCSI_NET_PARAM_REDIRECT_EN; + else if (attr == &dev_attr_iface_def_taskmgmt_tmo.attr) + param = ISCSI_IFACE_PARAM_DEF_TASKMGMT_TMO; + else if (attr == &dev_attr_iface_header_digest.attr) +@@ -508,6 +479,38 @@ static umode_t iscsi_iface_attr_is_visible(struct kobject *kobj, + param = ISCSI_IFACE_PARAM_STRICT_LOGIN_COMP_EN; + else if (attr == &dev_attr_iface_initiator_name.attr) + param = ISCSI_IFACE_PARAM_INITIATOR_NAME; ++ ++ if (param != -1) ++ return t->attr_is_visible(ISCSI_IFACE_PARAM, param); ++ ++ if (attr == &dev_attr_iface_vlan_id.attr) ++ param = ISCSI_NET_PARAM_VLAN_ID; ++ else if (attr == &dev_attr_iface_vlan_priority.attr) ++ param = ISCSI_NET_PARAM_VLAN_PRIORITY; ++ else if (attr == &dev_attr_iface_vlan_enabled.attr) ++ param = ISCSI_NET_PARAM_VLAN_ENABLED; ++ else if (attr == &dev_attr_iface_mtu.attr) ++ param = ISCSI_NET_PARAM_MTU; ++ else if (attr == &dev_attr_iface_port.attr) ++ param = ISCSI_NET_PARAM_PORT; ++ else if (attr == &dev_attr_iface_ipaddress_state.attr) ++ param = ISCSI_NET_PARAM_IPADDR_STATE; ++ else if (attr == &dev_attr_iface_delayed_ack_en.attr) ++ param = ISCSI_NET_PARAM_DELAYED_ACK_EN; ++ else if (attr == &dev_attr_iface_tcp_nagle_disable.attr) ++ param = ISCSI_NET_PARAM_TCP_NAGLE_DISABLE; ++ else if (attr == &dev_attr_iface_tcp_wsf_disable.attr) ++ param = ISCSI_NET_PARAM_TCP_WSF_DISABLE; ++ else if (attr == &dev_attr_iface_tcp_wsf.attr) ++ param = ISCSI_NET_PARAM_TCP_WSF; ++ else if (attr == &dev_attr_iface_tcp_timer_scale.attr) ++ param = ISCSI_NET_PARAM_TCP_TIMER_SCALE; ++ else if (attr == &dev_attr_iface_tcp_timestamp_en.attr) ++ param = ISCSI_NET_PARAM_TCP_TIMESTAMP_EN; ++ else if (attr == &dev_attr_iface_cache_id.attr) ++ param = ISCSI_NET_PARAM_CACHE_ID; ++ else if (attr == &dev_attr_iface_redirect_en.attr) ++ param = ISCSI_NET_PARAM_REDIRECT_EN; + else if (iface->iface_type == ISCSI_IFACE_TYPE_IPV4) { + if (attr == &dev_attr_ipv4_iface_ipaddress.attr) + param = ISCSI_NET_PARAM_IPV4_ADDR; +@@ -598,32 +601,7 @@ static umode_t iscsi_iface_attr_is_visible(struct kobject *kobj, + return 0; + } + +- switch (param) { +- case ISCSI_IFACE_PARAM_DEF_TASKMGMT_TMO: +- case ISCSI_IFACE_PARAM_HDRDGST_EN: +- case ISCSI_IFACE_PARAM_DATADGST_EN: +- case ISCSI_IFACE_PARAM_IMM_DATA_EN: +- case ISCSI_IFACE_PARAM_INITIAL_R2T_EN: +- case ISCSI_IFACE_PARAM_DATASEQ_INORDER_EN: +- case ISCSI_IFACE_PARAM_PDU_INORDER_EN: +- case ISCSI_IFACE_PARAM_ERL: +- case ISCSI_IFACE_PARAM_MAX_RECV_DLENGTH: +- case ISCSI_IFACE_PARAM_FIRST_BURST: +- case ISCSI_IFACE_PARAM_MAX_R2T: +- case ISCSI_IFACE_PARAM_MAX_BURST: +- case ISCSI_IFACE_PARAM_CHAP_AUTH_EN: +- case ISCSI_IFACE_PARAM_BIDI_CHAP_EN: +- case ISCSI_IFACE_PARAM_DISCOVERY_AUTH_OPTIONAL: +- case ISCSI_IFACE_PARAM_DISCOVERY_LOGOUT_EN: +- case ISCSI_IFACE_PARAM_STRICT_LOGIN_COMP_EN: +- case ISCSI_IFACE_PARAM_INITIATOR_NAME: +- param_type = ISCSI_IFACE_PARAM; +- break; +- default: +- param_type = ISCSI_NET_PARAM; +- } +- +- return t->attr_is_visible(param_type, param); ++ return t->attr_is_visible(ISCSI_NET_PARAM, param); + } + + static struct attribute *iscsi_iface_attrs[] = { + diff --git a/patches.suse/scsi-libsas-Use-_safe-loop-in-sas_resume_port b/patches.suse/scsi-libsas-Use-_safe-loop-in-sas_resume_port new file mode 100644 index 0000000..2704f5e --- /dev/null +++ b/patches.suse/scsi-libsas-Use-_safe-loop-in-sas_resume_port @@ -0,0 +1,47 @@ +From: Dan Carpenter +Date: Wed, 19 May 2021 17:20:27 +0300 +Subject: scsi: libsas: Use _safe() loop in sas_resume_port() +Git-commit: 8c7e7b8486cda21269d393245883c5e4737d5ee7 +Patch-mainline: v5.13-rc4 +References: git-fixes + +If sas_notify_lldd_dev_found() fails then this code calls: + + sas_unregister_dev(port, dev); + +which removes "dev", our list iterator, from the list. This could lead to +an endless loop. We need to use list_for_each_entry_safe(). + +Link: https://lore.kernel.org/r/YKUeq6gwfGcvvhty@mwanda +Fixes: 303694eeee5e ("[SCSI] libsas: suspend / resume support") +Reviewed-by: John Garry +Signed-off-by: Dan Carpenter +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/libsas/sas_port.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/scsi/libsas/sas_port.c b/drivers/scsi/libsas/sas_port.c +index 19cf418928fa..e3d03d744713 100644 +--- a/drivers/scsi/libsas/sas_port.c ++++ b/drivers/scsi/libsas/sas_port.c +@@ -25,7 +25,7 @@ static bool phy_is_wideport_member(struct asd_sas_port *port, struct asd_sas_phy + + static void sas_resume_port(struct asd_sas_phy *phy) + { +- struct domain_device *dev; ++ struct domain_device *dev, *n; + struct asd_sas_port *port = phy->port; + struct sas_ha_struct *sas_ha = phy->ha; + struct sas_internal *si = to_sas_internal(sas_ha->core.shost->transportt); +@@ -44,7 +44,7 @@ static void sas_resume_port(struct asd_sas_phy *phy) + * 1/ presume every device came back + * 2/ force the next revalidation to check all expander phys + */ +- list_for_each_entry(dev, &port->dev_list, dev_list_node) { ++ list_for_each_entry_safe(dev, n, &port->dev_list, dev_list_node) { + int i, rc; + + rc = sas_notify_lldd_dev_found(dev); + diff --git a/patches.suse/scsi-mpt3sas-Fix-error-return-value-in-_scsih_expander_add b/patches.suse/scsi-mpt3sas-Fix-error-return-value-in-_scsih_expander_add new file mode 100644 index 0000000..f33f8f7 --- /dev/null +++ b/patches.suse/scsi-mpt3sas-Fix-error-return-value-in-_scsih_expander_add @@ -0,0 +1,39 @@ +From: Zhen Lei +Date: Fri, 14 May 2021 16:13:00 +0800 +Subject: scsi: mpt3sas: Fix error return value in _scsih_expander_add() +Git-commit: d6c2ce435ffe23ef7f395ae76ec747414589db46 +Patch-mainline: v5.14-rc1 +References: git-fixes + +When an expander does not contain any 'phys', an appropriate error code -1 +should be returned, as done elsewhere in this function. However, we +currently do not explicitly assign this error code to 'rc'. As a result, 0 +was incorrectly returned. + +Link: https://lore.kernel.org/r/20210514081300.6650-1-thunder.leizhen@huawei.com +Fixes: f92363d12359 ("[SCSI] mpt3sas: add new driver supporting 12GB SAS") +Reported-by: Hulk Robot +Signed-off-by: Zhen Lei +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/mpt3sas/mpt3sas_scsih.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/scsi/mpt3sas/mpt3sas_scsih.c b/drivers/scsi/mpt3sas/mpt3sas_scsih.c +index dc2aaaf645d3..866d118f7931 100644 +--- a/drivers/scsi/mpt3sas/mpt3sas_scsih.c ++++ b/drivers/scsi/mpt3sas/mpt3sas_scsih.c +@@ -6920,8 +6920,10 @@ _scsih_expander_add(struct MPT3SAS_ADAPTER *ioc, u16 handle) + handle, parent_handle, + (u64)sas_expander->sas_address, sas_expander->num_phys); + +- if (!sas_expander->num_phys) ++ if (!sas_expander->num_phys) { ++ rc = -1; + goto out_fail; ++ } + sas_expander->phy = kcalloc(sas_expander->num_phys, + sizeof(struct _sas_phy), GFP_KERNEL); + if (!sas_expander->phy) { + diff --git a/patches.suse/scsi-qedf-Add-pointer-checks-in-qedf_update_link_speed b/patches.suse/scsi-qedf-Add-pointer-checks-in-qedf_update_link_speed new file mode 100644 index 0000000..e7206fa --- /dev/null +++ b/patches.suse/scsi-qedf-Add-pointer-checks-in-qedf_update_link_speed @@ -0,0 +1,58 @@ +From: Javed Hasan +Date: Wed, 12 May 2021 00:25:33 -0700 +Subject: scsi: qedf: Add pointer checks in qedf_update_link_speed() +Git-commit: 73578af92a0fae6609b955fcc9113e50e413c80f +Patch-mainline: v5.13-rc3 +References: git-fixes + +The following trace was observed: + + [ 14.042059] Call Trace: + [ 14.042061] + [ 14.042068] qedf_link_update+0x144/0x1f0 [qedf] + [ 14.042117] qed_link_update+0x5c/0x80 [qed] + [ 14.042135] qed_mcp_handle_link_change+0x2d2/0x410 [qed] + [ 14.042155] ? qed_set_ptt+0x70/0x80 [qed] + [ 14.042170] ? qed_set_ptt+0x70/0x80 [qed] + [ 14.042186] ? qed_rd+0x13/0x40 [qed] + [ 14.042205] qed_mcp_handle_events+0x437/0x690 [qed] + [ 14.042221] ? qed_set_ptt+0x70/0x80 [qed] + [ 14.042239] qed_int_sp_dpc+0x3a6/0x3e0 [qed] + [ 14.042245] tasklet_action_common.isra.14+0x5a/0x100 + [ 14.042250] __do_softirq+0xe4/0x2f8 + [ 14.042253] irq_exit+0xf7/0x100 + [ 14.042255] do_IRQ+0x7f/0xd0 + [ 14.042257] common_interrupt+0xf/0xf + [ 14.042259] + +API qedf_link_update() is getting called from QED but by that time +shost_data is not initialised. This results in a NULL pointer dereference +when we try to dereference shost_data while updating supported_speeds. + +Add a NULL pointer check before dereferencing shost_data. + +[lduncan: refreshed to apply] + +Link: https://lore.kernel.org/r/20210512072533.23618-1-jhasan@marvell.com +Fixes: 61d8658b4a43 ("scsi: qedf: Add QLogic FastLinQ offload FCoE driver framework.") +Reviewed-by: Himanshu Madhani +Signed-off-by: Javed Hasan +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/qedf/qedf_main.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/scsi/qedf/qedf_main.c ++++ b/drivers/scsi/qedf/qedf_main.c +@@ -530,7 +530,9 @@ static void qedf_update_link_speed(struc + if (linkmode_intersects(link->supported_caps, sup_caps)) + lport->link_supported_speeds |= FC_PORTSPEED_20GBIT; + +- fc_host_supported_speeds(lport->host) = lport->link_supported_speeds; ++ if (lport->host && lport->host->shost_data) ++ fc_host_supported_speeds(lport->host) = ++ lport->link_supported_speeds; + } + + static void qedf_bw_update(void *dev) diff --git a/patches.suse/scsi-qedf-Fix-error-codes-in-qedf_alloc_global_queues b/patches.suse/scsi-qedf-Fix-error-codes-in-qedf_alloc_global_queues new file mode 100644 index 0000000..addbfb1 --- /dev/null +++ b/patches.suse/scsi-qedf-Fix-error-codes-in-qedf_alloc_global_queues @@ -0,0 +1,73 @@ +From: Dan Carpenter +Date: Tue, 10 Aug 2021 11:51:49 +0300 +Subject: scsi: qedf: Fix error codes in qedf_alloc_global_queues() +Git-commit: ccc89737aa6b9f248cf1623014038beb6c2b7f56 +Patch-mainline: v5.15-rc1 +References: git-fixes + +This driver has some left over "return 1" on failure style code mixed with +"return negative error codes" style code. The caller doesn't care so we +should just convert everything to return negative error codes. + +Then there was a problem that there were two variables used to store error +codes which just resulted in confusion. If qedf_alloc_bdq() returned a +negative error code, we accidentally returned success instead of +propagating the error code. So get rid of the "rc" variable and use +"status" every where. + +Also remove the "status = 0" initialization so that these sorts of bugs +will be detected by the compiler in the future. + +Link: https://lore.kernel.org/r/20210810085023.GA23998@kili +Fixes: 61d8658b4a43 ("scsi: qedf: Add QLogic FastLinQ offload FCoE driver framework.") +Acked-by: Manish Rangankar +Signed-off-by: Dan Carpenter +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/qedf/qedf_main.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/scsi/qedf/qedf_main.c b/drivers/scsi/qedf/qedf_main.c +index 85f41abcb56c..42d0d941dba5 100644 +--- a/drivers/scsi/qedf/qedf_main.c ++++ b/drivers/scsi/qedf/qedf_main.c +@@ -3004,7 +3004,7 @@ static int qedf_alloc_global_queues(struct qedf_ctx *qedf) + { + u32 *list; + int i; +- int status = 0, rc; ++ int status; + u32 *pbl; + dma_addr_t page; + int num_pages; +@@ -3016,7 +3016,7 @@ static int qedf_alloc_global_queues(struct qedf_ctx *qedf) + */ + if (!qedf->num_queues) { + QEDF_ERR(&(qedf->dbg_ctx), "No MSI-X vectors available!\n"); +- return 1; ++ return -ENOMEM; + } + + /* +@@ -3024,7 +3024,7 @@ static int qedf_alloc_global_queues(struct qedf_ctx *qedf) + * addresses of our queues + */ + if (!qedf->p_cpuq) { +- status = 1; ++ status = -EINVAL; + QEDF_ERR(&qedf->dbg_ctx, "p_cpuq is NULL.\n"); + goto mem_alloc_failure; + } +@@ -3040,8 +3040,8 @@ static int qedf_alloc_global_queues(struct qedf_ctx *qedf) + "qedf->global_queues=%p.\n", qedf->global_queues); + + /* Allocate DMA coherent buffers for BDQ */ +- rc = qedf_alloc_bdq(qedf); +- if (rc) { ++ status = qedf_alloc_bdq(qedf); ++ if (status) { + QEDF_ERR(&qedf->dbg_ctx, "Unable to allocate bdq.\n"); + goto mem_alloc_failure; + } + diff --git a/patches.suse/scsi-qedi-Fix-error-codes-in-qedi_alloc_global_queues b/patches.suse/scsi-qedi-Fix-error-codes-in-qedi_alloc_global_queues new file mode 100644 index 0000000..1802cf6 --- /dev/null +++ b/patches.suse/scsi-qedi-Fix-error-codes-in-qedi_alloc_global_queues @@ -0,0 +1,78 @@ +From: Dan Carpenter +Date: Tue, 10 Aug 2021 11:47:53 +0300 +Subject: scsi: qedi: Fix error codes in qedi_alloc_global_queues() +Git-commit: 4dbe57d46d54a847875fa33e7d05877bb341585e +Patch-mainline: v5.15-rc1 +References: git-fixes + +This function had some left over code that returned 1 on error instead +negative error codes. Convert everything to use negative error codes. The +caller treats all non-zero returns the same so this does not affect run +time. + +A couple places set "rc" instead of "status" so those error paths ended up +returning success by mistake. Get rid of the "rc" variable and use +"status" everywhere. + +Remove the bogus "status = 0" initialization, as a future proofing measure +so the compiler will warn about uninitialized error codes. + +Link: https://lore.kernel.org/r/20210810084753.GD23810@kili +Fixes: ace7f46ba5fd ("scsi: qedi: Add QLogic FastLinQ offload iSCSI driver framework.") +Acked-by: Manish Rangankar +Signed-off-by: Dan Carpenter +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/qedi/qedi_main.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/scsi/qedi/qedi_main.c b/drivers/scsi/qedi/qedi_main.c +index 0b0acb827071..e6dc0b495a82 100644 +--- a/drivers/scsi/qedi/qedi_main.c ++++ b/drivers/scsi/qedi/qedi_main.c +@@ -1621,7 +1621,7 @@ static int qedi_alloc_global_queues(struct qedi_ctx *qedi) + { + u32 *list; + int i; +- int status = 0, rc; ++ int status; + u32 *pbl; + dma_addr_t page; + int num_pages; +@@ -1632,14 +1632,14 @@ static int qedi_alloc_global_queues(struct qedi_ctx *qedi) + */ + if (!qedi->num_queues) { + QEDI_ERR(&qedi->dbg_ctx, "No MSI-X vectors available!\n"); +- return 1; ++ return -ENOMEM; + } + + /* Make sure we allocated the PBL that will contain the physical + * addresses of our queues + */ + if (!qedi->p_cpuq) { +- status = 1; ++ status = -EINVAL; + goto mem_alloc_failure; + } + +@@ -1654,13 +1654,13 @@ static int qedi_alloc_global_queues(struct qedi_ctx *qedi) + "qedi->global_queues=%p.\n", qedi->global_queues); + + /* Allocate DMA coherent buffers for BDQ */ +- rc = qedi_alloc_bdq(qedi); +- if (rc) ++ status = qedi_alloc_bdq(qedi); ++ if (status) + goto mem_alloc_failure; + + /* Allocate DMA coherent buffers for NVM_ISCSI_CFG */ +- rc = qedi_alloc_nvm_iscsi_cfg(qedi); +- if (rc) ++ status = qedi_alloc_nvm_iscsi_cfg(qedi); ++ if (status) + goto mem_alloc_failure; + + /* Allocate a CQ and an associated PBL for each MSI-X + diff --git a/patches.suse/scsi-qla2xxx-Fix-a-memory-leak-in-an-error-path-of-qla2x00_process_els b/patches.suse/scsi-qla2xxx-Fix-a-memory-leak-in-an-error-path-of-qla2x00_process_els new file mode 100644 index 0000000..4fcbf8f --- /dev/null +++ b/patches.suse/scsi-qla2xxx-Fix-a-memory-leak-in-an-error-path-of-qla2x00_process_els @@ -0,0 +1,50 @@ +From: Joy Gu +Date: Tue, 12 Oct 2021 12:18:33 -0700 +Subject: scsi: qla2xxx: Fix a memory leak in an error path of + qla2x00_process_els() +Git-commit: 7fb223d0ad801f633c78cbe42b1d1b55f5d163ad +Patch-mainline: v5.15-rc7 +References: git-fixes + +Commit 8c0eb596baa5 ("[SCSI] qla2xxx: Fix a memory leak in an error path of +qla2x00_process_els()"), intended to change: + + bsg_job->request->msgcode == FC_BSG_HST_ELS_NOLOGIN + +to: + + bsg_job->request->msgcode != FC_BSG_RPT_ELS + +but changed it to: + + bsg_job->request->msgcode == FC_BSG_RPT_ELS + +instead. + +Change the == to a != to avoid leaking the fcport structure or freeing +unallocated memory. + +Link: https://lore.kernel.org/r/20211012191834.90306-2-jgu@purestorage.com +Fixes: 8c0eb596baa5 ("[SCSI] qla2xxx: Fix a memory leak in an error path of qla2x00_process_els()") +Reviewed-by: Bart Van Assche +Signed-off-by: Joy Gu +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/qla2xxx/qla_bsg.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/scsi/qla2xxx/qla_bsg.c b/drivers/scsi/qla2xxx/qla_bsg.c +index 4b5d28d89d69..655cf5de604b 100644 +--- a/drivers/scsi/qla2xxx/qla_bsg.c ++++ b/drivers/scsi/qla2xxx/qla_bsg.c +@@ -431,7 +431,7 @@ qla2x00_process_els(struct bsg_job *bsg_job) + goto done_free_fcport; + + done_free_fcport: +- if (bsg_request->msgcode == FC_BSG_RPT_ELS) ++ if (bsg_request->msgcode != FC_BSG_RPT_ELS) + qla2x00_free_fcport(fcport); + done: + return rval; + diff --git a/patches.suse/scsi-qla2xxx-Make-sure-that-aborted-commands-are-freed b/patches.suse/scsi-qla2xxx-Make-sure-that-aborted-commands-are-freed new file mode 100644 index 0000000..90961de --- /dev/null +++ b/patches.suse/scsi-qla2xxx-Make-sure-that-aborted-commands-are-freed @@ -0,0 +1,109 @@ +From: Bart Van Assche +Date: Thu, 8 Aug 2019 20:02:10 -0700 +Subject: scsi: qla2xxx: Make sure that aborted commands are freed +Git-commit: 0dcec41acb85da33841c2ab56dbf337ed00a3914 +Patch-mainline: v5.4-rc1 +References: git-fixes + +The LIO core requires that the target driver callback functions +.queue_data_in() and .queue_status() call target_put_sess_cmd() or +transport_generic_free_cmd(). These calls may happen synchronously or +asynchronously. Make sure that one of these LIO functions is called in case +a command has been aborted. This patch avoids that the code for removing a +session hangs due to commands that do not make progress. + +Cc: Himanshu Madhani +Fixes: 694833ee00c4 ("scsi: tcm_qla2xxx: Do not allow aborted cmd to advance.") # v4.13. +Fixes: a07100e00ac4 ("qla2xxx: Fix TMR ABORT interaction issue between qla2xxx and TCM") # v4.5. +Signed-off-by: Bart Van Assche +Tested-by: Himanshu Madhani +Reviewed-by: Himanshu Madhani +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/qla2xxx/qla_target.c | 13 ++++++++----- + drivers/scsi/qla2xxx/tcm_qla2xxx.c | 4 ++++ + 2 files changed, 12 insertions(+), 5 deletions(-) + +diff --git a/drivers/scsi/qla2xxx/qla_target.c b/drivers/scsi/qla2xxx/qla_target.c +index cc0c99b5f3fb..0ffda6171614 100644 +--- a/drivers/scsi/qla2xxx/qla_target.c ++++ b/drivers/scsi/qla2xxx/qla_target.c +@@ -3206,7 +3206,8 @@ int qlt_xmit_response(struct qla_tgt_cmd *cmd, int xmit_type, + if (!qpair->fw_started || (cmd->reset_count != qpair->chip_reset) || + (cmd->sess && cmd->sess->deleted)) { + cmd->state = QLA_TGT_STATE_PROCESSED; +- return 0; ++ res = 0; ++ goto free; + } + + ql_dbg_qp(ql_dbg_tgt, qpair, 0xe018, +@@ -3217,9 +3218,8 @@ int qlt_xmit_response(struct qla_tgt_cmd *cmd, int xmit_type, + + res = qlt_pre_xmit_response(cmd, &prm, xmit_type, scsi_status, + &full_req_cnt); +- if (unlikely(res != 0)) { +- return res; +- } ++ if (unlikely(res != 0)) ++ goto free; + + spin_lock_irqsave(qpair->qp_lock_ptr, flags); + +@@ -3239,7 +3239,8 @@ int qlt_xmit_response(struct qla_tgt_cmd *cmd, int xmit_type, + vha->flags.online, qla2x00_reset_active(vha), + cmd->reset_count, qpair->chip_reset); + spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); +- return 0; ++ res = 0; ++ goto free; + } + + /* Does F/W have an IOCBs for this request */ +@@ -3342,6 +3343,8 @@ int qlt_xmit_response(struct qla_tgt_cmd *cmd, int xmit_type, + qlt_unmap_sg(vha, cmd); + spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); + ++free: ++ vha->hw->tgt.tgt_ops->free_cmd(cmd); + return res; + } + EXPORT_SYMBOL(qlt_xmit_response); +diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.c b/drivers/scsi/qla2xxx/tcm_qla2xxx.c +index 963c220f8ba8..042a24314edc 100644 +--- a/drivers/scsi/qla2xxx/tcm_qla2xxx.c ++++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.c +@@ -620,6 +620,7 @@ static int tcm_qla2xxx_queue_data_in(struct se_cmd *se_cmd) + { + struct qla_tgt_cmd *cmd = container_of(se_cmd, + struct qla_tgt_cmd, se_cmd); ++ struct scsi_qla_host *vha = cmd->vha; + + if (cmd->aborted) { + /* Cmd can loop during Q-full. tcm_qla2xxx_aborted_task +@@ -632,6 +633,7 @@ static int tcm_qla2xxx_queue_data_in(struct se_cmd *se_cmd) + cmd->se_cmd.transport_state, + cmd->se_cmd.t_state, + cmd->se_cmd.se_cmd_flags); ++ vha->hw->tgt.tgt_ops->free_cmd(cmd); + return 0; + } + +@@ -659,6 +661,7 @@ static int tcm_qla2xxx_queue_status(struct se_cmd *se_cmd) + { + struct qla_tgt_cmd *cmd = container_of(se_cmd, + struct qla_tgt_cmd, se_cmd); ++ struct scsi_qla_host *vha = cmd->vha; + int xmit_type = QLA_TGT_XMIT_STATUS; + + if (cmd->aborted) { +@@ -672,6 +675,7 @@ static int tcm_qla2xxx_queue_status(struct se_cmd *se_cmd) + cmd, kref_read(&cmd->se_cmd.cmd_kref), + cmd->se_cmd.transport_state, cmd->se_cmd.t_state, + cmd->se_cmd.se_cmd_flags); ++ vha->hw->tgt.tgt_ops->free_cmd(cmd); + return 0; + } + cmd->bufflen = se_cmd->data_length; + diff --git a/patches.suse/scsi-smartpqi-Fix-an-error-code-in-pqi_get_raid_map b/patches.suse/scsi-smartpqi-Fix-an-error-code-in-pqi_get_raid_map new file mode 100644 index 0000000..9939330 --- /dev/null +++ b/patches.suse/scsi-smartpqi-Fix-an-error-code-in-pqi_get_raid_map @@ -0,0 +1,30 @@ +From: Dan Carpenter +Date: Tue, 10 Aug 2021 11:46:13 +0300 +Subject: scsi: smartpqi: Fix an error code in pqi_get_raid_map() +Git-commit: d1f6581a6796c4e9fd8a4a24e8b77463d18f0df1 +Patch-mainline: v5.15-rc1 +References: git-fixes + +Return -EINVAL on failure instead of success. + +[lduncan: refreshed to apply] + +Link: https://lore.kernel.org/r/20210810084613.GB23810@kili +Fixes: a91aaae0243b ("scsi: smartpqi: allow for larger raid maps") +Signed-off-by: Dan Carpenter +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/smartpqi/smartpqi_init.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/scsi/smartpqi/smartpqi_init.c ++++ b/drivers/scsi/smartpqi/smartpqi_init.c +@@ -1323,6 +1323,7 @@ static int pqi_get_raid_map(struct pqi_c + "requested %u bytes, received %u bytes\n", + raid_map_size, + get_unaligned_le32(&raid_map->structure_size)); ++ rc = -EINVAL; + goto error; + } + } diff --git a/patches.suse/scsi-snic-Fix-an-error-message b/patches.suse/scsi-snic-Fix-an-error-message new file mode 100644 index 0000000..3e3e193 --- /dev/null +++ b/patches.suse/scsi-snic-Fix-an-error-message @@ -0,0 +1,39 @@ +From: Christophe JAILLET +Date: Thu, 6 May 2021 20:38:20 +0200 +Subject: scsi: snic: Fix an error message +Git-commit: 9959d45166faaa75d9d4bf2ad8b945dfbe9888f8 +Patch-mainline: v5.14-rc1 +References: git-fixes + +'ret' is known to be 0 here. No error code is available so just remove +'ret' from the error message. + +While at it, change the word "Queuing" into "Init" which looks more +appropriate. + +Link: https://lore.kernel.org/r/3b9d5d767e09d03a07bede293a6ba32e3735cd1a.1620326191.git.christophe.jaillet@wanadoo.fr +Fixes: c8806b6c9e82 ("snic: driver for Cisco SCSI HBA") +Signed-off-by: Christophe JAILLET +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/snic/snic_ctl.c | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/drivers/scsi/snic/snic_ctl.c b/drivers/scsi/snic/snic_ctl.c +index 4cd86115cfb2..703f229862fc 100644 +--- a/drivers/scsi/snic/snic_ctl.c ++++ b/drivers/scsi/snic/snic_ctl.c +@@ -114,10 +114,7 @@ snic_queue_exch_ver_req(struct snic *snic) + + rqi = snic_req_init(snic, 0); + if (!rqi) { +- SNIC_HOST_ERR(snic->shost, +- "Queuing Exch Ver Req failed, err = %d\n", +- ret); +- ++ SNIC_HOST_ERR(snic->shost, "Init Exch Ver Req failed\n"); + ret = -ENOMEM; + goto error; + } + diff --git a/patches.suse/scsi-ufs-pci-Add-quirk-for-broken-auto-hibernate-for-Intel-EHL b/patches.suse/scsi-ufs-pci-Add-quirk-for-broken-auto-hibernate-for-Intel-EHL new file mode 100644 index 0000000..9ad270f --- /dev/null +++ b/patches.suse/scsi-ufs-pci-Add-quirk-for-broken-auto-hibernate-for-Intel-EHL @@ -0,0 +1,86 @@ +From: Adrian Hunter +Date: Mon, 10 Aug 2020 17:10:24 +0300 +Subject: scsi: ufs-pci: Add quirk for broken auto-hibernate for Intel EHL +Git-commit: 8da76f71fef7d8a1a72af09d48899573feb60065 +Patch-mainline: v5.9-rc2 +References: git-fixes + +Intel EHL UFS host controller advertises auto-hibernate capability but it +does not work correctly. Add a quirk for that. + +[mkp: checkpatch fix] +[lduncan: refreshed to apply] + +Link: https://lore.kernel.org/r/20200810141024.28859-1-adrian.hunter@intel.com +Fixes: 8c09d7527697 ("scsi: ufshdc-pci: Add Intel PCI IDs for EHL") +Acked-by: Stanley Chu +Signed-off-by: Adrian Hunter +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/ufs/ufshcd-pci.c | 16 ++++++++++++++-- + drivers/scsi/ufs/ufshcd.h | 9 ++++++++- + 2 files changed, 22 insertions(+), 3 deletions(-) + +--- a/drivers/scsi/ufs/ufshcd-pci.c ++++ b/drivers/scsi/ufs/ufshcd-pci.c +@@ -67,11 +67,23 @@ static int ufs_intel_link_startup_notify + return err; + } + ++static int ufs_intel_ehl_init(struct ufs_hba *hba) ++{ ++ hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8; ++ return 0; ++} ++ + static struct ufs_hba_variant_ops ufs_intel_cnl_hba_vops = { + .name = "intel-pci", + .link_startup_notify = ufs_intel_link_startup_notify, + }; + ++static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops = { ++ .name = "intel-pci", ++ .init = ufs_intel_ehl_init, ++ .link_startup_notify = ufs_intel_link_startup_notify, ++}; ++ + #ifdef CONFIG_PM_SLEEP + /** + * ufshcd_pci_suspend - suspend power management function +@@ -200,8 +212,8 @@ static const struct dev_pm_ops ufshcd_pc + static const struct pci_device_id ufshcd_pci_tbl[] = { + { PCI_VENDOR_ID_SAMSUNG, 0xC00C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, + { PCI_VDEVICE(INTEL, 0x9DFA), (kernel_ulong_t)&ufs_intel_cnl_hba_vops }, +- { PCI_VDEVICE(INTEL, 0x4B41), (kernel_ulong_t)&ufs_intel_cnl_hba_vops }, +- { PCI_VDEVICE(INTEL, 0x4B43), (kernel_ulong_t)&ufs_intel_cnl_hba_vops }, ++ { PCI_VDEVICE(INTEL, 0x4B41), (kernel_ulong_t)&ufs_intel_ehl_hba_vops }, ++ { PCI_VDEVICE(INTEL, 0x4B43), (kernel_ulong_t)&ufs_intel_ehl_hba_vops }, + { } /* terminate list */ + }; + +--- a/drivers/scsi/ufs/ufshcd.h ++++ b/drivers/scsi/ufs/ufshcd.h +@@ -541,6 +541,12 @@ enum ufshcd_quirks { + * OCS FATAL ERROR with device error through sense data + */ + UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, ++ ++ /* ++ * This quirk needs to be enabled if the host controller has ++ * auto-hibernate capability but it doesn't work. ++ */ ++ UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, + }; + + /** +@@ -776,7 +782,8 @@ return true; + + static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) + { +- return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT); ++ return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && ++ !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); + } + + static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) diff --git a/patches.suse/scsi-ufs-ufshcd-pltfrm-Fix-memory-leak-due-to-probe-defer b/patches.suse/scsi-ufs-ufshcd-pltfrm-Fix-memory-leak-due-to-probe-defer new file mode 100644 index 0000000..c44976c --- /dev/null +++ b/patches.suse/scsi-ufs-ufshcd-pltfrm-Fix-memory-leak-due-to-probe-defer @@ -0,0 +1,80 @@ +From: Srinivas Kandagatla +Date: Tue, 14 Sep 2021 10:22:14 +0100 +Subject: scsi: ufs: ufshcd-pltfrm: Fix memory leak due to probe defer +Git-commit: b6ca770ae7f2c560a29bbd02c4e3d734fafaf804 +Patch-mainline: v5.16-rc1 +References: git-fixes + +UFS drivers that probe defer will end up leaking memory allocated for clk +and regulator names via kstrdup() because the structure that is holding +this memory is allocated via devm_* variants which will be freed during +probe defer but the names are never freed. + +Use same devm_* variant of kstrdup to free the memory allocated to name +when driver probe defers. + +Kmemleak found around 11 leaks on Qualcomm Dragon Board RB5: + +unreferenced object 0xffff66f243fb2c00 (size 128): + comm "kworker/u16:0", pid 7, jiffies 4294893319 (age 94.848s) + hex dump (first 32 bytes): + 63 6f 72 65 5f 63 6c 6b 00 76 69 72 74 75 61 6c core_clk.virtual + 2f 77 6f 72 6b 71 75 65 75 65 2f 73 63 73 69 5f /workqueue/scsi_ + backtrace: + [<000000006f788cd1>] slab_post_alloc_hook+0x88/0x410 + [<00000000cfd1372b>] __kmalloc_track_caller+0x138/0x230 + [<00000000a92ab17b>] kstrdup+0xb0/0x110 + [<0000000037263ab6>] ufshcd_pltfrm_init+0x1a8/0x500 + [<00000000a20a5caa>] ufs_qcom_probe+0x20/0x58 + [<00000000a5e43067>] platform_probe+0x6c/0x118 + [<00000000ef686e3f>] really_probe+0xc4/0x330 + [<000000005b18792c>] __driver_probe_device+0x88/0x118 + [<00000000a5d295e8>] driver_probe_device+0x44/0x158 + [<000000007e83f58d>] __device_attach_driver+0xb4/0x128 + [<000000004bfa4470>] bus_for_each_drv+0x68/0xd0 + [<00000000b89a83bc>] __device_attach+0xec/0x170 + [<00000000ada2beea>] device_initial_probe+0x14/0x20 + [<0000000079921612>] bus_probe_device+0x9c/0xa8 + [<00000000d268bf7c>] deferred_probe_work_func+0x90/0xd0 + [<000000009ef64bfa>] process_one_work+0x29c/0x788 +unreferenced object 0xffff66f243fb2c80 (size 128): + comm "kworker/u16:0", pid 7, jiffies 4294893319 (age 94.848s) + hex dump (first 32 bytes): + 62 75 73 5f 61 67 67 72 5f 63 6c 6b 00 00 00 00 bus_aggr_clk.... + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + +With this patch no memory leaks are reported. + +[lduncan: applied with fuzz=3, refreshed] + +Link: https://lore.kernel.org/r/20210914092214.6468-1-srinivas.kandagatla@linaro.org +Fixes: aa4976130934 ("ufs: Add regulator enable support") +Fixes: c6e79dacd86f ("ufs: Add clock initialization support") +Reviewed-by: Bart Van Assche +Signed-off-by: Srinivas Kandagatla +Signed-off-by: Martin K. Petersen +Acked-by: Lee Duncan +--- + drivers/scsi/ufs/ufshcd-pltfrm.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/scsi/ufs/ufshcd-pltfrm.c ++++ b/drivers/scsi/ufs/ufshcd-pltfrm.c +@@ -116,7 +116,7 @@ static int ufshcd_parse_clock_info(struc + + clki->min_freq = clkfreq[i]; + clki->max_freq = clkfreq[i+1]; +- clki->name = kstrdup(name, GFP_KERNEL); ++ clki->name = devm_kstrdup(dev, name, GFP_KERNEL); + dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table-hz", + clki->min_freq, clki->max_freq, clki->name); + list_add_tail(&clki->list, &hba->clk_list_head); +@@ -150,7 +150,7 @@ static int ufshcd_populate_vreg(struct d + if (!vreg) + return -ENOMEM; + +- vreg->name = kstrdup(name, GFP_KERNEL); ++ vreg->name = devm_kstrdup(dev, name, GFP_KERNEL); + + snprintf(prop_name, MAX_PROP_SIZE, "%s-max-microamp", name); + if (of_property_read_u32(np, prop_name, &vreg->max_uA)) { diff --git a/patches.suse/stmmac-platform-Fix-signedness-bug-in-stmmac_probe_c.patch b/patches.suse/stmmac-platform-Fix-signedness-bug-in-stmmac_probe_c.patch new file mode 100644 index 0000000..c125e69 --- /dev/null +++ b/patches.suse/stmmac-platform-Fix-signedness-bug-in-stmmac_probe_c.patch @@ -0,0 +1,44 @@ +From: YueHaibing +Date: Wed, 7 Jul 2021 15:53:35 +0800 +Subject: stmmac: platform: Fix signedness bug in stmmac_probe_config_dt() + +Git-commit: eca81f09145d765c21dd8fb1ba5d874ca255c32c +Patch-mainline: v5.14-rc2 +References: git-fixes + +The "plat->phy_interface" variable is an enum and in this context GCC +will treat it as an unsigned int so the error handling is never +triggered. + +Fixes: b9f0b2f634c0 ("net: stmmac: platform: fix probe for ACPI devices") +Signed-off-by: YueHaibing +Signed-off-by: David S. Miller +Signed-off-by: Mian Yousaf Kaukab +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -369,6 +369,7 @@ stmmac_probe_config_dt(struct platform_d + struct device_node *np = pdev->dev.of_node; + struct plat_stmmacenet_data *plat; + struct stmmac_dma_cfg *dma_cfg; ++ int phy_mode; + int rc; + + plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); +@@ -409,7 +409,12 @@ stmmac_probe_config_dt(struct platform_d + *mac = NULL; + } + +- plat->phy_interface = device_get_phy_mode(&pdev->dev); ++ phy_mode = device_get_phy_mode(&pdev->dev); ++ if (phy_mode < 0) ++ return ERR_PTR(phy_mode); ++ ++ plat->interface = phy_mode; ++ + if (plat->phy_interface < 0) + return ERR_PTR(plat->phy_interface); + diff --git a/patches.suse/supported-flag-modverdir b/patches.suse/supported-flag-modverdir index 1415731..47d2849 100644 --- a/patches.suse/supported-flag-modverdir +++ b/patches.suse/supported-flag-modverdir @@ -4,7 +4,7 @@ Date: Fri, 9 Aug 2019 12:04:46 +0200 Subject: [PATCH] Bring back MODVERDIR to Makefile.modpost References: bsc#1066369 -Patch-mainline: no, SUSE specific +Patch-mainline: Never, SUSE specific Signed-off-by: Michal Suchanek --- diff --git a/patches.suse/swiotlb-xen-avoid-double-free.patch b/patches.suse/swiotlb-xen-avoid-double-free.patch new file mode 100644 index 0000000..cf53cd8 --- /dev/null +++ b/patches.suse/swiotlb-xen-avoid-double-free.patch @@ -0,0 +1,38 @@ +Patch-mainline: v5.15-rc2 +Git-commit: ce6a80d1b2f923b1839655a1cda786293feaa085 +References: git-fixes +From: Jan Beulich +Date: Tue, 7 Sep 2021 14:04:25 +0200 +Subject: [PATCH] swiotlb-xen: avoid double free + +Of the two paths leading to the "error" label in xen_swiotlb_init() one +didn't allocate anything, while the other did already free what was +allocated. + +Fixes: b82776005369 ("xen/swiotlb: Use the swiotlb_late_init_with_tbl to init Xen-SWIOTLB late when PV PCI is used") +Signed-off-by: Jan Beulich +Cc: stable@vger.kernel.org +Reviewed-by: Christoph Hellwig + +Link: https://lore.kernel.org/r/ce9c2adb-8a52-6293-982a-0d6ece943ac6@suse.com +Signed-off-by: Juergen Gross +--- + drivers/xen/swiotlb-xen.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c +index 24d11861ac7d..99d518526eaf 100644 +--- a/drivers/xen/swiotlb-xen.c ++++ b/drivers/xen/swiotlb-xen.c +@@ -267,8 +268,6 @@ int __ref xen_swiotlb_init(void) + pr_err("%s (rc:%d)\n", xen_swiotlb_error(m_ret), rc); + if (early) + panic("%s (rc:%d)", xen_swiotlb_error(m_ret), rc); +- else +- free_pages((unsigned long)xen_io_tlb_start, order); + return rc; + } + +-- +2.26.2 + diff --git a/patches.suse/tracing-Increase-PERF_MAX_TRACE_SIZE-to-handle-Senti.patch b/patches.suse/tracing-Increase-PERF_MAX_TRACE_SIZE-to-handle-Senti.patch new file mode 100644 index 0000000..29cb443 --- /dev/null +++ b/patches.suse/tracing-Increase-PERF_MAX_TRACE_SIZE-to-handle-Senti.patch @@ -0,0 +1,90 @@ +From e531e90b5ab0f7ce5ff298e165214c1aec6ed187 Mon Sep 17 00:00:00 2001 +From: "Robin H. Johnson" +Date: Mon, 30 Aug 2021 21:37:23 -0700 +Subject: [PATCH] tracing: Increase PERF_MAX_TRACE_SIZE to handle Sentinel1 and + docker together +Git-commit: e531e90b5ab0f7ce5ff298e165214c1aec6ed187 +Patch-mainline: v5.16-rc1 +References: bsc#1192745 + +Running endpoint security solutions like Sentinel1 that use perf-based +tracing heavily lead to this repeated dump complaining about dockerd. +The default value of 2048 is nowhere near not large enough. + +Using the prior patch "tracing: show size of requested buffer", we get +"perf buffer not large enough, wanted 6644, have 6144", after repeated +up-sizing (I did 2/4/6/8K). With 8K, the problem doesn't occur at all, +so below is the trace for 6K. + +I'm wondering if this value should be selectable at boot time, but this +is a good starting point. + +``` + +------------[ cut here ]------------ +perf buffer not large enough, wanted 6644, have 6144 +WARNING: CPU: 1 PID: 4997 at kernel/trace/trace_event_perf.c:402 perf_trace_buf_alloc+0x8c/0xa0 +Modules linked in: [..] +CPU: 1 PID: 4997 Comm: sh Tainted: G T 5.13.13-x86_64-00039-gb3959163488e #63 +Hardware name: LENOVO 20KH002JUS/20KH002JUS, BIOS N23ET66W (1.41 ) 09/02/2019 +RIP: 0010:perf_trace_buf_alloc+0x8c/0xa0 +Code: 80 3d 43 97 d0 01 00 74 07 31 c0 5b 5d 41 5c c3 ba 00 18 00 00 89 ee 48 c7 c7 00 82 7d 91 c6 05 25 97 d0 01 01 e8 22 ee bc 00 <0f> 0b 31 c0 eb db 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 00 55 89 +RSP: 0018:ffffb922026b7d58 EFLAGS: 00010282 +RAX: 0000000000000000 RBX: ffff9da5ee012000 RCX: 0000000000000027 +RDX: ffff9da881657828 RSI: 0000000000000001 RDI: ffff9da881657820 +RBP: 00000000000019f4 R08: 0000000000000000 R09: ffffb922026b7b80 +R10: ffffb922026b7b78 R11: ffffffff91dda688 R12: 000000000000000f +R13: ffff9da5ee012108 R14: ffff9da8816570a0 R15: ffffb922026b7e30 +FS: 00007f420db1a080(0000) GS:ffff9da881640000(0000) knlGS:0000000000000000 +CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 +CR2: 0000000000000060 CR3: 00000002504a8006 CR4: 00000000003706e0 +DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 +DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 +Call Trace: + kprobe_perf_func+0x11e/0x270 + ? do_execveat_common.isra.0+0x1/0x1c0 + ? do_execveat_common.isra.0+0x5/0x1c0 + kprobe_ftrace_handler+0x10e/0x1d0 + 0xffffffffc03aa0c8 + ? do_execveat_common.isra.0+0x1/0x1c0 + do_execveat_common.isra.0+0x5/0x1c0 + __x64_sys_execve+0x33/0x40 + do_syscall_64+0x6b/0xc0 + ? do_syscall_64+0x11/0xc0 + entry_SYSCALL_64_after_hwframe+0x44/0xae +RIP: 0033:0x7f420dc1db37 +Code: ff ff 76 e7 f7 d8 64 41 89 00 eb df 0f 1f 80 00 00 00 00 f7 d8 64 41 89 00 eb dc 0f 1f 84 00 00 00 00 00 b8 3b 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 01 43 0f 00 f7 d8 64 89 01 48 +RSP: 002b:00007ffd4e8b4e38 EFLAGS: 00000246 ORIG_RAX: 000000000000003b +RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f420dc1db37 +RDX: 0000564338d1e740 RSI: 0000564338d32d50 RDI: 0000564338d28f00 +RBP: 0000564338d28f00 R08: 0000564338d32d50 R09: 0000000000000020 +R10: 00000000000001b6 R11: 0000000000000246 R12: 0000564338d28f00 +R13: 0000564338d32d50 R14: 0000564338d1e740 R15: 0000564338d28c60 +---[ end trace 83ab3e8e16275e49 ]--- +``` + +Link: https://lkml.kernel.org/r/20210831043723.13481-2-robbat2@gentoo.org + +Signed-off-by: Robin H. Johnson +Signed-off-by: Steven Rostedt (VMware) +Acked-by: Petr Mladek +--- + include/linux/trace_events.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h +index 3e475eeb5a99..50453b287615 100644 +--- a/include/linux/trace_events.h ++++ b/include/linux/trace_events.h +@@ -671,7 +671,7 @@ struct trace_event_file { + } \ + early_initcall(trace_init_perf_perm_##name); + +-#define PERF_MAX_TRACE_SIZE 2048 ++#define PERF_MAX_TRACE_SIZE 8192 + + #define MAX_FILTER_STR_VAL 256 /* Should handle KSYM_SYMBOL_LEN */ + +-- +2.26.2 + diff --git a/patches.suse/tracing-histogram-Do-not-copy-the-fixed-size-char-array-field-over-the-field-size.patch b/patches.suse/tracing-histogram-Do-not-copy-the-fixed-size-char-array-field-over-the-field-size.patch new file mode 100644 index 0000000..e03b8d7 --- /dev/null +++ b/patches.suse/tracing-histogram-Do-not-copy-the-fixed-size-char-array-field-over-the-field-size.patch @@ -0,0 +1,65 @@ +From: Masami Hiramatsu +Date: Sat, 13 Nov 2021 01:02:08 +0900 +Subject: tracing/histogram: Do not copy the fixed-size char array field over + the field size +Git-commit: 63f84ae6b82bb4dff672f76f30c6fd7b9d3766bc +Patch-mainline: v5.16-rc1 +References: git-fixes + +Do not copy the fixed-size char array field of the events over +the field size. The histogram treats char array as a string and +there are 2 types of char array in the event, fixed-size and +dynamic string. The dynamic string (__data_loc) field must be +null terminated, but the fixed-size char array field may not +be null terminated (not a string, but just a data). +In that case, histogram can copy the data after the field. +This uses the original field size for fixed-size char array +field to restrict the histogram not to access over the original +field size. + +Link: https://lkml.kernel.org/r/163673292822.195747.3696966210526410250.stgit@devnote2 + +Fixes: 02205a6752f2 (tracing: Add support for 'field variables') +Signed-off-by: Masami Hiramatsu +Signed-off-by: Steven Rostedt (VMware) +Acked-by: Miroslav Benes +--- + kernel/trace/trace_events_hist.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c +index 8ff572a31fd3..6a9fa34e2785 100644 +--- a/kernel/trace/trace_events_hist.c ++++ b/kernel/trace/trace_events_hist.c +@@ -1953,9 +1953,10 @@ static struct hist_field *create_hist_field(struct hist_trigger_data *hist_data, + if (!hist_field->type) + goto free; + +- if (field->filter_type == FILTER_STATIC_STRING) ++ if (field->filter_type == FILTER_STATIC_STRING) { + hist_field->fn = hist_field_string; +- else if (field->filter_type == FILTER_DYN_STRING) ++ hist_field->size = field->size; ++ } else if (field->filter_type == FILTER_DYN_STRING) + hist_field->fn = hist_field_dynstring; + else + hist_field->fn = hist_field_pstring; +@@ -3025,7 +3026,7 @@ static inline void __update_field_vars(struct tracing_map_elt *elt, + char *str = elt_data->field_var_str[j++]; + char *val_str = (char *)(uintptr_t)var_val; + +- strscpy(str, val_str, STR_VAR_LEN_MAX); ++ strscpy(str, val_str, val->size); + var_val = (u64)(uintptr_t)str; + } + tracing_map_set_var(elt, var_idx, var_val); +@@ -4920,7 +4921,7 @@ static void hist_trigger_elt_update(struct hist_trigger_data *hist_data, + + str = elt_data->field_var_str[idx]; + val_str = (char *)(uintptr_t)hist_val; +- strscpy(str, val_str, STR_VAR_LEN_MAX); ++ strscpy(str, val_str, hist_field->size); + + hist_val = (u64)(uintptr_t)str; + } + diff --git a/patches.suse/tracing-use-ps-format-string-to-print-symbols.patch b/patches.suse/tracing-use-ps-format-string-to-print-symbols.patch new file mode 100644 index 0000000..b7e76b1 --- /dev/null +++ b/patches.suse/tracing-use-ps-format-string-to-print-symbols.patch @@ -0,0 +1,89 @@ +From: Arnd Bergmann +Date: Tue, 19 Oct 2021 17:33:13 +0200 +Subject: tracing: use %ps format string to print symbols +Git-commit: 8720aeecc246837bc6da64c5118dc3177c162e14 +Patch-mainline: v5.16-rc1 +References: git-fixes + +clang started warning about excessive stack usage in +hist_trigger_print_key() + +kernel/trace/trace_events_hist.c:4723:13: error: stack frame size (1336) exceeds limit (1024) in function 'hist_trigger_print_key' [-Werror,-Wframe-larger-than] + +The problem is that there are two 512-byte arrays on the stack if +hist_trigger_stacktrace_print() gets inlined. I don't think this has +changed in the past five years, but something probably changed the +inlining decisions made by the compiler, so the problem is now made +more obvious. + +Rather than printing the symbol names into separate buffers, it +seems we can simply use the special %ps format string modifier +to print the pointers symbolically and get rid of both buffers. + +Marking hist_trigger_stacktrace_print() would be a simpler +way of avoiding the warning, but that would not address the +excessive stack usage. + +Link: https://lkml.kernel.org/r/20211019153337.294790-1-arnd@kernel.org + +Fixes: 69a0200c2e25 ("tracing: Add hist trigger support for stacktraces as keys") +Link: https://lore.kernel.org/all/20211015095704.49a99859@gandalf.local.home/ +Reviewed-by: Tom Zanussi +Tested-by: Tom Zanussi +Signed-off-by: Arnd Bergmann +Signed-off-by: Steven Rostedt (VMware) +Acked-by: Miroslav Benes +--- + kernel/trace/trace_events_hist.c | 15 +++++---------- + 1 file changed, 5 insertions(+), 10 deletions(-) + +diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c +index a6061a69aa84..b64aed538628 100644 +--- a/kernel/trace/trace_events_hist.c ++++ b/kernel/trace/trace_events_hist.c +@@ -4706,7 +4706,6 @@ static void hist_trigger_stacktrace_print(struct seq_file *m, + unsigned long *stacktrace_entries, + unsigned int max_entries) + { +- char str[KSYM_SYMBOL_LEN]; + unsigned int spaces = 8; + unsigned int i; + +@@ -4715,8 +4714,7 @@ static void hist_trigger_stacktrace_print(struct seq_file *m, + return; + + seq_printf(m, "%*c", 1 + spaces, ' '); +- sprint_symbol(str, stacktrace_entries[i]); +- seq_printf(m, "%s\n", str); ++ seq_printf(m, "%pS\n", (void*)stacktrace_entries[i]); + } + } + +@@ -4726,7 +4724,6 @@ static void hist_trigger_print_key(struct seq_file *m, + struct tracing_map_elt *elt) + { + struct hist_field *key_field; +- char str[KSYM_SYMBOL_LEN]; + bool multiline = false; + const char *field_name; + unsigned int i; +@@ -4747,14 +4744,12 @@ static void hist_trigger_print_key(struct seq_file *m, + seq_printf(m, "%s: %llx", field_name, uval); + } else if (key_field->flags & HIST_FIELD_FL_SYM) { + uval = *(u64 *)(key + key_field->offset); +- sprint_symbol_no_offset(str, uval); +- seq_printf(m, "%s: [%llx] %-45s", field_name, +- uval, str); ++ seq_printf(m, "%s: [%llx] %-45ps", field_name, ++ uval, (void *)(uintptr_t)uval); + } else if (key_field->flags & HIST_FIELD_FL_SYM_OFFSET) { + uval = *(u64 *)(key + key_field->offset); +- sprint_symbol(str, uval); +- seq_printf(m, "%s: [%llx] %-55s", field_name, +- uval, str); ++ seq_printf(m, "%s: [%llx] %-55pS", field_name, ++ uval, (void *)(uintptr_t)uval); + } else if (key_field->flags & HIST_FIELD_FL_EXECNAME) { + struct hist_elt_data *elt_data = elt->private_data; + char *comm; + diff --git a/patches.suse/x86-Xen-swap-NX-determination-and-GDT-setup-on-BSP.patch b/patches.suse/x86-Xen-swap-NX-determination-and-GDT-setup-on-BSP.patch new file mode 100644 index 0000000..49d69a8 --- /dev/null +++ b/patches.suse/x86-Xen-swap-NX-determination-and-GDT-setup-on-BSP.patch @@ -0,0 +1,55 @@ +Patch-mainline: v5.13-rc3 +Git-commit: ae897fda4f507e4b239f0bdfd578b3688ca96fb4 +References: git-fixes +From: Jan Beulich +Date: Thu, 20 May 2021 13:42:42 +0200 +Subject: [PATCH] x86/Xen: swap NX determination and GDT setup on BSP + +xen_setup_gdt(), via xen_load_gdt_boot(), wants to adjust page tables. +For this to work when NX is not available, x86_configure_nx() needs to +be called first. + +[jgross] Note that this is a revert of 36104cb9012a82e73 ("x86/xen: +Delay get_cpu_cap until stack canary is established"), which is possible +now that we no longer support running as PV guest in 32-bit mode. + +Cc: # 5.9 +Fixes: 36104cb9012a82e73 ("x86/xen: Delay get_cpu_cap until stack canary is established") +Reported-by: Olaf Hering +Signed-off-by: Jan Beulich +Reviewed-by: Juergen Gross + +Link: https://lore.kernel.org/r/12a866b0-9e89-59f7-ebeb-a2a6cec0987a@suse.com +Signed-off-by: Juergen Gross +--- + arch/x86/xen/enlighten_pv.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c +index 17503fed2017..e87699aa2dc8 100644 +--- a/arch/x86/xen/enlighten_pv.c ++++ b/arch/x86/xen/enlighten_pv.c +@@ -1273,16 +1273,16 @@ asmlinkage __visible void __init xen_start_kernel(void) + /* Get mfn list */ + xen_build_dynamic_phys_to_machine(); + ++ /* Work out if we support NX */ ++ get_cpu_cap(&boot_cpu_data); ++ x86_configure_nx(); ++ + /* + * Set up kernel GDT and segment registers, mainly so that + * -fstack-protector code can be executed. + */ + xen_setup_gdt(0); + +- /* Work out if we support NX */ +- get_cpu_cap(&boot_cpu_data); +- x86_configure_nx(); +- + /* Determine virtual and physical address sizes */ + get_cpu_address_sizes(&boot_cpu_data); + +-- +2.26.2 + diff --git a/patches.suse/x86-sme-use-define-use_early_pgtable_l5-in-mem_encrypt_identity-c.patch b/patches.suse/x86-sme-use-define-use_early_pgtable_l5-in-mem_encrypt_identity-c.patch new file mode 100644 index 0000000..da3dbfe --- /dev/null +++ b/patches.suse/x86-sme-use-define-use_early_pgtable_l5-in-mem_encrypt_identity-c.patch @@ -0,0 +1,57 @@ +From: Tom Lendacky +Date: Fri, 15 Oct 2021 12:24:16 -0500 +Subject: x86/sme: Use #define USE_EARLY_PGTABLE_L5 in mem_encrypt_identity.c +Git-commit: e7d445ab26db833d6640d4c9a08bee176777cc82 +Patch-mainline: v5.16-rc1 +References: bsc#1152489 + +When runtime support for converting between 4-level and 5-level pagetables +was added to the kernel, the SME code that built pagetables was updated +to use the pagetable functions, e.g. p4d_offset(), etc., in order to +simplify the code. However, the use of the pagetable functions in early +boot code requires the use of the USE_EARLY_PGTABLE_L5 #define in order to +ensure that the proper definition of pgtable_l5_enabled() is used. + +Without the #define, pgtable_l5_enabled() is #defined as +cpu_feature_enabled(X86_FEATURE_LA57). In early boot, the CPU features +have not yet been discovered and populated, so pgtable_l5_enabled() will +return false even when 5-level paging is enabled. This causes the SME code +to always build 4-level pagetables to perform the in-place encryption. +If 5-level paging is enabled, switching to the SME pagetables results in +a page-fault that kills the boot. + +Adding the #define results in pgtable_l5_enabled() using the +__pgtable_l5_enabled variable set in early boot and the SME code building +pagetables for the proper paging level. + +Fixes: aad983913d77 ("x86/mm/encrypt: Simplify sme_populate_pgd() and sme_populate_pgd_large()") +Signed-off-by: Tom Lendacky +Signed-off-by: Borislav Petkov +Acked-by: Kirill A. Shutemov +Cc: # 4.18.x +Link: https://lkml.kernel.org/r/2cb8329655f5c753905812d951e212022a480475.1634318656.git.thomas.lendacky@amd.com +--- + arch/x86/mm/mem_encrypt_identity.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_identity.c +index 470b20208430..700ce8fdea87 100644 +--- a/arch/x86/mm/mem_encrypt_identity.c ++++ b/arch/x86/mm/mem_encrypt_identity.c +@@ -27,6 +27,15 @@ + #undef CONFIG_PARAVIRT_XXL + #undef CONFIG_PARAVIRT_SPINLOCKS + ++/* ++ * This code runs before CPU feature bits are set. By default, the ++ * pgtable_l5_enabled() function uses bit X86_FEATURE_LA57 to determine if ++ * 5-level paging is active, so that won't work here. USE_EARLY_PGTABLE_L5 ++ * is provided to handle this situation and, instead, use a variable that ++ * has been set by the early boot code. ++ */ ++#define USE_EARLY_PGTABLE_L5 ++ + #include + #include + #include + diff --git a/patches.suse/x86-xen-Mark-cpu_bringup_and_idle-as-dead_end_functi.patch b/patches.suse/x86-xen-Mark-cpu_bringup_and_idle-as-dead_end_functi.patch new file mode 100644 index 0000000..db07314 --- /dev/null +++ b/patches.suse/x86-xen-Mark-cpu_bringup_and_idle-as-dead_end_functi.patch @@ -0,0 +1,45 @@ +Patch-mainline: v5.16-rc1 +Git-commit: 9af9dcf11bda3e2c0e24c1acaacb8685ad974e93 +References: git-fixes +From: Peter Zijlstra +Date: Thu, 24 Jun 2021 11:41:00 +0200 +Subject: [PATCH] x86/xen: Mark cpu_bringup_and_idle() as dead_end_function + +The asm_cpu_bringup_and_idle() function is required to push the return +value on the stack in order to make ORC happy, but the only reason +objtool doesn't complain is because of a happy accident. + +The thing is that asm_cpu_bringup_and_idle() doesn't return, so +validate_branch() never terminates and falls through to the next +function, which in the normal case is the hypercall_page. And that, as +it happens, is 4095 NOPs and a RET. + +Make asm_cpu_bringup_and_idle() terminate on it's own, by making the +function it calls as a dead-end. This way we no longer rely on what +code happens to come after. + +Fixes: c3881eb58d56 ("x86/xen: Make the secondary CPU idle tasks reliable") +Signed-off-by: Peter Zijlstra (Intel) +Reviewed-by: Juergen Gross +Reviewed-by: Miroslav Benes +Link: https://lore.kernel.org/r/20210624095147.693801717@infradead.org +Signed-off-by: Juergen Gross +--- + tools/objtool/check.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/tools/objtool/check.c b/tools/objtool/check.c +index e5947fbb9e7a..0e3981d91afc 100644 +--- a/tools/objtool/check.c ++++ b/tools/objtool/check.c +@@ -161,6 +161,7 @@ static bool __dead_end_function(struct objtool_file *file, struct symbol *func, + "usercopy_abort", + "machine_real_restart", + "rewind_stack_do_exit", ++ "cpu_bringup_and_idle", + }; + + if (!func) +-- +2.26.2 + diff --git a/patches.suse/xen-Fix-implicit-type-conversion.patch b/patches.suse/xen-Fix-implicit-type-conversion.patch new file mode 100644 index 0000000..2952b65 --- /dev/null +++ b/patches.suse/xen-Fix-implicit-type-conversion.patch @@ -0,0 +1,61 @@ +Patch-mainline: v5.16-rc1 +Git-commit: cbd5458ef19594c7a1ec69e77a624a5502a79eb9 +References: git-fixes +From: Jiasheng Jiang +Date: Tue, 26 Oct 2021 07:32:11 +0000 +Subject: [PATCH] xen: Fix implicit type conversion + +The variable 'i' is defined as UINT. However, in the for_each_possible_cpu +its value is assigned to -1. That doesn't make sense and in the +cpumask_next() it is implicitly type converted to INT. It is universally +accepted that the implicit type conversion is terrible. Also, having the +good programming custom will set an example for others. Thus, it might be +better to change the definition of 'i' from UINT to INT. + +[boris: fixed commit message formatting] + +Fixes: 3fac10145b76 ("xen: Re-upload processor PM data to hypervisor after S3 resume (v2)") +Signed-off-by: Jiasheng Jiang +Link: https://lore.kernel.org/r/1635233531-2437704-1-git-send-email-jiasheng@iscas.ac.cn +Reviewed-by: Juergen Gross +Reviewed-by: Jiamei Xie +Signed-off-by: Boris Ostrovsky +Signed-off-by: Juergen Gross +--- + drivers/xen/xen-acpi-processor.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/xen/xen-acpi-processor.c b/drivers/xen/xen-acpi-processor.c +index df7cab870be5..9cb61db67efd 100644 +--- a/drivers/xen/xen-acpi-processor.c ++++ b/drivers/xen/xen-acpi-processor.c +@@ -450,7 +450,7 @@ static struct acpi_processor_performance __percpu *acpi_perf_data; + + static void free_acpi_perf_data(void) + { +- unsigned int i; ++ int i; + + /* Freeing a NULL pointer is OK, and alloc_percpu zeroes. */ + for_each_possible_cpu(i) +@@ -462,7 +462,7 @@ static void free_acpi_perf_data(void) + static int xen_upload_processor_pm_data(void) + { + struct acpi_processor *pr_backup = NULL; +- unsigned int i; ++ int i; + int rc = 0; + + pr_info("Uploading Xen processor PM info\n"); +@@ -518,7 +518,7 @@ static struct syscore_ops xap_syscore_ops = { + + static int __init xen_acpi_processor_init(void) + { +- unsigned int i; ++ int i; + int rc; + + if (!xen_initial_domain()) +-- +2.26.2 + diff --git a/patches.suse/xen-pciback-Fix-return-in-pm_ctrl_init.patch b/patches.suse/xen-pciback-Fix-return-in-pm_ctrl_init.patch new file mode 100644 index 0000000..da8c4d8 --- /dev/null +++ b/patches.suse/xen-pciback-Fix-return-in-pm_ctrl_init.patch @@ -0,0 +1,38 @@ +Patch-mainline: v5.16-rc1 +Git-commit: 4745ea2628bb43a7ec34b71763b5a56407b33990 +References: git-fixes +From: YueHaibing +Date: Fri, 8 Oct 2021 15:44:17 +0800 +Subject: [PATCH] xen-pciback: Fix return in pm_ctrl_init() + +Return NULL instead of passing to ERR_PTR while err is zero, +this fix smatch warnings: +drivers/xen/xen-pciback/conf_space_capability.c:163 + pm_ctrl_init() warn: passing zero to 'ERR_PTR' + +Fixes: a92336a1176b ("xen/pciback: Drop two backends, squash and cleanup some code.") +Signed-off-by: YueHaibing +Reviewed-by: Juergen Gross +Link: https://lore.kernel.org/r/20211008074417.8260-1-yuehaibing@huawei.com +Signed-off-by: Boris Ostrovsky +Signed-off-by: Juergen Gross +--- + drivers/xen/xen-pciback/conf_space_capability.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/xen/xen-pciback/conf_space_capability.c b/drivers/xen/xen-pciback/conf_space_capability.c +index 22f13abbe913..5e53b4817f16 100644 +--- a/drivers/xen/xen-pciback/conf_space_capability.c ++++ b/drivers/xen/xen-pciback/conf_space_capability.c +@@ -160,7 +160,7 @@ static void *pm_ctrl_init(struct pci_dev *dev, int offset) + } + + out: +- return ERR_PTR(err); ++ return err ? ERR_PTR(err) : NULL; + } + + static const struct config_field caplist_pm[] = { +-- +2.26.2 + diff --git a/patches.suse/xen-privcmd-fix-error-handling-in-mmap-resource-proc.patch b/patches.suse/xen-privcmd-fix-error-handling-in-mmap-resource-proc.patch new file mode 100644 index 0000000..3e971cf --- /dev/null +++ b/patches.suse/xen-privcmd-fix-error-handling-in-mmap-resource-proc.patch @@ -0,0 +1,54 @@ +Patch-mainline: v5.15-rc5 +Git-commit: e11423d6721dd63b23fb41ade5e8d0b448b17780 +References: git-fixes +From: Jan Beulich +Date: Wed, 22 Sep 2021 12:17:48 +0200 +Subject: [PATCH] xen/privcmd: fix error handling in mmap-resource processing + +xen_pfn_t is the same size as int only on 32-bit builds (and not even +on Arm32). Hence pfns[] can't be used directly to read individual error +values returned from xen_remap_domain_mfn_array(); every other error +indicator would be skipped/ignored on 64-bit. + +Fixes: 3ad0876554ca ("xen/privcmd: add IOCTL_PRIVCMD_MMAP_RESOURCE") +Cc: stable@vger.kernel.org +Signed-off-by: Jan Beulich +Reviewed-by: Boris Ostrovsky + +Link: https://lore.kernel.org/r/aa6d6a67-6889-338a-a910-51e889f792d5@suse.com +Signed-off-by: Juergen Gross +--- + drivers/xen/privcmd.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c +index a3f2031aa3d9..5af2a295e32f 100644 +--- a/drivers/xen/privcmd.c ++++ b/drivers/xen/privcmd.c +@@ -803,11 +803,12 @@ static long privcmd_ioctl_mmap_resource(struct file *file, + unsigned int domid = + (xdata.flags & XENMEM_rsrc_acq_caller_owned) ? + DOMID_SELF : kdata.dom; +- int num; ++ int num, *errs = (int *)pfns; + ++ BUILD_BUG_ON(sizeof(*errs) > sizeof(*pfns)); + num = xen_remap_domain_mfn_array(vma, + kdata.addr & PAGE_MASK, +- pfns, kdata.num, (int *)pfns, ++ pfns, kdata.num, errs, + vma->vm_page_prot, + domid, + vma->vm_private_data); +@@ -817,7 +818,7 @@ static long privcmd_ioctl_mmap_resource(struct file *file, + unsigned int i; + + for (i = 0; i < num; i++) { +- rc = pfns[i]; ++ rc = errs[i]; + if (rc < 0) + break; + } +-- +2.26.2 + diff --git a/patches.suse/xen-x86-fix-PV-trap-handling-on-secondary-processors.patch b/patches.suse/xen-x86-fix-PV-trap-handling-on-secondary-processors.patch new file mode 100644 index 0000000..5a57461 --- /dev/null +++ b/patches.suse/xen-x86-fix-PV-trap-handling-on-secondary-processors.patch @@ -0,0 +1,100 @@ +Patch-mainline: v5.15-rc3 +Git-commit: 0594c58161b6e0f3da8efa9c6e3d4ba52b652717 +References: git-fixes +From: Jan Beulich +Date: Mon, 20 Sep 2021 18:15:11 +0200 +Subject: [PATCH] xen/x86: fix PV trap handling on secondary processors + +The initial observation was that in PV mode under Xen 32-bit user space +didn't work anymore. Attempts of system calls ended in #GP(0x402). All +of the sudden the vector 0x80 handler was not in place anymore. As it +turns out up to 5.13 redundant initialization did occur: Once from +cpu_initialize_context() (through its VCPUOP_initialise hypercall) and a +2nd time while each CPU was brought fully up. This 2nd initialization is +now gone, uncovering that the 1st one was flawed: Unlike for the +set_trap_table hypercall, a full virtual IDT needs to be specified here; +the "vector" fields of the individual entries are of no interest. With +many (kernel) IDT entries still(?) (i.e. at that point at least) empty, +the syscall vector 0x80 ended up in slot 0x20 of the virtual IDT, thus +becoming the domain's handler for vector 0x20. + +Make xen_convert_trap_info() fit for either purpose, leveraging the fact +that on the xen_copy_trap_info() path the table starts out zero-filled. +This includes moving out the writing of the sentinel, which would also +have lead to a buffer overrun in the xen_copy_trap_info() case if all +(kernel) IDT entries were populated. Convert the writing of the sentinel +to clearing of the entire table entry rather than just the address +field. + +(I didn't bother trying to identify the commit which uncovered the issue +in 5.14; the commit named below is the one which actually introduced the +bad code.) + +Fixes: f87e4cac4f4e ("xen: SMP guest support") +Cc: stable@vger.kernel.org +Signed-off-by: Jan Beulich +Reviewed-by: Boris Ostrovsky +Link: https://lore.kernel.org/r/7a266932-092e-b68f-f2bb-1473b61adc6e@suse.com +Signed-off-by: Juergen Gross +--- + arch/x86/xen/enlighten_pv.c | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c +index 349f780a1567..6e0d0754f94f 100644 +--- a/arch/x86/xen/enlighten_pv.c ++++ b/arch/x86/xen/enlighten_pv.c +@@ -755,8 +755,8 @@ static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g) + preempt_enable(); + } + +-static void xen_convert_trap_info(const struct desc_ptr *desc, +- struct trap_info *traps) ++static unsigned xen_convert_trap_info(const struct desc_ptr *desc, ++ struct trap_info *traps, bool full) + { + unsigned in, out, count; + +@@ -766,17 +766,18 @@ static void xen_convert_trap_info(const struct desc_ptr *desc, + for (in = out = 0; in < count; in++) { + gate_desc *entry = (gate_desc *)(desc->address) + in; + +- if (cvt_gate_to_trap(in, entry, &traps[out])) ++ if (cvt_gate_to_trap(in, entry, &traps[out]) || full) + out++; + } +- traps[out].address = 0; ++ ++ return out; + } + + void xen_copy_trap_info(struct trap_info *traps) + { + const struct desc_ptr *desc = this_cpu_ptr(&idt_desc); + +- xen_convert_trap_info(desc, traps); ++ xen_convert_trap_info(desc, traps, true); + } + + /* Load a new IDT into Xen. In principle this can be per-CPU, so we +@@ -786,6 +787,7 @@ static void xen_load_idt(const struct desc_ptr *desc) + { + static DEFINE_SPINLOCK(lock); + static struct trap_info traps[257]; ++ unsigned out; + + trace_xen_cpu_load_idt(desc); + +@@ -793,7 +795,8 @@ static void xen_load_idt(const struct desc_ptr *desc) + + memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc)); + +- xen_convert_trap_info(desc, traps); ++ out = xen_convert_trap_info(desc, traps, false); ++ memset(&traps[out], 0, sizeof(traps[0])); + + xen_mc_flush(); + if (HYPERVISOR_set_trap_table(traps)) +-- +2.26.2 + diff --git a/patches.suse/zram-avoid-race-between-zram_remove-and-disksize_sto.patch b/patches.suse/zram-avoid-race-between-zram_remove-and-disksize_sto.patch new file mode 100644 index 0000000..4e2ba82 --- /dev/null +++ b/patches.suse/zram-avoid-race-between-zram_remove-and-disksize_sto.patch @@ -0,0 +1,43 @@ +From 5a4b653655d554b5f51a5d2252882708c56a6f7e Mon Sep 17 00:00:00 2001 +From: Ming Lei +Date: Mon, 25 Oct 2021 10:54:25 +0800 +Subject: [PATCH] zram: avoid race between zram_remove and disksize_store +Git-commit: 5a4b653655d554b5f51a5d2252882708c56a6f7e +Reviewed-by: Luis Chamberlain +Patch-mainline: v5.16-rc1 +References: bsc#1170269 + +After resetting device in zram_remove(), disksize_store still may come and +allocate resources again before deleting gendisk, fix the race by resetting +zram after del_gendisk() returns. At that time, disksize_store can't come +any more. + +Reported-by: Luis Chamberlain +Reviewed-by: Luis Chamberlain +Signed-off-by: Ming Lei +Acked-by: Minchan Kim +Link: https://lore.kernel.org/r/20211025025426.2815424-4-ming.lei@redhat.com +Signed-off-by: Jens Axboe +Signed-off-by: Luis Chamberlain +--- + drivers/block/zram/zram_drv.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c +index b12694c..dcde8d8 100644 +--- a/drivers/block/zram/zram_drv.c ++++ b/drivers/block/zram/zram_drv.c +@@ -2006,6 +2006,13 @@ static int zram_remove(struct zram *zram) + /* del_gendisk drains pending reset_store */ + WARN_ON_ONCE(claimed && zram->claim); + ++ /* ++ * disksize_store() may be called in between zram_reset_device() ++ * and del_gendisk(), so run the last reset to avoid leaking ++ * anything allocated with disksize_store() ++ */ ++ zram_reset_device(zram); ++ + blk_cleanup_queue(zram->disk->queue); + put_disk(zram->disk); + kfree(zram); diff --git a/patches.suse/zram-don-t-fail-to-remove-zram-during-unloading-modu.patch b/patches.suse/zram-don-t-fail-to-remove-zram-during-unloading-modu.patch new file mode 100644 index 0000000..d591cc7 --- /dev/null +++ b/patches.suse/zram-don-t-fail-to-remove-zram-during-unloading-modu.patch @@ -0,0 +1,101 @@ +From 8c54499a59b026a3dc2afccf6e1b36d5700d2fef Mon Sep 17 00:00:00 2001 +From: Ming Lei +Date: Mon, 25 Oct 2021 10:54:24 +0800 +Subject: [PATCH] zram: don't fail to remove zram during unloading module +Git-commit: 8c54499a59b026a3dc2afccf6e1b36d5700d2fef +Reviewed-by: Luis Chamberlain +Patch-mainline: v5.16-rc1 +References: bsc#1170269 + +When the zram module is being unloaded, no one should be using the +zram disks. However even while being unloaded the zram module's +sysfs attributes might be poked at to re-configure zram devices. +This is expected, and kernfs ensures that these operations complete +before device_del() completes. + +But reset_store() may set ->claim which will fail zram_remove(), when +this happens, zram_reset_device() is bypassed, and zram->comp can't +be destroyed, so the warning of 'Error: Removing state 63 which has +instances left.' is triggered during unloading module, together with +memory leak and sort of thing. + +Fixes the issue by not failing zram_remove() if ->claim is set, and +we actually need to do nothing in case that zram_reset() is running +since del_gendisk() will wait until zram_reset() is done. + +Reported-by: Luis Chamberlain +Reviewed-by: Luis Chamberlain +Signed-off-by: Ming Lei +Acked-by: Minchan Kim +Link: https://lore.kernel.org/r/20211025025426.2815424-3-ming.lei@redhat.com +Signed-off-by: Jens Axboe +Signed-off-by: Luis Chamberlain +--- + drivers/block/zram/zram_drv.c | 27 +++++++++++++++++++++------ + 1 file changed, 21 insertions(+), 6 deletions(-) + +diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c +index 313e093..b12694c 100644 +--- a/drivers/block/zram/zram_drv.c ++++ b/drivers/block/zram/zram_drv.c +@@ -1966,31 +1966,46 @@ static int zram_add(void) + static int zram_remove(struct zram *zram) + { + struct block_device *bdev; ++ bool claimed; + + bdev = bdget_disk(zram->disk, 0); + if (!bdev) + return -ENOMEM; + + mutex_lock(&bdev->bd_mutex); +- if (bdev->bd_openers || zram->claim) { ++ if (bdev->bd_openers) { + mutex_unlock(&bdev->bd_mutex); + bdput(bdev); + return -EBUSY; + } + +- zram->claim = true; ++ claimed = zram->claim; ++ if (!claimed) ++ zram->claim = true; + mutex_unlock(&bdev->bd_mutex); + + zram_debugfs_unregister(zram); + ++ if (claimed) { ++ /* ++ * If we were claimed by reset_store(), del_gendisk() will ++ * wait until reset_store() is done, so nothing need to do. ++ */ ++ ; ++ } else { + /* Make sure all the pending I/O are finished */ +- fsync_bdev(bdev); +- zram_reset_device(zram); +- bdput(bdev); ++ fsync_bdev(bdev); ++ zram_reset_device(zram); ++ bdput(bdev); ++ } + + pr_info("Removed device: %s\n", zram->disk->disk_name); + + del_gendisk(zram->disk); ++ ++ /* del_gendisk drains pending reset_store */ ++ WARN_ON_ONCE(claimed && zram->claim); ++ + blk_cleanup_queue(zram->disk->queue); + put_disk(zram->disk); + kfree(zram); +@@ -2068,7 +2083,7 @@ static struct class zram_control_class = { + + static int zram_remove_cb(int id, void *ptr, void *data) + { +- zram_remove(ptr); ++ WARN_ON_ONCE(zram_remove(ptr)); + return 0; + } + diff --git a/patches.suse/zram-fix-race-between-zram_reset_device-and-disksize.patch b/patches.suse/zram-fix-race-between-zram_reset_device-and-disksize.patch new file mode 100644 index 0000000..5c4723b --- /dev/null +++ b/patches.suse/zram-fix-race-between-zram_reset_device-and-disksize.patch @@ -0,0 +1,45 @@ +From 6f1637795f2827d36aec9e0246487f5852e8abf7 Mon Sep 17 00:00:00 2001 +From: Ming Lei +Date: Mon, 25 Oct 2021 10:54:23 +0800 +Subject: [PATCH] zram: fix race between zram_reset_device() and + disksize_store() +Git-commit: 6f1637795f2827d36aec9e0246487f5852e8abf7 +Reviewed-by: Luis Chamberlain +Patch-mainline: v5.16-rc1 +References: bsc#1170269 + +When the ->init_lock is released in zram_reset_device(), disksize_store() +can come in and try to allocate meta, but zram_reset_device() is freeing +free meta, so cause races. + +Link: https://lore.kernel.org/linux-block/20210927163805.808907-1-mcgrof@kernel.org/T/#mc617f865a3fa2778e40f317ddf48f6447c20c073 +Reported-by: Luis Chamberlain +Reviewed-by: Luis Chamberlain +Signed-off-by: Ming Lei +Acked-by: Minchan Kim +Link: https://lore.kernel.org/r/20211025025426.2815424-2-ming.lei@redhat.com +Signed-off-by: Jens Axboe +Signed-off-by: Luis Chamberlain +--- + drivers/block/zram/zram_drv.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c +index f09259f..313e093 100644 +--- a/drivers/block/zram/zram_drv.c ++++ b/drivers/block/zram/zram_drv.c +@@ -1691,12 +1691,13 @@ static void zram_reset_device(struct zram *zram) + set_capacity(zram->disk, 0); + part_stat_set_all(&zram->disk->part0, 0); + +- up_write(&zram->init_lock); + /* I/O operation under all of CPU are done so let's free */ + zram_meta_free(zram, disksize); + memset(&zram->stats, 0, sizeof(zram->stats)); + zcomp_destroy(comp); + reset_bdev(zram); ++ ++ up_write(&zram->init_lock); + } + + static ssize_t disksize_store(struct device *dev, diff --git a/patches.suse/zram-replace-fsync_bdev-with-sync_blockdev.patch b/patches.suse/zram-replace-fsync_bdev-with-sync_blockdev.patch new file mode 100644 index 0000000..d0bb36d --- /dev/null +++ b/patches.suse/zram-replace-fsync_bdev-with-sync_blockdev.patch @@ -0,0 +1,45 @@ +From 00c5495c54f785beb0f6a34f7a3674d3ea0997d5 Mon Sep 17 00:00:00 2001 +From: Ming Lei +Date: Mon, 25 Oct 2021 10:54:26 +0800 +Subject: [PATCH] zram: replace fsync_bdev with sync_blockdev +Git-commit: 00c5495c54f785beb0f6a34f7a3674d3ea0997d5 +Reviewed-by: Luis Chamberlain +Patch-mainline: v5.16-rc1 +References: bsc#1170269 + +When calling fsync_bdev(), zram driver guarantees that the bdev won't be +opened by anyone, then there can't be one active fs/superblock over the +zram bdev, so replace fsync_bdev with sync_blockdev. + +Reviewed-by: Luis Chamberlain +Signed-off-by: Ming Lei +Acked-by: Minchan Kim +Link: https://lore.kernel.org/r/20211025025426.2815424-5-ming.lei@redhat.com +Signed-off-by: Jens Axboe +Signed-off-by: Luis Chamberlain +--- + drivers/block/zram/zram_drv.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c +index dcde8d8..862e603 100644 +--- a/drivers/block/zram/zram_drv.c ++++ b/drivers/block/zram/zram_drv.c +@@ -1782,7 +1782,7 @@ static ssize_t reset_store(struct device *dev, + mutex_unlock(&bdev->bd_mutex); + + /* Make sure all the pending I/O are finished */ +- fsync_bdev(bdev); ++ sync_blockdev(bdev); + zram_reset_device(zram); + revalidate_disk_size(zram->disk, true); + bdput(bdev); +@@ -1994,7 +1994,7 @@ static int zram_remove(struct zram *zram) + ; + } else { + /* Make sure all the pending I/O are finished */ +- fsync_bdev(bdev); ++ sync_blockdev(bdev); + zram_reset_device(zram); + bdput(bdev); + } diff --git a/rpm/kernel-cert-subpackage b/rpm/kernel-cert-subpackage index 8bdf47d..44aaa05 100644 --- a/rpm/kernel-cert-subpackage +++ b/rpm/kernel-cert-subpackage @@ -1,8 +1,8 @@ %package -n %{-n*}-ueficert Summary: UEFI Secure Boot Certificate For Package %{-n*}-kmp Group: System/Kernel -Requires(post): suse-kernel-rpm-scriptlets Requires(pre): suse-kernel-rpm-scriptlets +Requires(postun): suse-kernel-rpm-scriptlets %description -n %{-n*}-ueficert This package contains the UEFI Secure Boot certificate used to sign modules in the %{-n*}-kmp packages. diff --git a/rpm/kernel-module-subpackage b/rpm/kernel-module-subpackage index e8c1a89..d00434f 100644 --- a/rpm/kernel-module-subpackage +++ b/rpm/kernel-module-subpackage @@ -26,6 +26,8 @@ Provides: %{-n*}-kmp = %{-v*} Provides: multiversion(kernel) Provides: %{-n*}-kmp-%1-%_this_kmp_kernel_version Requires: coreutils grep +Requires(pre): suse-kernel-rpm-scriptlets +Requires(postun): suse-kernel-rpm-scriptlets %{-c:Requires: %{-n*}-ueficert} Enhances: kernel-%1 Supplements: packageand(kernel-%1:%{-n*}) diff --git a/scripts/bugzilla/_cli.py b/scripts/bugzilla/_cli.py index d314d38..1c10586 100644 --- a/scripts/bugzilla/_cli.py +++ b/scripts/bugzilla/_cli.py @@ -635,7 +635,8 @@ def _do_info(bz, opt): elif opt.versions: proddict = bz.getproducts()[0] for v in proddict['versions']: - print(to_encoding(v["name"])) + if v["is_active"]: + print(to_encoding(v["name"])) elif opt.component_owners: details = bz.getcomponentsdetails(productname) diff --git a/scripts/git_sort/git_sort.py b/scripts/git_sort/git_sort.py index 2c1b8df..a6102da 100755 --- a/scripts/git_sort/git_sort.py +++ b/scripts/git_sort/git_sort.py @@ -239,6 +239,7 @@ remotes = ( Head(RepoURL("herbert/crypto-2.6.git"), "master"), Head(RepoURL("rafael/linux-pm.git")), Head(RepoURL("git://git.linux-nfs.org/~bfields/linux.git"), "nfsd-next"), + Head(RepoURL("git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux.git"), "for-next"), Head(RepoURL("vkoul/soundwire.git"),"fixes"), Head(RepoURL("vkoul/soundwire.git"),"next"), Head(RepoURL("arm64/linux.git"), "for-next/core"), @@ -255,6 +256,7 @@ remotes = ( Head(RepoURL("clk/linux.git"), "clk-next"), Head(RepoURL("git://github.com/ceph/ceph-client"), "testing"), Head(RepoURL("bpf/bpf.git")), + Head(RepoURL("linusw/linux-gpio.git"), "for-next"), ) diff --git a/scripts/git_sort/tests/opensuse-15.0/Dockerfile b/scripts/git_sort/tests/opensuse-15.0/Dockerfile deleted file mode 100644 index 0959660..0000000 --- a/scripts/git_sort/tests/opensuse-15.0/Dockerfile +++ /dev/null @@ -1,25 +0,0 @@ -# https://hub.docker.com/r/opensuse/leap/ -FROM opensuse/leap:15.0 AS base - -RUN zypper -n ref - -FROM base AS packages - -RUN zypper -n in git python3 python3-dbm rcs - -RUN git config --global user.email "you@example.com" -RUN git config --global user.name "Your Name" - -RUN zypper -n ar -G https://download.opensuse.org/repositories/Kernel:/tools/openSUSE_Leap_15.0/Kernel:tools.repo -RUN zypper -n in python3-pygit2 - -RUN zypper -n ar -G https://download.opensuse.org/repositories/home:/benjamin_poirier:/series_sort/openSUSE_Leap_15.0/home:benjamin_poirier:series_sort.repo -RUN zypper -n in --from home_benjamin_poirier_series_sort quilt - -FROM packages - -VOLUME /scripts - -WORKDIR /scripts/git_sort - -CMD python3 -m unittest discover -v diff --git a/scripts/git_sort/tests/opensuse-15.3/Dockerfile b/scripts/git_sort/tests/opensuse-15.3/Dockerfile new file mode 100644 index 0000000..6c45bc6 --- /dev/null +++ b/scripts/git_sort/tests/opensuse-15.3/Dockerfile @@ -0,0 +1,22 @@ +# https://hub.docker.com/r/opensuse/leap/ +FROM opensuse/leap:15.3 AS base + +RUN zypper -n ref + +FROM base AS packages + +RUN zypper -n in git python3 python3-dbm rcs + +RUN git config --global user.email "you@example.com" +RUN git config --global user.name "Your Name" + +RUN zypper -n ar -G https://download.opensuse.org/repositories/Kernel:/tools/openSUSE_Leap_15.3/Kernel:tools.repo +RUN zypper -n in python3-pygit2 quilt + +FROM packages + +VOLUME /scripts + +WORKDIR /scripts/git_sort + +CMD python3 -m unittest discover -v diff --git a/scripts/git_sort/tests/opensuse-tumbleweed/Dockerfile b/scripts/git_sort/tests/opensuse-tumbleweed/Dockerfile index 182c8d0..3497815 100644 --- a/scripts/git_sort/tests/opensuse-tumbleweed/Dockerfile +++ b/scripts/git_sort/tests/opensuse-tumbleweed/Dockerfile @@ -10,8 +10,8 @@ RUN zypper -n in git python3 python3-dbm python3-pygit2 rcs RUN git config --global user.email "you@example.com" RUN git config --global user.name "Your Name" -RUN zypper -n ar -G https://download.opensuse.org/repositories/home:/benjamin_poirier:/series_sort/openSUSE_Tumbleweed/home:benjamin_poirier:series_sort.repo -RUN zypper -n in --from home_benjamin_poirier_series_sort quilt +RUN zypper -n ar -G https://download.opensuse.org/repositories/Kernel:/tools/openSUSE_Factory/Kernel:tools.repo +RUN zypper -n in --from Kernel_tools quilt FROM packages diff --git a/scripts/git_sort/tests/run_all.sh b/scripts/git_sort/tests/run_all.sh index 8764b19..0177c1a 100755 --- a/scripts/git_sort/tests/run_all.sh +++ b/scripts/git_sort/tests/run_all.sh @@ -2,19 +2,11 @@ libdir=$(dirname "$(readlink -f "$0")") -# The sle12-sp2 image is not picked up by registry.suse.de, import it manually -if [ $(docker image ls -q benjamin_poirier/docker_images/sle-12-sp2:latest | wc -l) -ne 1 ]; then - echo "Fetching base image for sle12-sp2..." - wget -q -O - http://download.suse.de/ibs/home:/benjamin_poirier:/docker_images:/SLE-12-SP2/images/x86_64/sles12sp2-docker-image.rpm | \ - rpm2cpio - | cpio -i --quiet --to-stdout *.tar.xz | xzcat | \ - docker import - benjamin_poirier/docker_images/sle-12-sp2 -fi - for release in \ - sle12-sp2 \ - sle12-sp3 \ + sle12-sp4 \ + sle12-sp5 \ sle15 \ - opensuse-15.0 \ + opensuse-15.3 \ opensuse-tumbleweed \ ; do echo "Building container image for $release..." diff --git a/scripts/git_sort/tests/sle12-sp2/Dockerfile b/scripts/git_sort/tests/sle12-sp2/Dockerfile deleted file mode 100644 index f5bfc48..0000000 --- a/scripts/git_sort/tests/sle12-sp2/Dockerfile +++ /dev/null @@ -1,24 +0,0 @@ -FROM benjamin_poirier/docker_images/sle-12-sp2:latest AS base - -RUN zypper -n --no-gpg-checks ref - -FROM base AS packages - -RUN zypper -n in git python3 python3-dbm rcs - -RUN git config --global user.email "you@example.com" -RUN git config --global user.name "Your Name" - -RUN zypper -n ar -G https://download.opensuse.org/repositories/Kernel:/tools/SLE_12_SP2/Kernel:tools.repo -RUN zypper -n in python3-pygit2 - -RUN zypper -n ar -G https://download.opensuse.org/repositories/home:/benjamin_poirier:/series_sort/SLE_12_SP2/home:benjamin_poirier:series_sort.repo -RUN zypper -n in --from home_benjamin_poirier_series_sort quilt - -FROM packages - -VOLUME /scripts - -WORKDIR /scripts/git_sort - -CMD python3 -m unittest discover -v diff --git a/scripts/git_sort/tests/sle12-sp3/Dockerfile b/scripts/git_sort/tests/sle12-sp3/Dockerfile deleted file mode 100644 index df097b6..0000000 --- a/scripts/git_sort/tests/sle12-sp3/Dockerfile +++ /dev/null @@ -1,25 +0,0 @@ -# http://registry.suse.de/ -FROM registry.suse.de/home/benjamin_poirier/docker_images/sle-12-sp3/images/suse/sles12sp3:2.0.3 AS base - -RUN zypper -n ref - -FROM base AS packages - -RUN zypper -n in git python3 python3-dbm rcs - -RUN git config --global user.email "you@example.com" -RUN git config --global user.name "Your Name" - -RUN zypper -n ar -G https://download.opensuse.org/repositories/Kernel:/tools/SLE_12_SP3/Kernel:tools.repo -RUN zypper -n in python3-pygit2 - -RUN zypper -n ar -G https://download.opensuse.org/repositories/home:/benjamin_poirier:/series_sort/SLE_12_SP3/home:benjamin_poirier:series_sort.repo -RUN zypper -n in --from home_benjamin_poirier_series_sort quilt - -FROM packages - -VOLUME /scripts - -WORKDIR /scripts/git_sort - -CMD python3 -m unittest discover -v diff --git a/scripts/git_sort/tests/sle12-sp4/Dockerfile b/scripts/git_sort/tests/sle12-sp4/Dockerfile new file mode 100644 index 0000000..e0c545b --- /dev/null +++ b/scripts/git_sort/tests/sle12-sp4/Dockerfile @@ -0,0 +1,31 @@ +# http://registry.suse.de/ +FROM registry.suse.de/suse/containers/sle-server/12-sp4/containers/suse/sles12sp4:latest AS base + +RUN rpm -e container-suseconnect +RUN zypper -n ar -G http://download.suse.de/ibs/SUSE:/SLE-12:/GA/standard/SUSE:SLE-12:GA.repo +RUN zypper -n ar -G http://download.suse.de/ibs/SUSE:/SLE-12:/Update/standard/SUSE:SLE-12:Update.repo +RUN zypper -n ar -G http://download.suse.de/install/SLP/SLE-12-SP4-Server-GM/$(rpm -E %_arch)/DVD1/ DVD1 +RUN zypper -n ar -G http://download.suse.de/install/SLP/SLE-12-SP4-Server-GM/$(rpm -E %_arch)/DVD2/ DVD2 +RUN zypper -n ar -G http://download.suse.de/install/SLP/SLE-12-SP4-Server-GM/$(rpm -E %_arch)/DVD3/ DVD3 +# RUN zypper -n ar -G http://updates.suse.de/SUSE/Products/SLE-SDK/12-SP4/$(rpm -E %_arch)/product/ SDK +RUN zypper -n ar -G http://download.suse.de/update/build.suse.de/SUSE/Updates/SLE-SERVER/12-SP4/$(rpm -E %_arch)/update/SUSE:Updates:SLE-SERVER:12-SP4:$(rpm -E %_arch).repo + +RUN zypper -n ref + +FROM base AS packages + +RUN zypper -n in git-core python3 python3-dbm rcs + +RUN git config --global user.email "you@example.com" +RUN git config --global user.name "Your Name" + +RUN zypper -n ar -G https://download.opensuse.org/repositories/Kernel:/tools/SLE_12_SP4/Kernel:tools.repo +RUN zypper -n in python3-pygit2 quilt + +FROM packages + +VOLUME /scripts + +WORKDIR /scripts/git_sort + +CMD python3 -m unittest discover -v diff --git a/scripts/git_sort/tests/sle12-sp5/Dockerfile b/scripts/git_sort/tests/sle12-sp5/Dockerfile new file mode 100644 index 0000000..c8b601d --- /dev/null +++ b/scripts/git_sort/tests/sle12-sp5/Dockerfile @@ -0,0 +1,31 @@ +# http://registry.suse.de/ +FROM registry.suse.de/suse/containers/sle-server/12-sp5/containers/suse/sles12sp5:latest AS base + +RUN rpm -e container-suseconnect +RUN zypper -n ar -G http://download.suse.de/ibs/SUSE:/SLE-12:/GA/standard/SUSE:SLE-12:GA.repo +RUN zypper -n ar -G http://download.suse.de/ibs/SUSE:/SLE-12:/Update/standard/SUSE:SLE-12:Update.repo +RUN zypper -n ar -G http://download.suse.de/install/SLP/SLE-12-SP5-Server-GM/$(rpm -E %_arch)/DVD1/ DVD1 +RUN zypper -n ar -G http://download.suse.de/install/SLP/SLE-12-SP5-Server-GM/$(rpm -E %_arch)/DVD2/ DVD2 +RUN zypper -n ar -G http://download.suse.de/install/SLP/SLE-12-SP5-Server-GM/$(rpm -E %_arch)/DVD3/ DVD3 +# RUN zypper -n ar -G http://updates.suse.de/SUSE/Products/SLE-SDK/12-SP5/$(rpm -E %_arch)/product/ SDK +RUN zypper -n ar -G http://download.suse.de/update/build.suse.de/SUSE/Updates/SLE-SERVER/12-SP5/$(rpm -E %_arch)/update/SUSE:Updates:SLE-SERVER:12-SP5:$(rpm -E %_arch).repo + +RUN zypper -n ref + +FROM base AS packages + +RUN zypper -n in git-core python3 python3-dbm rcs + +RUN git config --global user.email "you@example.com" +RUN git config --global user.name "Your Name" + +RUN zypper -n ar -G https://download.opensuse.org/repositories/Kernel:/tools/SLE_12_SP5/Kernel:tools.repo +RUN zypper -n in python3-pygit2 quilt + +FROM packages + +VOLUME /scripts + +WORKDIR /scripts/git_sort + +CMD python3 -m unittest discover -v diff --git a/scripts/git_sort/tests/sle15/Dockerfile b/scripts/git_sort/tests/sle15/Dockerfile index 3b08991..3fd5bf4 100644 --- a/scripts/git_sort/tests/sle15/Dockerfile +++ b/scripts/git_sort/tests/sle15/Dockerfile @@ -1,20 +1,20 @@ # http://registry.suse.de/ -FROM registry.suse.de/home/david_chang/branches/devel/docker/images/sle15/images/suse/sles15:2.0.3 AS base +FROM registry.suse.de/suse/containers/sle-server/15/containers/bci/python:3.9 AS base +RUN rpm -e container-suseconnect +RUN zypper -n ar -G http://download.suse.de/ibs/SUSE:/SLE-15:/GA/standard/SUSE:SLE-15:GA.repo +RUN zypper -n ar -G http://download.suse.de/ibs/SUSE:/SLE-15:/Update/standard/SUSE:SLE-15:Update.repo RUN zypper -n ref FROM base AS packages -RUN zypper -n in git python3 python3-dbm rcs awk +RUN zypper -n in git-core python3 python3-dbm rcs awk RUN git config --global user.email "you@example.com" RUN git config --global user.name "Your Name" RUN zypper -n ar -G https://download.opensuse.org/repositories/Kernel:/tools/SLE_15/Kernel:tools.repo -RUN zypper -n in python3-pygit2 - -RUN zypper -n ar -G https://download.opensuse.org/repositories/home:/benjamin_poirier:/series_sort/SLE_15/home:benjamin_poirier:series_sort.repo -RUN zypper -n in --from home_benjamin_poirier_series_sort quilt +RUN zypper -n in python3-pygit2 quilt FROM packages diff --git a/scripts/lib/SUSE/MyBS.pm b/scripts/lib/SUSE/MyBS.pm index 41fa503..206a5f3 100644 --- a/scripts/lib/SUSE/MyBS.pm +++ b/scripts/lib/SUSE/MyBS.pm @@ -62,7 +62,7 @@ sub new { die join("\n", @Config::IniFiles::errors), "\n"; } my %cred; - for my $kw (qw(user pass passx keyring credentials_mgr_class)) { + for my $kw (qw(user pass passx keyring gnome_keyring credentials_mgr_class)) { for my $section ($api_url, "$api_url/", $self->{url}->host) { if (exists($config{$section}) && exists($config{$section}{$kw})) { @@ -84,7 +84,7 @@ sub new { IO::Uncompress::Bunzip2::bunzip2(\$bz2 => \$cred{pass}) or die "Decoding password for $api_url failed: $IO::Uncompress::Bunzip2::Bunzip2Error\n"; } - if (!exists($cred{pass}) && exists($cred{keyring})) { + if (!exists($cred{pass}) && (exists($cred{keyring}) || exists($cred{gnome_keyring}))) { my $api = $api_url; $api =~ s/^https?:\/\///; open(my $secret, "secret-tool lookup service $api username $cred{user} |") diff --git a/scripts/python/check-patchhdr b/scripts/python/check-patchhdr index bfa28fc..0f8f89e 100755 --- a/scripts/python/check-patchhdr +++ b/scripts/python/check-patchhdr @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/python3 # -*- coding: utf-8 -*-, from __future__ import absolute_import @@ -24,15 +24,19 @@ if __name__ == "__main__": parser.error("Must either provide filename(s) or use --stdin") sys.exit(128) + if options.stdin and len(args) > 1 : + parser.error("Only one filename can be used with --stdin") + sys.exit(128) + errors = 0 if options.stdin: + if args: + fn = args[0] + else: + fn = "" try: - checker = header.Checker(sys.stdin, options.update) + checker = header.Checker(sys.stdin, options.update, fn) except header.HeaderException as e: - if args: - fn = args[0] - else: - fn = "" print(e.error_message(fn), file=sys.stderr) if not fn.startswith("patches.xen/"): errors += 1 @@ -40,7 +44,7 @@ if __name__ == "__main__": for fn in args: try: f = open(fn) - checker = header.Checker(f, options.update) + checker = header.Checker(f, options.update, fn) f.close() except header.HeaderException as e: print(e.error_message(fn), file=sys.stderr) diff --git a/scripts/python/suse_git/header.py b/scripts/python/suse_git/header.py index c12697d..1cbf0a9 100755 --- a/scripts/python/suse_git/header.py +++ b/scripts/python/suse_git/header.py @@ -13,6 +13,7 @@ tag_regex = re.compile("(\S+):[ \t]*(.*)") tag_map = { 'Patch-mainline' : { 'required' : True, + 'required_on_kabi' : False, 'accepted' : [ { # In mainline repo, tagged for release @@ -41,6 +42,7 @@ tag_map = { 'name' : 'No', 'match' : 'No,?\s+.+', 'excludes' : [ 'Git-commit', 'Git-repo' ], + 'error' : "Please use 'Not yet' or 'Never'", }, { # Never, typically used for patches that have been rejected # for upstream inclusion but still have a compelling reason @@ -276,9 +278,12 @@ class Tag: return False class HeaderChecker(patch.PatchChecker): - def __init__(self, stream, updating=False): + def __init__(self, stream, updating=False, filename=""): patch.PatchChecker.__init__(self) self.updating = updating + self.filename = filename + self.kabi = re.match("^patches[.]kabi/", self.filename) + if isinstance(stream, str): stream = StringIO(stream) self.stream = stream @@ -293,6 +298,10 @@ class HeaderChecker(patch.PatchChecker): def get_rulename(self, ruleset, rulename): if rulename in ruleset: + if self.kabi: + kabi_rule = "%s_on_kabi" % rulename + if kabi_rule in ruleset: + return kabi_rule if self.updating: updating_rule = "%s_on_update" % rulename if updating_rule in ruleset: @@ -438,6 +447,9 @@ class HeaderChecker(patch.PatchChecker): found = True if not found: required = True + if self.kabi and 'required_on_kabi' in tag_map[entry]: + if not tag_map[entry]['required_on_kabi']: + required = False if self.updating and 'required_on_update' in tag_map[entry]: if not tag_map[entry]['required_on_update']: required = False diff --git a/scripts/python/tests/test_header.py b/scripts/python/tests/test_header.py index 003c0c8..59a2906 100755 --- a/scripts/python/tests/test_header.py +++ b/scripts/python/tests/test_header.py @@ -368,7 +368,12 @@ Patch-mainline: No, handled differently upstream References: bsc#12345 Acked-by: developer@suse.com """ - self.header = header.Checker(text) + with self.assertRaises(header.HeaderException) as cm: + self.header = header.Checker(text) + + e = cm.exception + self.assertEqual(1, e.errors(header.FormatError)) + self.assertEqual(1, e.errors()) def test_patch_mainline_not_yet_detail(self): text = """ @@ -701,3 +706,12 @@ Acked-by: developer@suse.com self.assertEqual(1, e.errors(header.MissingTagError)) self.assertTrue(e.tag_is_missing('references')) self.assertEqual(1, e.errors()) + + def test_no_patch_mainline_for_kabi(self): + text = """ +From: developer@site.com +Subject: some patch +References: FATE#123456 +Acked-by: developer@suse.com +""" + self.header = header.Checker(text, False, "patches.kabi/FATE123456_fix_kabi.patch") diff --git a/scripts/run_oldconfig.sh b/scripts/run_oldconfig.sh index 429bf0a..5659bfe 100755 --- a/scripts/run_oldconfig.sh +++ b/scripts/run_oldconfig.sh @@ -426,6 +426,7 @@ for config in $config_files; do chmod 755 scripts/dummy-tools/* chmod 755 scripts/* fi + MAKE_ARGS="$MAKE_ARGS RUSTC=/nothing/nowhere" if $silent; then MAKE_ARGS="$MAKE_ARGS -s" fi diff --git a/scripts/sequence-patch.sh b/scripts/sequence-patch.sh index 5cfecd7..e1ea2f1 100755 --- a/scripts/sequence-patch.sh +++ b/scripts/sequence-patch.sh @@ -69,6 +69,9 @@ SYNOPSIS: $0 [-qv] [--symbol=...] [--dir=...] The --dry-run option only works with --fast and --rapid. + The --signing-key option specifies a pathname for a key to be used for + module signing and for signing the kernel for use with UEFI Secure Boot. + When used with last-patch-name, both --fast and --no-quilt will set up a quilt environment for the remaining patches. END @@ -212,7 +215,7 @@ if $have_arch_patches; then else arch_opt="" fi -options=`getopt -o qvd:F: --long quilt,no-quilt,$arch_opt,symbol:,dir:,combine,fast,rapid,vanilla,fuzz:,patch-dir:,build-dir:,config:,kabi,ctags,cscope,etags,skip-reverse,dry-run -- "$@"` +options=`getopt -o qvd:F: --long quilt,no-quilt,$arch_opt,symbol:,dir:,combine,fast,rapid,vanilla,fuzz:,patch-dir:,build-dir:,config:,kabi,ctags,cscope,etags,skip-reverse,dry-run,signing-key: -- "$@"` if [ $? -ne 0 ] then @@ -237,6 +240,7 @@ CSCOPE=false ETAGS=false SKIP_REVERSE=false DRY_RUN= +SIGNING_KEY= while true; do case "$1" in @@ -310,6 +314,10 @@ while true; do --dry-run) DRY_RUN=--dry-run ;; + --signing-key) + SIGNING_KEY="$2" + shift + ;; --) shift break ;; @@ -716,6 +724,107 @@ if test -n "$CONFIG"; then make -C $PATCH_DIR O=$SP_BUILD_DIR -s $syncconfig fi +filter_fingerprints() { + grep 'SHA1 Fingerprint' | sed -e 's/SHA1 Fingerprint.//' | \ + tr -d ' :' | tr a-z A-Z +} + +cert_fingerprint() { + local cert=$1 + + openssl x509 -fingerprint -noout -in "$cert" | filter_fingerprints +} + +cert_fingerprint8() { + local cert=$1 + + cert_fingerprint "$cert" | cut -b 1-8 +} + +cert_signature_algo() { + local cert=$1 + + # openssl doesn't have a way to just show the algo + openssl x509 -noout -text -in "$cert" | grep 'Signature Algorithm' | \ + tr -d ' ' | uniq | cut -d ':' -f 2 +} + +get_config_option() { + local config=$1 + local option=$2 + + sed -n "/^CONFIG_$option=/s///p" "$config" |tr -d '"' | tail -1 +} + +set_config_option() { + local config=$1 + local option=$2 + local value=$3 + + sed -i -e "/^CONFIG_$option=/s;=.*;=$value;" "$config" +} + +set_config_option_string() { + local config=$1 + local option=$2 + local value=$3 + + set_config_option "$config" "$option" "\"$value\"" +} + +copy_signing_key() { + local cert=$1 + + echo "[ Copying signing key $SIGNING_KEY ]" + + if ! test -f "$cert"; then + echo "*** ERROR: Signing key $cert does not exist" + return + fi + keyexts=$(openssl x509 -in $cert -ext keyUsage,extendedKeyUsage -noout) + + if ! echo $keyexts | grep -q "Code Signing"; then + echo "*** WARNING: Signing key must have extendedKeyUsage=codeSigning" \ + "to be used to sign kernel for Secure Boot" >&2 + fi + if ! echo $keyexts | grep -q "Digital Signature"; then + echo "*** WARNING: Signing key must have keyUsage=digitalSignature" \ + "to be used to sign modules" >&2 + fi + + mkdir -p "$SP_BUILD_DIR/certs" + certname="$(cert_fingerprint8 "$cert").pem" + cp "$cert" "$SP_BUILD_DIR/certs/$certname" + + if test -z "$CONFIG"; then + echo "*** WARNING: signing key copied to certs/$certname but" \ + "no config available to enable" + return + fi + + local config="$SP_BUILD_DIR/.config" + + # Check for algo compatibility + config_algo="$(get_config_option $config MODULE_SIG_HASH)" + if test -z "$config_algo"; then + echo "*** WARNING: Module signing is disabled in active config" + return + fi + + cert_algo=$(cert_signature_algo $cert) + cert_algo=${cert_algo%%WithRSAEncryption} + if test "$config_algo" != "$cert_algo"; then + echo "*** WARNING: Signing key uses hash algo '$cert_algo' but" \ + " kernel config uses '$config_algo'" + fi + + set_config_option_string $config MODULE_SIG_KEY "certs/$certname" +} + +if test -n "$SIGNING_KEY"; then + copy_signing_key $SIGNING_KEY +fi + # Some archs we use for the config do not exist or have a different name in the # kernl source tree case $CONFIG_ARCH in diff --git a/scripts/supported-conf-fixup b/scripts/supported-conf-fixup index 7f0b4b5..295bfd3 100755 --- a/scripts/supported-conf-fixup +++ b/scripts/supported-conf-fixup @@ -106,7 +106,7 @@ sub gather_path if ($file_or_dir eq "modules.builtin") { open(BUILTIN, "<$file_or_dir") or die; while () { - next unless m,^kernel/(.*)/([^/]+)\.ko(\.xz)?$,; + next unless m,^kernel/(.*)/([^/]+)\.ko(\.xz|\.gz|\.zst)?$,; $path = $1; $module = $2; @@ -124,7 +124,7 @@ sub gather_path return unless $module_path =~ s,^(.*?/)?kernel/,,; if (-f $file_or_dir) { - return unless $module_path =~ m,^(.*)/([^/]+)\.ko(\.xz)?$,; + return unless $module_path =~ m,^(.*)/([^/]+)\.ko(\.xz|\.gz|\.zst)?$,; $path = $1; $module = $2; @@ -264,7 +264,7 @@ sub check_path return; } - unless ($module_path =~ m,^(.*)/([^/]+)(\.ko)(\.xz)?$, || + unless ($module_path =~ m,^(.*)/([^/]+)(\.ko)(\.xz|\.gz|\.zst)?$, || $module_path =~ m,^(.*)/([^/]+)$,) { print STDERR "$sup_conf_file: $line: Unparsable module path: $module_path\n"; return; diff --git a/series.conf b/series.conf index 9a1febc..614680d 100644 --- a/series.conf +++ b/series.conf @@ -2529,6 +2529,9 @@ patches.suse/net-phy-add-__set_linkmode_max_speed.patch patches.suse/net-phy-add-phy_speed_down_core-and-phy_resolve_min_.patch patches.suse/net-phy-let-phy_speed_down-up-support-speeds-1Gbps.patch + patches.suse/r8152-separate-the-rx-buffer-size.patch + patches.suse/r8152-replace-array-with-linking-list-for-rx-informa.patch + patches.suse/r8152-use-alloc_pages-for-rx-buffer.patch patches.suse/netfilter-synproxy-rename-mss-synproxy_options-field.patch patches.suse/netfilter-conntrack-use-shared-sysctl-constants.patch patches.suse/0001-ipvs-Improve-robustness-to-the-ipvs-sysctl.patch @@ -2670,6 +2673,7 @@ patches.suse/rtlwifi-rtl8192ce-Convert-inline-routines-to-little-.patch patches.suse/Revert-mwifiex-fix-system-hang-problem-after-resume.patch patches.suse/b43legacy-Remove-pointless-cond_resched-wrapper.patch + patches.suse/r8152-divide-the-tx-and-rx-bottom-functions.patch patches.suse/net-dsa-use-a-single-switch-statement-for-port-setup.patch patches.suse/netdevsim-Fix-build-error-without-CONFIG_INET.patch patches.suse/s390-qeth-use-node_descriptor-struct @@ -2773,6 +2777,8 @@ patches.suse/i40e-fix-retrying-in-i40e_aq_get_phy_capabilities.patch patches.suse/net-fec-add-c45-mdio-read-write-support.patch patches.suse/ethernet-Delete-unnecessary-checks-before-the-macro-.patch + patches.suse/r8152-saving-the-settings-of-EEE.patch + patches.suse/r8152-add-a-helper-function-about-setting-EEE.patch patches.suse/net-ipv6-fix-listify-ip6_rcv_finish-in-case-of-forwa.patch patches.suse/net-mlx5-Fix-return-code-in-case-of-hyperv-wrong-siz.patch patches.suse/drop_monitor-Make-timestamps-y2038-safe.patch @@ -2816,6 +2822,9 @@ patches.suse/net-sched-flower-don-t-take-rtnl-lock-for-cls-hw-off.patch patches.suse/r8169-improve-DMA-handling-in-rtl_rx.patch patches.suse/nfp-add-AMDA0058-boards-to-firmware-list.patch + patches.suse/net-stmmac-add-EHL-SGMII-1Gbps-PCI-info-and-PCI-ID.patch + patches.suse/net-stmmac-add-TGL-SGMII-1Gbps-PCI-info-and-PCI-ID.patch + patches.suse/net-stmmac-add-EHL-RGMII-1Gbps-PCI-info-and-PCI-ID.patch patches.suse/ice-Fix-ethtool-port-and-PFC-stats-for-4x25G-cards.patch patches.suse/ice-added-sibling-head-to-parse-nodes.patch patches.suse/ice-Sanitize-ice_ena_vsi-and-ice_dis_vsi.patch @@ -3420,6 +3429,7 @@ patches.suse/qed-Fix-Config-attribute-frame-format.patch patches.suse/net-stmmac-implement-support-for-passive-mode-conver.patch patches.suse/net-phy-dp83867-Add-SGMII-mode-type-switching.patch + patches.suse/net-stmmac-pci-Add-HAPS-support-using-GMAC5.patch patches.suse/nfp-read-chip-model-from-the-PluDevice-register.patch patches.suse/cxgb4-Fix-spelling-typos.patch patches.suse/netfilter-nf_tables-Fix-an-Oops-in-nf_tables_updobj-.patch @@ -6285,6 +6295,7 @@ patches.suse/scsi-qla2xxx-Make-qlt_handle_abts_completion-more-ro.patch patches.suse/scsi-qla2xxx-Modify-NVMe-include-directives.patch patches.suse/scsi-qla2xxx-Introduce-qla2xxx_get_next_handle.patch + patches.suse/scsi-qla2xxx-Make-sure-that-aborted-commands-are-freed patches.suse/scsi-qla2xxx-Complain-if-sp-done-is-not-called-from-.patch patches.suse/scsi-qla2xxx-Let-the-compiler-check-the-type-of-the-.patch patches.suse/scsi-qla2xxx-Remove-superfluous-sts_entry_-casts.patch @@ -9100,6 +9111,7 @@ patches.suse/btrfs-use-refcount_inc_not_zero-in-kill_all_nodes.patch patches.suse/btrfs-drop-unused-parameter-is_new-from-btrfs_iget.patch patches.suse/btrfs-add-__cold-attribute-to-more-functions.patch + patches.suse/btrfs-block-group-Rework-documentation-of-check_syst.patch patches.suse/btrfs-Avoid-getting-stuck-during-cyclic-writebacks.patch patches.suse/btrfs-Rename-btrfs_join_transaction_nolock.patch patches.suse/btrfs-use-bool-argument-in-free_root_pointers.patch @@ -9947,6 +9959,7 @@ patches.suse/bnx2x-Fix-PF-VF-communication-over-multi-cos-queues.patch patches.suse/cnic-Set-fp_hsi_ver-as-part-of-CLIENT_SETUP-ramrod.patch patches.suse/cxgb4-Add-pci-reset-handler.patch + patches.suse/r8152-Add-macpassthru-support-for-ThinkPad-Thunderbo.patch patches.suse/brcmfmac-send-port-authorized-event-for-FT-802.1X.patch patches.suse/brcmsmac-remove-a-useless-test.patch patches.suse/brcmfmac-don-t-WARN-when-there-are-no-requests.patch @@ -11662,6 +11675,7 @@ patches.suse/pinctrl-devicetree-Avoid-taking-direct-reference-to-.patch patches.suse/pinctrl-ssbi-gpio-convert-to-hierarchical-IRQ-helper.patch patches.suse/pinctl-ti-iodelay-fix-error-checking-on-pinctrl_coun.patch + patches.suse/pinctrl-rockchip-add-rk3308-SoC-support.patch patches.suse/Revert-pinctrl-sh-pfc-r8a77990-Fix-MOD_SEL1-bit30-wh.patch patches.suse/Revert-pinctrl-sh-pfc-r8a77990-Fix-MOD_SEL1-bit31-wh.patch patches.suse/pinctrl-rza2-Fix-gpio-name-typos.patch @@ -16396,8 +16410,13 @@ patches.suse/airo-Add-missing-CAP_NET_ADMIN-check-in-AIROOLDIOCTL.patch patches.suse/net-rtnetlink-validate-IFLA_MTU-attribute-in-rtnl_cr.patch patches.suse/gtp-make-sure-only-SOCK_DGRAM-UDP-sockets-are-accept.patch + patches.suse/r8152-fix-runtime-resume-for-linking-change.patch + patches.suse/r8152-reset-flow-control-patch-when-linking-on-for-R.patch patches.suse/r8152-get-default-setting-of-WOL-before-initializing.patch + patches.suse/r8152-disable-U2P3-for-RTL8153B.patch + patches.suse/r8152-Disable-PLA-MCU-clock-speed-down.patch patches.suse/r8152-disable-test-IO-for-RTL8153B.patch + patches.suse/r8152-don-t-enable-U1U2-with-USB_SPEED_HIGH-for-RTL8.patch patches.suse/r8152-avoid-the-MCU-to-clear-the-lanwake.patch patches.suse/r8152-disable-DelayPhyPwrChg.patch patches.suse/mlxsw-spectrum_acl-Fix-use-after-free-during-reload.patch @@ -25509,6 +25528,9 @@ patches.suse/libbpf-Add-support-for-bpf_link-based-cgroup-attachm.patch patches.suse/selftests-bpf-Test-FD-based-cgroup-attachment.patch patches.suse/net-dsa-bcm_sf2-Fix-overflow-checks.patch + patches.suse/net-stmmac-create-dwmac-intel.c-to-contain-all-Intel.patch + patches.suse/net-stmmac-add-EHL-PSE0-PSE1-1Gbps-PCI-info-and-PCI-.patch + patches.suse/net-stmmac-add-EHL-2.5Gbps-PCI-info-and-PCI-ID.patch patches.suse/netdevsim-dev-Fix-memory-leak-in-nsim_dev_take_snaps.patch patches.suse/mac80211-fix-authentication-with-iwlwifi-mvm.patch patches.suse/ipv4-fix-a-RCU-list-lock-in-fib_triestat_seq_show.patch @@ -29871,6 +29893,7 @@ patches.suse/pstore-blk-support-non-block-storage-devices.patch patches.suse/pstore-blk-introduce-best_effort-mode.patch patches.suse/mtd-support-kmsg-dumper-based-on-pstore-blk.patch + patches.suse/printk-handle-blank-console-arguments-passed-in.patch patches.suse/edac-skx-i10nm-make-some-configurations-cpu-model-specific.patch patches.suse/edac-i10nm-update-driver-to-support-different-bus-number-config-register-offsets.patch patches.suse/edac-skx-use-the-mcmtr-register-to-retrieve-close_pg-bank_xor_enable.patch @@ -31611,6 +31634,7 @@ patches.suse/s390-dasd-remove-ioctl_by_bdev-calls.patch patches.suse/block-remove-ioctl_by_bdev.patch patches.suse/loop-remove-redundant-assignment-to-variable-error.patch + patches.suse/block-floppy-fix-contended-case-in-floppy_queue_rq.patch patches.suse/nvmet-replace-kstrndup-with-kmemdup_nul.patch patches.suse/nvmet-mark-nvmet_ana_state-static.patch patches.suse/nvme-tcp-set-MSG_SENDPAGE_NOTLAST-with-MSG_MORE-when.patch @@ -34003,6 +34027,7 @@ patches.suse/s390-Change-s390_kernel_write-return-type-to-match-m.patch patches.suse/livepatch-make-klp_apply_object_relocs-static.patch patches.suse/fanotify-fix-ignore-mask-logic-for-events-on-child-a.patch + patches.suse/mm-fix-mremap-not-considering-huge-pmd-devmap.patch patches.suse/mm-add-kvfree_sensitive-for-freeing-sensitive-data-o.patch patches.suse/0001-mm-memory_hotplug-refrain-from-adding-memory-into-an.patch patches.suse/0019-mm-memory_hotplug-introduce-add_memory_driver_manage.patch @@ -34940,6 +34965,7 @@ patches.suse/rtc-pcf2127-watchdog-handle-nowayout-feature.patch patches.suse/pinctrl-stmfx-stmfx_pinconf_set-doesn-t-require-to-g.patch patches.suse/pinctrl-rza1-Fix-wrong-array-assignment-of-rza1l_swi.patch + patches.suse/pinctrl-rockchip-return-ENOMEM-instead-of-EINVAL-if-.patch patches.suse/pinctrl-rockchip-fix-memleak-in-rockchip_dt_node_to_.patch patches.suse/pinctrl-cherryview-Re-use-data-structures-from-pinct.patch patches.suse/pinctrl-cherryview-Use-GENMASK-consistently.patch @@ -36607,6 +36633,7 @@ patches.suse/i2c-also-convert-placeholder-function-to-return-errn.patch patches.suse/i2c-slave-improve-sanity-check-when-registering.patch patches.suse/i2c-slave-add-sanity-check-when-unregistering.patch + patches.suse/net-mscc-ocelot-fix-hardware-timestamp-dequeue-logic.patch patches.suse/net-hns3-fix-desc-filling-bug-when-skb-is-expanded-o.patch patches.suse/net-hns3-fix-a-TX-timeout-issue.patch patches.suse/net-hns3-add-reset-check-for-VF-updating-port-based-.patch @@ -41625,7 +41652,9 @@ patches.suse/pinctrl-single-fix-pcs_parse_pinconf-return-value.patch patches.suse/pinctrl-single-fix-function-name-in-documentation.patch patches.suse/pinctrl-ingenic-Enhance-support-for-IRQ_TYPE_EDGE_BO.patch + patches.suse/pinctrl-pinctrl-rockchip-Fix-a-bunch-of-kerneldoc-mi.patch patches.suse/pinctrl-tegra-pinctrl-tegra194-Do-not-initialise-fie.patch + patches.suse/pinctrl-rockchip-Replace-HTTP-links-with-HTTPS-ones.patch patches.suse/pinctrl-cherryview-Introduce-chv_readl-helper.patch patches.suse/pinctrl-cherryview-Introduce-helpers-to-IO-with-comm.patch patches.suse/pinctrl-cherryview-Convert-chv_writel-to-use-chv_pad.patch @@ -42127,6 +42156,7 @@ patches.suse/mm-page_alloc-fix-core-hung-in-free_pcppages_bulk.patch patches.suse/of-address-check-for-invalid-range-cpu_addr.patch patches.suse/scsi-fcoe-Fix-I-O-path-allocation.patch + patches.suse/scsi-ufs-pci-Add-quirk-for-broken-auto-hibernate-for-Intel-EHL patches.suse/scsi-zfcp-fix-use-after-free-in-request-timeout-handlers patches.suse/scsi-qla2xxx-Use-MBX_TOV_SECONDS-for-mailbox-command.patch patches.suse/scsi-qla2xxx-Flush-all-sessions-on-zone-disable.patch @@ -43975,6 +44005,7 @@ patches.suse/drm-i915-Configure-GEN11_-TBT-TC-_HOTPLUG_CTL-for-po.patch patches.suse/drm-i915-Move-hpd_pin-setup-to-encoder-init.patch patches.suse/drm-i915-Introduce-HPD_PORT_TC-n.patch + patches.suse/drm-i915-Introduce-intel_hpd_hotplug_irqs.patch patches.suse/drm-amd-display-Check-clock-table-return.patch patches.suse/drm-amdgpu-No-sysfs-not-an-error-condition.patch patches.suse/drm-amd-display-Delete-duplicated-argument-to-or.patch @@ -45703,6 +45734,8 @@ patches.suse/gpio-pcie-idio-24-Fix-irq-mask-when-masking.patch patches.suse/gpio-pcie-idio-24-Fix-IRQ-Enable-Register-value.patch patches.suse/gpio-pcie-idio-24-Enable-PEX8311-interrupts.patch + patches.suse/pinctrl-rockchip-enable-gpio-pclk-for-rockchip_gpio_.patch + patches.suse/pinctrl-rockchip-create-irq-mapping-in-gpio_to_irq.patch patches.suse/pinctrl-aspeed-Fix-GPI-only-function-problem.patch patches.suse/pinctrl-amd-fix-incorrect-way-to-disable-debounce-fi.patch patches.suse/pinctrl-amd-use-higher-precision-for-512-RtcClk.patch @@ -46908,6 +46941,7 @@ patches.suse/bitmap-remove-unused-function-declaration.patch patches.suse/lib-string-remove-unnecessary-undefs.patch patches.suse/apparmor-remove-duplicate-macro-list_entry_is_head.patch + patches.suse/printk-console-Allow-to-disable-console-output-by-us.patch patches.suse/selinux-fix-error-initialization-in-inode_doinit_wit.patch patches.suse/selinux-fix-inode_doinit_with_dentry-LABEL_INVALID-e.patch patches.suse/gcc-plugins-simplify-GCC-plugin-dev-capability-test.patch @@ -47527,6 +47561,7 @@ patches.suse/mlxsw-core-Add-validation-of-transceiver-temperature.patch patches.suse/mlxsw-core-Increase-critical-threshold-for-ASIC-ther.patch patches.suse/net-mvpp2-Remove-Pause-and-Asym_Pause-support.patch + patches.suse/rndis_host-set-proper-input-size-for-OID_GEN_PHYSICA.patch patches.suse/r8152-Add-Lenovo-Powered-USB-C-Travel-Hub.patch patches.suse/bnxt_en-Improve-stats-context-resource-accounting-wi.patch patches.suse/smc-fix-out-of-bound-access-in-smc_nl_get_sys_info @@ -48602,6 +48637,7 @@ patches.suse/can-flexcan-invoke-flexcan_chip_freeze-to-enter-free.patch patches.suse/can-skb-can_skb_set_owner-fix-ref-counting-if-socket.patch patches.suse/ibmvnic-Fix-possibly-uninitialized-old_num_tx_queues.patch + patches.suse/Revert-r8152-adjust-the-settings-about-MAC-clock-spe.patch patches.suse/ixgbe-fail-to-create-xfrm-offload-of-IPsec-tunnel-mo.patch patches.suse/net-usb-qmi_wwan-allow-qmimux-add-del-with-master-up.patch patches.suse/netdevsim-init-u64-stats-for-32bit-hardware.patch @@ -48888,6 +48924,7 @@ patches.suse/netfilter-nftables-allow-to-update-flowtable-flags.patch patches.suse/netfilter-flowtable-Make-sure-GC-works-periodically-.patch patches.suse/net-cdc-phonet-fix-data-interface-release-on-probe-f.patch + patches.suse/r8152-limit-the-RX-buffer-size-of-RTL8153A-for-USB-2.patch patches.suse/e1000e-Fix-duplicate-include-guard.patch patches.suse/igb-Fix-duplicate-include-guard.patch patches.suse/igb-check-timestamp-validity.patch @@ -48917,6 +48954,7 @@ patches.suse/ACPICA-Always-create-namespace-nodes-using-acpi_ns_c.patch patches.suse/ACPI-video-Add-missing-callback-back-for-Sony-VPCEH3.patch patches.suse/0002-dm-verity-fix-DM_VERITY_OPTS_MAX-value.patch + patches.suse/dm-ioctl-fix-out-of-bounds-array-access-when-no-devi.patch patches.suse/scsi-ibmvfc-Fix-potential-race-in-ibmvfc_wait_for_op.patch patches.suse/scsi-ibmvfc-Make-ibmvfc_wait_for_ops-MQ-aware.patch patches.suse/scsi-qedi-Fix-error-return-code-of-qedi_alloc_global_queues @@ -49806,9 +49844,13 @@ patches.suse/i2c-mlxbf-add-IRQ-check.patch patches.suse/i2c-sh7760-add-IRQ-check.patch patches.suse/i2c-sh7760-fix-IRQ-error-path.patch + patches.suse/pinctrl-rockchip-clear-int-status-when-driver-probed.patch + patches.suse/pinctrl-rockchip-make-driver-be-tristate-module.patch + patches.suse/pinctrl-rockchip-add-support-for-rk3568.patch patches.suse/pinctrl-samsung-use-int-for-register-masks-in-Exynos.patch patches.suse/pinctrl-Ingenic-Add-missing-pins-to-the-JZ4770-MAC-M.patch patches.suse/pinctrl-core-Fix-kernel-doc-string-for-pin_get_name.patch + patches.suse/pinctrl-rockchip-do-coding-style-for-mux-route-struc.patch patches.suse/watchdog-rename-__touch_watchdog-to-a-better-descrip.patch patches.suse/watchdog-explicitly-update-timestamp-when-reporting-.patch patches.suse/watchdog-softlockup-report-the-overall-time-of-softl.patch @@ -50004,6 +50046,7 @@ patches.suse/cdrom-gdrom-deallocate-struct-gdrom_unit-fields-in-r.patch patches.suse/Revert-char-hpet-fix-a-missing-check-of-ioremap.patch patches.suse/char-hpet-add-checks-after-calling-ioremap.patch + patches.suse/Revert-scsi-ufs-fix-a-missing-check-of-devm_reset_control_get patches.suse/Revert-video-hgafb-fix-potential-NULL-pointer-derefe.patch patches.suse/video-hgafb-fix-potential-NULL-pointer-dereference.patch patches.suse/Revert-isdn-mISDNinfineon-fix-potential-NULL-pointer.patch @@ -50052,6 +50095,7 @@ patches.suse/ALSA-intel8x0-Don-t-update-period-unless-prepared.patch patches.suse/ALSA-dice-fix-stream-format-for-TC-Electronic-Konnek.patch patches.suse/ALSA-line6-Fix-racy-initialization-of-LINE6-MIDI.patch + patches.suse/scsi-qedf-Add-pointer-checks-in-qedf_update_link_speed patches.suse/scsi-qla2xxx-Fix-error-return-code-in-qla82xx_write_.patch patches.suse/firmware-arm_scpi-Prevent-the-ternary-sign-expansion.patch patches.suse/drm-i915-gt-Disable-HiZ-Raw-Stall-Optimization-on-br.patch @@ -50068,6 +50112,7 @@ patches.suse/gpio-cadence-Add-missing-MODULE_DEVICE_TABLE.patch patches.suse/gpio-xilinx-Correct-kernel-doc-for-xgpio_probe.patch patches.suse/cifs-fix-memory-leak-in-smb2_copychunk_range.patch + patches.suse/x86-Xen-swap-NX-determination-and-GDT-setup-on-BSP.patch patches.suse/xen-pciback-redo-VF-placement-in-the-virtual-topolog.patch patches.suse/xen-pciback-reconfigure-also-from-backend-watch-hand.patch patches.suse/nvme-tcp-rerun-io_work-if-req_list-is-not-empty.patch @@ -50102,6 +50147,8 @@ patches.suse/bpf-Fix-alu32-const-subreg-bound-tracking-on-bitwise.patch patches.suse/bpf-ringbuf-Deny-reserve-of-buffers-larger-than-ring.patch patches.suse/bpf-Prevent-writable-memory-mapping-of-read-only-rin.patch + patches.suse/bpf-kconfig-Add-consolidated-menu-entry-for-bpf-with.patch + patches.suse/bpf-Add-kconfig-knob-for-disabling-unpriv-bpf-by-def.patch patches.suse/chelsio-chtls-unlock-on-error-in-chtls_pt_recvmsg.patch patches.suse/cxgb4-ch_ktls-Clear-resources-when-pf4-device-is-rem.patch patches.suse/netfilter-nft_set_pipapo_avx2-Add-irq_fpu_usable-che.patch @@ -50128,6 +50175,7 @@ patches.suse/net-sched-fq_pie-fix-OOB-access-in-the-traffic-path.patch patches.suse/net-usb-fix-memory-leak-in-smsc75xx_bind.patch patches.suse/net-zero-initialize-tc-skb-extension-on-allocation.patch + patches.suse/bpf-Fix-BPF_JIT-kconfig-symbol-dependency.patch patches.suse/bpftool-Add-sock_release-help-info-for-cgroup-attach.patch patches.suse/bpf-Wrap-aux-data-inside-bpf_sanitize_info-container.patch patches.suse/bpf-Fix-mask-direction-swap-upon-off-reg-sign-change.patch @@ -50174,6 +50222,7 @@ patches.suse/s390-dasd-add-missing-discipline-function patches.suse/nvme-fc-short-circuit-reconnect-retries.patch patches.suse/nvme-fabrics-decode-host-pathing-error-for-connect.patch + patches.suse/scsi-libsas-Use-_safe-loop-in-sas_resume_port patches.suse/scsi-target-qla2xxx-Wait-for-stop_phase1-at-WWN-remo.patch patches.suse/USB-usbfs-Don-t-WARN-about-excessively-large-memory-.patch patches.suse/usb-dwc3-gadget-Properly-track-pending-and-queued-SG.patch @@ -50369,6 +50418,7 @@ patches.suse/mlxsw-reg-Spectrum-3-Enforce-lowest-max-shaper-burst.patch patches.suse/vrf-fix-maximum-MTU.patch patches.suse/batman-adv-Avoid-WARN_ON-timing-related-checks.patch + patches.suse/net-dsa-felix-re-enable-TX-flow-control-in-ocelot_po.patch patches.suse/mac80211-remove-warning-in-ieee80211_get_sband.patch patches.suse/mac80211_hwsim-drop-pending-frames-on-stop.patch patches.suse/cfg80211-call-cfg80211_leave_ocb-when-switching-away.patch @@ -50444,6 +50494,7 @@ patches.suse/kthread-prevent-deadlock-when-kthread_mod_delayed_wo.patch patches.suse/mm-futex-fix-shared-futex-pgoff-on-shmem-huge-page.patch patches.suse/pinctrl-stm32-fix-the-reported-number-of-GPIO-lines-.patch + patches.suse/s390-topology-clear-thread-group-maps-for-offline-cpus patches.suse/s390-stack-fix-possible-register-corruption-with-stack-switch-helper.patch patches.suse/ata-ahci_sunxi-Disable-DIPM.patch patches.suse/ahci-Add-support-for-Dell-S140-and-later.patch @@ -50818,6 +50869,7 @@ patches.suse/iommu-dma-fix-compile-warning-in-32-bit-builds patches.suse/xfs-fix-log-intent-recovery-ENOSPC-shutdowns-when-in.patch patches.suse/scsi-lpfc-Remove-redundant-assignment-to-pointer-tem.patch + patches.suse/scsi-snic-Fix-an-error-message patches.suse/scsi-ibmvfc-Handle-move-login-failure.patch patches.suse/scsi-ibmvfc-Avoid-move-login-if-fast-fail-is-enabled.patch patches.suse/scsi-ibmvfc-Reinit-target-retries.patch @@ -50835,6 +50887,7 @@ patches.suse/scsi-lpfc-Reregister-FPIN-types-if-ELS_RDF-is-receiv.patch patches.suse/scsi-lpfc-Update-lpfc-version-to-12.8.0.10.patch patches.suse/scsi-qla2xxx-Log-PCI-address-in-qla_nvme_unregister_.patch + patches.suse/scsi-FlashPoint-Rename-si_flags-field patches.suse/scsi-mpi3mr-Add-mpi30-Rev-R-headers-and-Kconfig patches.suse/scsi-mpi3mr-Base-driver-code patches.suse/scsi-mpi3mr-Create-operational-request-and-reply-queue-pair @@ -50877,6 +50930,7 @@ patches.suse/scsi-qla2xxx-Use-list_move_tail-instead-of-list_del-.patch patches.suse/scsi-mpi3mr-Fix-missing-unlock-on-error patches.suse/scsi-mpi3mr-Fix-error-return-code-in-mpi3mr_init_ioc + patches.suse/scsi-mpt3sas-Fix-error-return-value-in-_scsih_expander_add patches.suse/scsi-lpfc-Fix-build-error-in-lpfc_scsi.c.patch patches.suse/ALSA-usx2y-Avoid-camelCase.patch patches.suse/ALSA-usx2y-Don-t-call-free_pages_exact-with-NULL-add.patch @@ -51120,6 +51174,7 @@ patches.suse/rtc-stm32-Fix-unbalanced-clk_disable_unprepare-on-pr.patch patches.suse/rtc-pcf2127-handle-timestamp-interrupts.patch patches.suse/scsi-qla2xxx-Add-heartbeat-check.patch + patches.suse/scsi-be2iscsi-Fix-an-error-handling-path-in-beiscsi_dev_probe patches.suse/scsi-libfc-Fix-array-index-out-of-bound-exception.patch patches.suse/btrfs-fix-deadlock-with-concurrent-chunk-allocations.patch patches.suse/btrfs-rework-chunk-allocation-to-avoid-exhaustion-of.patch @@ -51152,6 +51207,7 @@ patches.suse/bonding-Add-struct-bond_ipesc-to-manage-SA.patch patches.suse/bonding-fix-suspicious-RCU-usage-in-bond_ipsec_offlo.patch patches.suse/bonding-fix-incorrect-return-value-of-bond_ipsec_off.patch + patches.suse/stmmac-platform-Fix-signedness-bug-in-stmmac_probe_c.patch patches.suse/netfilter-conntrack-do-not-renew-entry-stuck-in-tcp-.patch patches.suse/netfilter-ctnetlink-suspicious-RCU-usage-in-ctnetlin.patch patches.suse/0001-netfilter-conntrack-improve-RST-handling-when-tuple-.patch @@ -51228,6 +51284,7 @@ patches.suse/rbd-don-t-hold-lock_rwsem-while-running_list-is-being-drained.patch patches.suse/ceph-don-t-warn-if-we-re-still-opening-a-session-to-an-mds.patch patches.suse/nvme-fix-refcounting-imbalance-when-all-paths-are-do.patch + patches.suse/scsi-iscsi-Fix-iface-sysfs-attr-detection patches.suse/ACPI-fix-NULL-pointer-dereference.patch patches.suse/efi-tpm-Differentiate-missing-and-invalid-final-even.patch patches.suse/firmware-efi-Tell-memblock-about-EFI-iomem-reservati.patch @@ -51321,6 +51378,7 @@ patches.suse/soc-ixp4xx-qmgr-fix-invalid-__iomem-access.patch patches.suse/Revert-ACPICA-Fix-memory-leak-caused-by-_CID-repair-.patch patches.suse/ext4-fix-potential-htree-corruption-when-growing-lar.patch + patches.suse/s390-dasd-fix-use-after-free-in-dasd-path-handling patches.suse/0007-md-raid10-properly-indicate-failure-when-ending-a-fa.patch patches.suse/blk-iolatency-error-out-if-blk_get_queue-failed-in-i.patch patches.suse/USB-usbtmc-Fix-RCU-stall-warning.patch @@ -51370,6 +51428,7 @@ patches.suse/netfilter-conntrack-collect-all-entries-in-one-cycle.patch patches.suse/bpf-Fix-integer-overflow-involving-bucket_size.patch patches.suse/net-ethernet-ti-cpsw-fix-min-eth-packet-size-for-non.patch + patches.suse/net-smc-Correct-smc-link-connection-counter-in-case-of-smc-client patches.suse/bareudp-Fix-invalid-read-beyond-skb-s-linear-data.patch patches.suse/ice-Prevent-probing-virtual-functions.patch patches.suse/ice-don-t-remove-netdev-dev_addr-from-uc-sync-list.patch @@ -51429,6 +51488,7 @@ patches.suse/drm-Copy-drm_wait_vblank-to-user-before-returning.patch patches.suse/drm-nouveau-disp-power-down-unused-DP-links-during-i.patch patches.suse/drm-nouveau-kms-nv50-workaround-EFI-GOP-window-chann.patch + patches.suse/s390-pci-fix-use-after-free-of-zpci_dev patches.suse/slimbus-messaging-start-transaction-ids-from-1-inste.patch patches.suse/slimbus-messaging-check-for-valid-transaction-id.patch patches.suse/slimbus-ngd-reset-dma-setup-during-runtime-pm.patch @@ -51440,6 +51500,8 @@ patches.suse/e1000e-Fix-the-max-snoop-no-snoop-latency-for-10M.patch patches.suse/net-sched-ets-fix-crash-when-flipping-from-strict-to.patch patches.suse/can-usb-esd_usb2-esd_usb2_rx_event-fix-the-interchan.patch + patches.suse/ipv6-use-siphash-in-rt6_exception_hash.patch + patches.suse/ipv4-use-siphash-instead-of-jenkins-in-fnhe_hashfun.patch patches.suse/cxgb4-dont-touch-blocked-freelist-bitmap-after-free.patch patches.suse/bpf-Fix-ringbuf-helper-function-compatibility.patch patches.suse/drm-i915-Fix-syncmap-memory-leak.patch @@ -51468,6 +51530,14 @@ patches.suse/crypto-qat-use-proper-type-for-vf_mask.patch patches.suse/edac-mce_amd-do-not-load-edac_mce_amd-module-on-guests.patch patches.suse/edac-i10nm-fix-nvdimm-detection.patch + patches.suse/pinctrl-rockchip-always-enable-clock-for-gpio-contro.patch + patches.suse/pinctrl-rockchip-separate-struct-rockchip_pin_bank-t.patch + patches.suse/pinctrl-rockchip-add-pinctrl-device-to-gpio-bank-str.patch + patches.suse/gpio-rockchip-add-driver-for-rockchip-gpio.patch + patches.suse/gpio-rockchip-use-struct-rockchip_gpio_regs-for-gpio.patch + patches.suse/gpio-rockchip-support-next-version-gpio-controller.patch + patches.suse/gpio-rockchip-drop-irq_gc_lock-irq_gc_unlock-for-irq.patch + patches.suse/pinctrl-rockchip-drop-the-gpio-related-codes.patch patches.suse/x86-reboot-limit-dell-optiplex-990-quirk-to-early-bios-versions.patch patches.suse/block-bfq-fix-bfq_set_next_ioprio_data.patch patches.suse/params-lift-param_set_uint_minmax-to-common-code.patch @@ -51543,6 +51613,8 @@ patches.suse/iwlwifi-skip-first-element-in-the-WTAS-ACPI-table.patch patches.suse/bcma-Fix-memory-leak-for-internally-handled-cores.patch patches.suse/brcmfmac-pcie-fix-oops-on-failure-to-resume-and-repr.patch + patches.suse/ipv6-make-exception-cache-less-predictible.patch + patches.suse/ipv4-make-exception-cache-less-predictible.patch patches.suse/ice-Only-lock-to-update-netdev-dev_addr.patch patches.suse/fpga-altera-freeze-bridge-Address-warning-about-unus.patch patches.suse/fpga-xiilnx-spi-Address-warning-about-unused-variabl.patch @@ -51714,8 +51786,10 @@ patches.suse/scsi-qla2xxx-Update-version-to-10.02.00.107-k.patch patches.suse/scsi-qla2xxx-Fix-spelling-mistakes-allloc-alloc.patch patches.suse/scsi-lpfc-Fix-possible-ABBA-deadlock-in-nvmet_xri_ab.patch + patches.suse/scsi-BusLogic-Fix-missing-pr_cont-use patches.suse/scsi-qla2xxx-Fix-use-after-free-in-debug-code.patch patches.suse/scsi-qla2xxx-Remove-redundant-initialization-of-vari.patch + patches.suse/scsi-fdomain-Fix-error-return-code-in-fdomain_probe patches.suse/scsi-core-Introduce-the-scsi_cmd_to_rq-function.patch patches.suse/scsi-lpfc-Use-scsi_cmd_to_rq-instead-of-scsi_cmnd.re.patch patches.suse/scsi-mpi3mr-Use-scsi_cmd_to_rq-instead-of-scsi_cmnd.request @@ -51735,6 +51809,9 @@ patches.suse/scsi-qla2xxx-Sync-queue-idx-with-queue_pair_map-idx.patch patches.suse/scsi-qla2xxx-Update-version-to-10.02.06.100-k.patch patches.suse/scsi-mpi3mr-Use-the-proper-SCSI-midlayer-interfaces-for-PI + patches.suse/scsi-smartpqi-Fix-an-error-code-in-pqi_get_raid_map + patches.suse/scsi-qedi-Fix-error-codes-in-qedi_alloc_global_queues + patches.suse/scsi-qedf-Fix-error-codes-in-qedf_alloc_global_queues patches.suse/scsi-ibmvfc-Do-not-wait-for-initial-device-scan.patch patches.suse/scsi-qla2xxx-edif-Fix-stale-session.patch patches.suse/scsi-qla2xxx-edif-Reject-AUTH-ELS-on-session-down.patch @@ -51804,6 +51881,7 @@ patches.suse/fuse-truncate-pagecache-on-atomic_o_trunc.patch patches.suse/fuse-flush-extending-writes.patch patches.suse/gpio-mpc8xxx-Fix-a-resources-leak-in-the-error-handl.patch + patches.suse/gpio-mpc8xxx-Use-devm_gpiochip_add_data-to-simplify-.patch patches.suse/mfd-axp20x-Update-AXP288-volatile-ranges.patch patches.suse/mfd-Don-t-use-irq_create_mapping-to-resolve-a-mappin.patch patches.suse/mfd-tqmx86-Clear-GPIO-IRQ-resource-when-no-IRQ-is-se.patch @@ -51832,6 +51910,7 @@ patches.suse/PCI-xilinx-nwl-Enable-the-clock-through-CCF.patch patches.suse/ipc-replace-costly-bailout-check-in-sysvipc_find_ipc.patch patches.suse/SUNRPC-improve-error-response-to-over-size-gss-crede.patch + patches.suse/mm-hugetlb-initialize-hugetlb_usage-in-mm_init.patch patches.suse/dmaengine-sprd-Add-missing-MODULE_DEVICE_TABLE.patch patches.suse/dmaengine-idxd-fix-wq-slot-allocation-index-check.patch patches.suse/dmaengine-idxd-clear-block-on-fault-flag-when-clear-.patch @@ -51868,6 +51947,7 @@ patches.suse/bnxt_en-make-bnxt_free_skbs-safe-to-call-after-bnxt_.patch patches.suse/PM-base-power-don-t-try-to-use-non-existing-RTC-for-.patch patches.suse/xen-reset-legacy-rtc-flag-for-PV-domU.patch + patches.suse/swiotlb-xen-avoid-double-free.patch patches.suse/nvme-avoid-race-in-shutdown-namespace-removal.patch patches.suse/PCI-Add-AMD-GPU-multi-function-power-dependencies.patch patches.suse/spi-Fix-tegra20-build-with-CONFIG_PM-n.patch @@ -51879,9 +51959,15 @@ patches.suse/net-mlx4_en-Resolve-bad-operstate-value.patch patches.suse/bnxt_en-Fix-TX-timeout-when-TX-ring-size-is-set-to-t.patch patches.suse/net-hns3-check-queue-id-range-before-using.patch + patches.suse/net-smc-fix-workqueue-leaked-lock-in-smc_conn_abort_work + patches.suse/s390-qeth-fix-NULL-deref-in-qeth_clear_working_pool_list + patches.suse/s390-qeth-Fix-deadlock-in-remove_discipline + patches.suse/s390-qeth-fix-deadlock-during-failing-recovery patches.suse/qed-rdma-don-t-wait-for-resources-under-hw-error-rec.patch patches.suse/net-mlx4_en-Don-t-allow-aRFS-for-encapsulated-packet.patch patches.suse/gpio-uniphier-Fix-void-functions-to-remove-return-va.patch + patches.suse/gpio-rockchip-extended-debounce-support-is-only-avai.patch + patches.suse/gpio-rockchip-fix-get_direction-value-handling.patch patches.suse/usb-gadget-r8a66597-fix-a-loop-in-set_feature.patch patches.suse/USB-cdc-acm-fix-minor-number-release.patch patches.suse/usb-dwc2-gadget-Fix-ISOC-flow-for-BDMA-and-Slave.patch @@ -51897,6 +51983,7 @@ patches.suse/fpga-machxo2-spi-Return-an-error-on-failure.patch patches.suse/fpga-machxo2-spi-Fix-missing-error-code-in-machxo2_w.patch patches.suse/erofs-fix-up-erofs_lookup-tracepoint.patch + patches.suse/xen-x86-fix-PV-trap-handling-on-secondary-processors.patch patches.suse/nvme-fc-update-hardware-queues-before-using-them.patch patches.suse/nvme-fc-avoid-race-between-time-out-and-tear-down.patch patches.suse/nvme-fc-remove-freeze-unfreeze-around-update_nr_hw_q.patch @@ -51918,6 +52005,9 @@ patches.suse/HID-u2fzero-ignore-incomplete-packets-without-data.patch patches.suse/watchdog-sb_watchdog-fix-compilation-problem-due-to-.patch patches.suse/media-cedrus-Fix-SUNXI-tile-size-calculation.patch + patches.suse/pinctrl-rockchip-add-a-queue-for-deferred-pin-output.patch + patches.suse/gpio-rockchip-fetch-deferred-output-settings-on-prob.patch + patches.suse/crypto_ccp-fix_resource_leaks_in_ccp_run_aes_gcm_cmd.patch patches.suse/ALSA-hda-realtek-Quirks-to-enable-speaker-output-for.patch patches.suse/ASoC-Intel-sof_sdw-tag-SoundWire-BEs-as-non-atomic.patch patches.suse/ASoC-mediatek-common-handle-NULL-case-in-suspend-res.patch @@ -51947,6 +52037,7 @@ patches.suse/ACPI-NFIT-Use-fallback-node-id-when-numa-info-in-NFI.patch patches.suse/nvme-add-command-id-quirk-for-apple-controllers.patch patches.suse/scsi-qla2xxx-Fix-excessive-messages-during-device-lo.patch + patches.suse/scsi-csiostor-Add-module-softdep-on-cxgb4 patches.suse/hwmon-mlxreg-fan-Return-non-zero-value-when-fan-curr.patch patches.suse/hwmon-tmp421-report-PVLD-condition-as-fault.patch patches.suse/hwmon-tmp421-fix-rounding-for-negative-values.patch @@ -51975,6 +52066,8 @@ patches.suse/drm-nouveau-debugfs-fix-file-release-memory-leak.patch patches.suse/mmc-meson-gx-do-not-use-memcpy_to-fromio-for-dram-ac.patch patches.suse/usb-chipidea-ci_hdrc_imx-Also-search-for-phys-phandl.patch + patches.suse/xen-privcmd-fix-error-handling-in-mmap-resource-proc.patch + patches.suse/s390-pci-fix-zpci_zdev_put-on-reserve patches.suse/scsi-lpfc-Fix-memory-overwrite-during-FC-GS-I-O-abor.patch patches.suse/i2c-acpi-fix-resource-leak-in-reconfiguration-device.patch patches.suse/x86-sev-return-an-error-on-a-returned-non-zero-sw_exitinfo1.patch @@ -51999,6 +52092,7 @@ patches.suse/ALSA-hda-realtek-Add-quirk-for-Clevo-X170KM-G.patch patches.suse/ALSA-hda-realtek-ALC236-headset-MIC-recording-issue.patch patches.suse/ALSA-hda-realtek-Add-quirk-for-TongFang-PHxTxX1.patch + patches.suse/ALSA-hda-intel-Allow-repeatedly-probing-on-codec-con.patch patches.suse/ALSA-hda-realtek-Fix-for-quirk-to-enable-speaker-out.patch patches.suse/ALSA-pcm-Workaround-for-a-wrong-offset-in-SYNC_PTR-c.patch patches.suse/ALSA-hda-realtek-Fix-the-mic-type-detection-issue-fo.patch @@ -52010,6 +52104,7 @@ patches.suse/ionic-don-t-remove-netdev-dev_addr-when-syncing-uc-l.patch patches.suse/isdn-mISDN-Fix-sleeping-function-called-from-invalid.patch patches.suse/qed-Fix-missing-error-code-in-qed_slowpath_start.patch + patches.suse/net-mscc-ocelot-warn-when-a-PTP-IRQ-is-raised-for-an.patch patches.suse/net-mlx5e-Mutually-exclude-RX-FCS-and-RX-port-timest.patch patches.suse/nfc-fix-error-handling-of-nfc_proto_register.patch patches.suse/NFC-digital-fix-possible-memory-leak-in-digital_tg_l.patch @@ -52066,10 +52161,12 @@ patches.suse/can-peak_pci-peak_pci_remove-fix-UAF.patch patches.suse/can-peak_usb-pcan_usb_fd_decode_status-fix-back-to-E.patch patches.suse/net-hns3-fix-vf-reset-workqueue-cannot-exit.patch + patches.suse/e1000e-Separate-TGP-board-type-from-SPT.patch patches.suse/e1000e-Fix-packet-loss-on-Tiger-Lake-and-later.patch patches.suse/ice-Add-missing-E810-device-ids.patch patches.suse/netfilter-xt_IDLETIMER-fix-panic-that-occurs-when-ti.patch patches.suse/usbnet-sanity-check-for-maxpacket.patch + patches.suse/scsi-qla2xxx-Fix-a-memory-leak-in-an-error-path-of-qla2x00_process_els patches.suse/ata-sata_mv-Fix-the-error-handling-of-mv_chip_id.patch patches.suse/regmap-Fix-possible-double-free-in-regcache_rbtree_e.patch patches.suse/cfg80211-scan-fix-RCU-in-cfg80211_add_nontrans_list.patch @@ -52092,6 +52189,11 @@ patches.suse/mmc-vub300-fix-control-message-timeouts.patch patches.suse/scsi-ibmvfc-Fix-up-duplicate-response-detection.patch patches.suse/tpm-Check-for-integer-overflow-in-tpm2_map_response_.patch + patches.suse/btrfs-fix-deadlock-between-chunk-allocation-and-chun.patch + patches.suse/btrfs-update-comments-for-chunk-allocation-ENOSPC-ca.patch + patches.suse/x86-xen-Mark-cpu_bringup_and_idle-as-dead_end_functi.patch + patches.suse/edac-sb_edac-fix-top-of-high-memory-value-for-broadwell-haswell.patch + patches.suse/x86-sme-use-define-use_early_pgtable_l5-in-mem_encrypt_identity-c.patch patches.suse/firmware-psci-fix-application-of-sizeof-to-pointer.patch patches.suse/media-em28xx-add-missing-em28xx_close_extension.patch patches.suse/media-cxd2880-spi-Fix-a-null-pointer-dereference-on-.patch @@ -52099,6 +52201,7 @@ patches.suse/media-staging-intel-ipu3-css-Fix-wrong-size-comparis.patch patches.suse/media-v4l2-ioctl-Fix-check_ext_ctrls.patch patches.suse/media-v4l2-ioctl-S_CTRL-output-the-right-value.patch + patches.suse/media-firewire-firedtv-avc-fix-a-buffer-overflow-in-.patch patches.suse/media-TDA1997x-handle-short-reads-of-hdmi-info-frame.patch patches.suse/media-mtk-vpu-Fix-a-resource-leak-in-the-error-handl.patch patches.suse/media-i2c-ths8200-needs-V4L2_ASYNC.patch @@ -52120,10 +52223,13 @@ patches.suse/hwmon-Fix-possible-memleak-in-__hwmon_device_registe.patch patches.suse/hwmon-pmbus-lm25066-Add-offset-coefficients.patch patches.suse/hwmon-pmbus-lm25066-Let-compiler-determine-outer-dim.patch + patches.suse/tracing-use-ps-format-string-to-print-symbols.patch + patches.suse/tracing-Increase-PERF_MAX_TRACE_SIZE-to-handle-Senti.patch patches.suse/crypto-caam-disable-pkc-for-non-E-SoCs.patch patches.suse/crypto-qat-detect-PFVF-collision-after-ACK.patch patches.suse/crypto-qat-disregard-spurious-PFVF-interrupts.patch patches.suse/hwrng-mtk-Force-runtime-pm-ops-for-sleep-ops.patch + patches.suse/crypto-pcrypt-Delay-write-to-padata-info.patch patches.suse/ibmvnic-Consolidate-code-in-replenish_rx_pool.patch patches.suse/ibmvnic-Fix-up-some-comments-and-messages.patch patches.suse/ibmvnic-Use-rename-local-vars-in-init_rx_pools.patch @@ -52133,6 +52239,7 @@ patches.suse/ibmvnic-Reuse-LTB-when-possible.patch patches.suse/ibmvnic-Reuse-rx-pools-when-possible.patch patches.suse/ibmvnic-Reuse-tx-pools-when-possible.patch + patches.suse/Bluetooth-sco-Fix-lock_sock-blockage-by-memcpy_from_.patch patches.suse/Bluetooth-fix-init-and-cleanup-of-sco_conn.timeout_w.patch patches.suse/Bluetooth-btmtkuart-fix-a-memleak-in-mtk_hci_wmt_syn.patch patches.suse/rsi-Fix-module-dev_oper_mode-parameter-description.patch @@ -52162,9 +52269,11 @@ patches.suse/rsi-fix-control-message-timeout.patch patches.suse/mwifiex-fix-division-by-zero-in-fw-download-path.patch patches.suse/iwlwifi-mvm-fix-some-kerneldoc-issues.patch + patches.suse/bpf-Disallow-unprivileged-bpf-by-default.patch patches.suse/ibmvnic-don-t-stop-queue-in-xmit.patch patches.suse/ibmvnic-Process-crqs-after-enabling-interrupts.patch patches.suse/ibmvnic-delay-complete.patch + patches.suse/Revert-x86-kvm-fix-vcpu-id-indexed-array-sizes.patch patches.suse/PM-sleep-Do-not-let-syscore-devices-runtime-suspend-.patch patches.suse/drm-sun4i-Fix-macros-in-sun8i_csc.h.patch patches.suse/drm-v3d-fix-wait-for-TMU-write-combiner-flush.patch @@ -52237,6 +52346,10 @@ patches.suse/scsi-lpfc-Zero-CGN-stats-only-during-initial-driver-.patch patches.suse/scsi-lpfc-Improve-PBDE-checks-during-SGL-processing.patch patches.suse/scsi-lpfc-Update-lpfc-version-to-14.0.0.2.patch + patches.suse/scsi-dc395-Fix-error-case-unwinding + patches.suse/scsi-core-Fix-spelling-in-a-source-code-comment + patches.suse/scsi-csiostor-Uninitialized-data-in-csio_ln_vnp_read_cbfn + patches.suse/scsi-ufs-ufshcd-pltfrm-Fix-memory-leak-due-to-probe-defer patches.suse/scsi-lpfc-Revert-LOG_TRACE_EVENT-back-to-LOG_INIT-pr.patch patches.suse/scsi-lpfc-Wait-for-successful-restart-of-SLI3-adapte.patch patches.suse/scsi-lpfc-Correct-sysfs-reporting-of-loop-support-af.patch @@ -52263,9 +52376,22 @@ patches.suse/auxdisplay-img-ascii-lcd-Fix-lock-up-when-displaying.patch patches.suse/auxdisplay-ht16k33-Connect-backlight-to-fbdev.patch patches.suse/auxdisplay-ht16k33-Fix-frame-buffer-device-blanking.patch + patches.suse/fuse-fix-page-stealing.patch + patches.suse/zram-fix-race-between-zram_reset_device-and-disksize.patch + patches.suse/zram-don-t-fail-to-remove-zram-during-unloading-modu.patch + patches.suse/zram-avoid-race-between-zram_remove-and-disksize_sto.patch + patches.suse/zram-replace-fsync_bdev-with-sync_blockdev.patch + patches.suse/xen-pciback-Fix-return-in-pm_ctrl_init.patch + patches.suse/xen-Fix-implicit-type-conversion.patch + patches.suse/Input-elantench-fix-misreporting-trackpoint-coordina.patch + patches.suse/ALSA-hda-Free-card-instance-properly-at-probe-errors.patch + patches.suse/ALSA-hda-fix-general-protection-fault-in-azx_runtime.patch + patches.suse/tracing-histogram-Do-not-copy-the-fixed-size-char-array-field-over-the-field-size.patch + patches.suse/btrfs-fix-memory-ordering-between-normal-and-ordered-work-functions.patch # out-of-tree patches patches.suse/ibmvfc-disable-MQ-channelization-by-default.patch + patches.suse/random-fix-crash-on-multiple-early-calls-to-add_bootloader_randomness.patch ######################################################## # end of sorted patches @@ -52287,24 +52413,19 @@ patches.suse/powerpc-pseries-group-lmb-operation-and-memblock-s.patch patches.suse/powerpc-pseries-update-device-tree-before-ejecting-h.patch patches.suse/rpadlpar_io-Add-MODULE_DESCRIPTION-entries-to-kernel.patch - patches.suse/ahci-Add-Intel-Emmitsburg-PCH-RAID-PCI-IDs.patch - patches.suse/block-genhd-use-atomic_t-for-disk_event-block.patch patches.suse/nxp-nci-add-NXP1002-id.patch - patches.suse/locking-rwsem-Disable-reader-optimistic-spinning.patch - patches.suse/sched-fair-Enable-SIS_AVG_CPU-by-default.patch patches.suse/qla2xxx-synchronize-rport-dev_loss_tmo-setting.patch - patches.suse/Bluetooth-sco-Fix-lock_sock-blockage-by-memcpy_from_.patch - patches.suse/crypto_ccp-fix_resource_leaks_in_ccp_run_aes_gcm_cmd.patch patches.suse/misc-sram-Only-map-reserved-areas-in-Tegra-SYSRAM.patch patches.suse/phy-tegra-xusb-Fix-dangling-pointer-on-probe-failure.patch patches.suse/NFS-change-nfs_access_get_cached-to-only-report-the-.patch patches.suse/NFS-pass-cred-explicitly-for-access-tests.patch patches.suse/NFS-don-t-store-struct-cred-in-struct-nfs_access_ent.patch - patches.suse/media-firewire-firedtv-avc-fix-a-buffer-overflow-in-.patch - - patches.suse/ALSA-hda-intel-Allow-repeatedly-probing-on-codec-con.patch + patches.suse/ALSA-usb-audio-Use-int-for-dB-map-values.patch + patches.suse/ALSA-usb-audio-Add-minimal-mute-notion-in-dB-mapping.patch + patches.suse/ALSA-usb-audio-Fix-dB-level-of-Bose-Revolve-SoundLin.patch + patches.suse/ARM-socfpga-Fix-crash-with-CONFIG_FORTIRY_SOURCE.patch ######################################################## # kbuild/module infrastructure fixes @@ -52388,13 +52509,12 @@ patches.suse/setuid-dumpable-wrongdir patches.suse/perf_timechart_fix_zero_timestamps.patch patches.suse/sched-nohz-Avoid-disabling-the-tick-for-very-short-durations.patch - - # bnc#1176588 patches.suse/sched-numa-Check-numa-balancing-information-only-when-enabled.patch patches.suse/cpuidle-Poll-for-a-minimum-of-30ns-and-poll-for-a-tick-if-lower-c-states-are-disabled.patch # bsc#1177399, bsc#1180347, bsc#1180141 patches.suse/intel_idle-Disable-ACPI-_CST-on-Haswell.patch + patches.suse/sched-fair-Enable-SIS_AVG_CPU-by-default.patch patches.suse/0001-kernel-allow-to-configure-PREEMPT_NONE-PREEMPT_VOLUN.patch @@ -52406,8 +52526,6 @@ patches.suse/0001-Reserve-64MiB-of-CMA-for-RPi3-s-VC4.patch patches.suse/mm-Warn-users-of-node-memory-hot-remove-if-the-memory-ratio-is-a-high-risk.patch - patches.suse/mm-fix-mremap-not-considering-huge-pmd-devmap.patch - ######################################################## # Filesystems ######################################################## @@ -52468,8 +52586,6 @@ patches.suse/md-raid0-fix-buffer-overflow-at-debug-print.patch +jeffm patches.suse/mdraid-fix-read-write-bytes-accounting.patch patches.suse/bfq-tune-slice-idle.patch - patches.suse/block-floppy-fix-contended-case-in-floppy_queue_rq.patch - patches.suse/genirq-add-device_has_managed_msi_irq.patch patches.suse/blk-mq-mark-if-one-queue-map-uses-managed-irq.patch patches.suse/blk-mq-don-t-deactivate-hctx-if-managed-irq-isn-t-used.patch @@ -52549,6 +52665,7 @@ ######################################################## # Other core patches ######################################################## + patches.suse/locking-rwsem-Disable-reader-optimistic-spinning.patch ######################################################## # PM @@ -52614,7 +52731,6 @@ patches.suse/target-rbd-support-COMPARE_AND_WRITE.patch patches.suse/target-rbd-detect-stripe_unit-SCSI-block-size-misali.patch patches.suse/target-disallow-emulate_legacy_capacity-with-RBD-obj.patch - patches.suse/qla2xxx-add-module_version-back-to-driver.patch patches.suse/lpfc-decouple-port_template-and-vport_template.patch patches.suse/rdma-addr-create-addr_wq-with-wq_mem_reclaim-flag.patch @@ -52669,7 +52785,6 @@ patches.suse/drm-v3d-add-support-for-bcm2711.patch patches.suse/soc-bcm-bcm2835-pm-add-support-for-bcm2711.patch - ######################################################## # Debugging ######################################################## @@ -52767,7 +52882,6 @@ patches.kabi/rq-qos-fix-missed-wake-ups-kabi.patch patches.kabi/SUNRPC-defer-slow-parts-of-rpc_free_client-to-a-work-kabi.patch patches.kabi/kABI-fix-of-usb_dcd_config_params.patch - patches.kabi/kabi-fix-after-kvm-vcpu-id-array-fix.patch patches.kabi/kabi-fix-bpf_insn_aux_data-revert-sanitize_stack_spill.patch patches.kabi/NFS-pass-cred-explicitly-for-access-tests.patch patches.kabi/scsi-fc-kABI-fixes-for-new-ELS_RDP-definition.patch diff --git a/supported.conf b/supported.conf index 06f7086..dd0074d 100644 --- a/supported.conf +++ b/supported.conf @@ -3078,6 +3078,7 @@ drivers/ptp/ptp_qoriq drivers/pwm/pwm-bcm2835 drivers/pwm/pwm-raspberrypi-poe + drivers/pwm/pwm-rockchip drivers/pwm/pwm-tegra - drivers/pwm/* - drivers/rapidio/*