From 859a9b751fa71e0573a70ff85ce82ac2263cdc77 Mon Sep 17 00:00:00 2001 From: Johannes Thumshirn Date: Aug 24 2018 12:05:51 +0000 Subject: Merge remote-tracking branch 'origin/SLE15' into SLE12-SP4 --- diff --git a/patches.drivers/ACPI-IORT-Remove-temporary-iort_get_id_mapping_index.patch b/patches.drivers/ACPI-IORT-Remove-temporary-iort_get_id_mapping_index.patch new file mode 100644 index 0000000..e0108b9 --- /dev/null +++ b/patches.drivers/ACPI-IORT-Remove-temporary-iort_get_id_mapping_index.patch @@ -0,0 +1,63 @@ +From: Lorenzo Pieralisi +Date: Thu, 8 Feb 2018 09:58:52 +0000 +Subject: ACPI/IORT: Remove temporary iort_get_id_mapping_index() ACPICA guard +Git-commit: 6c47506361ecd9591813bbaaca518f8a76162a3d +Patch-mainline: v4.17-rc1 +References: bsc#1103387 + +In IORT issue C SMMUv3 IORT nodes gained an additional field (DeviceID +mapping index) so that the SMMUv3 can describe its MSI interrupts. + +Referring to it in the kernel requires ACPICA changes and in order +to prevent kernel<->ACPICA dependencies kernel code depending on the +SMMUv3 DeviceID mapping index field was guarded with an ACPICA version +conditional. + +ACPICA changes introducing DeviceID mapping index in the IORT structs +were integrated in the kernel with: + +commit 4c106aa411ee ("ACPICA: iasl: Add SMMUv3 device ID mapping index +support") + +so the temporary ACPICA guard has become stale and can be removed. + +Signed-off-by: Lorenzo Pieralisi +Acked-by: Hanjun Guo +Cc: Will Deacon +Cc: Hanjun Guo +Cc: Sudeep Holla +Cc: Catalin Marinas +Cc: "Rafael J. Wysocki" +Signed-off-by: Matthias Brugger +--- + drivers/acpi/arm64/iort.c | 7 ------- + 1 file changed, 7 deletions(-) + +diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c +index 95255ecfae7c..a84a5787bbd2 100644 +--- a/drivers/acpi/arm64/iort.c ++++ b/drivers/acpi/arm64/iort.c +@@ -366,7 +366,6 @@ static struct acpi_iort_node *iort_node_get_id(struct acpi_iort_node *node, + return NULL; + } + +-#if (ACPI_CA_VERSION > 0x20170929) + static int iort_get_id_mapping_index(struct acpi_iort_node *node) + { + struct acpi_iort_smmu_v3 *smmu; +@@ -400,12 +399,6 @@ static int iort_get_id_mapping_index(struct acpi_iort_node *node) + return -EINVAL; + } + } +-#else +-static inline int iort_get_id_mapping_index(struct acpi_iort_node *node) +-{ +- return -EINVAL; +-} +-#endif + + static struct acpi_iort_node *iort_node_map_id(struct acpi_iort_node *node, + u32 id_in, u32 *id_out, +-- +2.18.0 + diff --git a/patches.drivers/ACPICA-iasl-Add-SMMUv3-device-ID-mapping-index-suppo.patch b/patches.drivers/ACPICA-iasl-Add-SMMUv3-device-ID-mapping-index-suppo.patch new file mode 100644 index 0000000..4a141d3 --- /dev/null +++ b/patches.drivers/ACPICA-iasl-Add-SMMUv3-device-ID-mapping-index-suppo.patch @@ -0,0 +1,41 @@ +From: Hanjun Guo +Date: Fri, 17 Nov 2017 15:42:19 -0800 +Subject: ACPICA: iasl: Add SMMUv3 device ID mapping index support +Git-commit: 4c106aa411ee7c1919589f283a4f17888dfee387 +Patch-mainline: v4.16-rc1 +References: bsc#1103387 + +ACPICA commit 5c371879e035122c5807752f42247fd091d107d6 + +SMMUv3 device ID mapping index is used for SMMUv3 +MSI which is introduced in IORT spec revision c, +add its support for iasl. + +Tested with iasl -t IORT then get the right SMMUv3 +node in iort.asl. + +Link: https://github.com/acpica/acpica/commit/5c371879 +Signed-off-by: Hanjun Guo +Signed-off-by: Bob Moore +Signed-off-by: Erik Schmauss +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Matthias Brugger +--- + include/acpi/actbl2.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h +index 2623f9d72e46..0d60d5df14f8 100644 +--- a/include/acpi/actbl2.h ++++ b/include/acpi/actbl2.h +@@ -810,6 +810,7 @@ struct acpi_iort_smmu_v3 { + u8 pxm; + u8 reserved1; + u16 reserved2; ++ u32 id_mapping_index; + }; + + /* Values for Model field above */ +-- +2.18.0 + diff --git a/patches.drivers/ixgbe-Refactor-queue-disable-logic-to-take-completio.patch b/patches.drivers/ixgbe-Refactor-queue-disable-logic-to-take-completio.patch new file mode 100644 index 0000000..3579b51 --- /dev/null +++ b/patches.drivers/ixgbe-Refactor-queue-disable-logic-to-take-completio.patch @@ -0,0 +1,401 @@ +From: Alexander Duyck +Date: Fri, 20 Jul 2018 18:29:34 -0400 +Subject: ixgbe: Refactor queue disable logic to take completion time into + account +Patch-mainline: v4.17-rc6 +Git-commit: 1918e937ca3b4270181e6f05734d5240306bd2cf +References: bsc#1101557 + +This change is meant to allow us to take completion time into account when +disabling queues. Previously we were just working with hard coded values +for how long we should wait. This worked fine for the standard case where +completion timeout was operating in the 50us to 50ms range, however on +platforms that have higher completion timeout times this was resulting in +Rx queues disable messages being displayed as we weren't waiting long +enough for outstanding Rx DMA completions. + +Signed-off-by: Alexander Duyck +Tested-by: Don Buchholz +Signed-off-by: Jeff Kirsher +Acked-by: Thomas Bogendoerfer +--- + drivers/net/ethernet/intel/ixgbe/ixgbe.h | 3 + drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c | 32 -- + drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 280 +++++++++++++++++------ + 3 files changed, 224 insertions(+), 91 deletions(-) + +--- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h ++++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h +@@ -871,7 +871,8 @@ void ixgbe_free_rx_resources(struct ixgb + void ixgbe_free_tx_resources(struct ixgbe_ring *); + void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); + void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); +-void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); ++void ixgbe_disable_rx(struct ixgbe_adapter *adapter); ++void ixgbe_disable_tx(struct ixgbe_adapter *adapter); + void ixgbe_update_stats(struct ixgbe_adapter *adapter); + int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); + bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, +--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ++++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c +@@ -1709,35 +1709,17 @@ static int ixgbe_intr_test(struct ixgbe_ + + static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) + { +- struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; +- struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; +- struct ixgbe_hw *hw = &adapter->hw; +- u32 reg_ctl; +- +- /* shut down the DMA engines now so they can be reinitialized later */ ++ /* Shut down the DMA engines now so they can be reinitialized later, ++ * since the test rings and normally used rings should overlap on ++ * queue 0 we can just use the standard disable Rx/Tx calls and they ++ * will take care of disabling the test rings for us. ++ */ + + /* first Rx */ +- hw->mac.ops.disable_rx(hw); +- ixgbe_disable_rx_queue(adapter, rx_ring); ++ ixgbe_disable_rx(adapter); + + /* now Tx */ +- reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx)); +- reg_ctl &= ~IXGBE_TXDCTL_ENABLE; +- IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl); +- +- switch (hw->mac.type) { +- case ixgbe_mac_82599EB: +- case ixgbe_mac_X540: +- case ixgbe_mac_X550: +- case ixgbe_mac_X550EM_x: +- case ixgbe_mac_x550em_a: +- reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); +- reg_ctl &= ~IXGBE_DMATXCTL_TE; +- IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl); +- break; +- default: +- break; +- } ++ ixgbe_disable_tx(adapter); + + ixgbe_reset(adapter); + +--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c ++++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +@@ -4040,38 +4040,6 @@ static void ixgbe_rx_desc_queue_enable(s + } + } + +-void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, +- struct ixgbe_ring *ring) +-{ +- struct ixgbe_hw *hw = &adapter->hw; +- int wait_loop = IXGBE_MAX_RX_DESC_POLL; +- u32 rxdctl; +- u8 reg_idx = ring->reg_idx; +- +- if (ixgbe_removed(hw->hw_addr)) +- return; +- rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); +- rxdctl &= ~IXGBE_RXDCTL_ENABLE; +- +- /* write value back with RXDCTL.ENABLE bit cleared */ +- IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); +- +- if (hw->mac.type == ixgbe_mac_82598EB && +- !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) +- return; +- +- /* the hardware may take up to 100us to really disable the rx queue */ +- do { +- udelay(10); +- rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); +- } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); +- +- if (!wait_loop) { +- e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " +- "the polling period\n", reg_idx); +- } +-} +- + void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, + struct ixgbe_ring *ring) + { +@@ -4081,9 +4049,13 @@ void ixgbe_configure_rx_ring(struct ixgb + u32 rxdctl; + u8 reg_idx = ring->reg_idx; + +- /* disable queue to avoid issues while updating state */ ++ /* disable queue to avoid use of these values while updating state */ + rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); +- ixgbe_disable_rx_queue(adapter, ring); ++ rxdctl &= ~IXGBE_RXDCTL_ENABLE; ++ ++ /* write value back with RXDCTL.ENABLE bit cleared */ ++ IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); ++ IXGBE_WRITE_FLUSH(hw); + + IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); + IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); +@@ -5647,6 +5619,212 @@ void ixgbe_up(struct ixgbe_adapter *adap + ixgbe_up_complete(adapter); + } + ++static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter) ++{ ++ u16 devctl2; ++ ++ pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2); ++ ++ switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) { ++ case IXGBE_PCIDEVCTRL2_17_34s: ++ case IXGBE_PCIDEVCTRL2_4_8s: ++ /* For now we cap the upper limit on delay to 2 seconds ++ * as we end up going up to 34 seconds of delay in worst ++ * case timeout value. ++ */ ++ case IXGBE_PCIDEVCTRL2_1_2s: ++ return 2000000ul; /* 2.0 s */ ++ case IXGBE_PCIDEVCTRL2_260_520ms: ++ return 520000ul; /* 520 ms */ ++ case IXGBE_PCIDEVCTRL2_65_130ms: ++ return 130000ul; /* 130 ms */ ++ case IXGBE_PCIDEVCTRL2_16_32ms: ++ return 32000ul; /* 32 ms */ ++ case IXGBE_PCIDEVCTRL2_1_2ms: ++ return 2000ul; /* 2 ms */ ++ case IXGBE_PCIDEVCTRL2_50_100us: ++ return 100ul; /* 100 us */ ++ case IXGBE_PCIDEVCTRL2_16_32ms_def: ++ return 32000ul; /* 32 ms */ ++ default: ++ break; ++ } ++ ++ /* We shouldn't need to hit this path, but just in case default as ++ * though completion timeout is not supported and support 32ms. ++ */ ++ return 32000ul; ++} ++ ++void ixgbe_disable_rx(struct ixgbe_adapter *adapter) ++{ ++ unsigned long wait_delay, delay_interval; ++ struct ixgbe_hw *hw = &adapter->hw; ++ int i, wait_loop; ++ u32 rxdctl; ++ ++ /* disable receives */ ++ hw->mac.ops.disable_rx(hw); ++ ++ if (ixgbe_removed(hw->hw_addr)) ++ return; ++ ++ /* disable all enabled Rx queues */ ++ for (i = 0; i < adapter->num_rx_queues; i++) { ++ struct ixgbe_ring *ring = adapter->rx_ring[i]; ++ u8 reg_idx = ring->reg_idx; ++ ++ rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); ++ rxdctl &= ~IXGBE_RXDCTL_ENABLE; ++ rxdctl |= IXGBE_RXDCTL_SWFLSH; ++ ++ /* write value back with RXDCTL.ENABLE bit cleared */ ++ IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); ++ } ++ ++ /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ ++ if (hw->mac.type == ixgbe_mac_82598EB && ++ !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) ++ return; ++ ++ /* Determine our minimum delay interval. We will increase this value ++ * with each subsequent test. This way if the device returns quickly ++ * we should spend as little time as possible waiting, however as ++ * the time increases we will wait for larger periods of time. ++ * ++ * The trick here is that we increase the interval using the ++ * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result ++ * of that wait is that it totals up to 100x whatever interval we ++ * choose. Since our minimum wait is 100us we can just divide the ++ * total timeout by 100 to get our minimum delay interval. ++ */ ++ delay_interval = ixgbe_get_completion_timeout(adapter) / 100; ++ ++ wait_loop = IXGBE_MAX_RX_DESC_POLL; ++ wait_delay = delay_interval; ++ ++ while (wait_loop--) { ++ usleep_range(wait_delay, wait_delay + 10); ++ wait_delay += delay_interval * 2; ++ rxdctl = 0; ++ ++ /* OR together the reading of all the active RXDCTL registers, ++ * and then test the result. We need the disable to complete ++ * before we start freeing the memory and invalidating the ++ * DMA mappings. ++ */ ++ for (i = 0; i < adapter->num_rx_queues; i++) { ++ struct ixgbe_ring *ring = adapter->rx_ring[i]; ++ u8 reg_idx = ring->reg_idx; ++ ++ rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); ++ } ++ ++ if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) ++ return; ++ } ++ ++ e_err(drv, ++ "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); ++} ++ ++void ixgbe_disable_tx(struct ixgbe_adapter *adapter) ++{ ++ unsigned long wait_delay, delay_interval; ++ struct ixgbe_hw *hw = &adapter->hw; ++ int i, wait_loop; ++ u32 txdctl; ++ ++ if (ixgbe_removed(hw->hw_addr)) ++ return; ++ ++ /* disable all enabled Tx queues */ ++ for (i = 0; i < adapter->num_tx_queues; i++) { ++ struct ixgbe_ring *ring = adapter->tx_ring[i]; ++ u8 reg_idx = ring->reg_idx; ++ ++ IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); ++ } ++ ++ /* disable all enabled XDP Tx queues */ ++ for (i = 0; i < adapter->num_xdp_queues; i++) { ++ struct ixgbe_ring *ring = adapter->xdp_ring[i]; ++ u8 reg_idx = ring->reg_idx; ++ ++ IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); ++ } ++ ++ /* If the link is not up there shouldn't be much in the way of ++ * pending transactions. Those that are left will be flushed out ++ * when the reset logic goes through the flush sequence to clean out ++ * the pending Tx transactions. ++ */ ++ if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) ++ goto dma_engine_disable; ++ ++ /* Determine our minimum delay interval. We will increase this value ++ * with each subsequent test. This way if the device returns quickly ++ * we should spend as little time as possible waiting, however as ++ * the time increases we will wait for larger periods of time. ++ * ++ * The trick here is that we increase the interval using the ++ * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result ++ * of that wait is that it totals up to 100x whatever interval we ++ * choose. Since our minimum wait is 100us we can just divide the ++ * total timeout by 100 to get our minimum delay interval. ++ */ ++ delay_interval = ixgbe_get_completion_timeout(adapter) / 100; ++ ++ wait_loop = IXGBE_MAX_RX_DESC_POLL; ++ wait_delay = delay_interval; ++ ++ while (wait_loop--) { ++ usleep_range(wait_delay, wait_delay + 10); ++ wait_delay += delay_interval * 2; ++ txdctl = 0; ++ ++ /* OR together the reading of all the active TXDCTL registers, ++ * and then test the result. We need the disable to complete ++ * before we start freeing the memory and invalidating the ++ * DMA mappings. ++ */ ++ for (i = 0; i < adapter->num_tx_queues; i++) { ++ struct ixgbe_ring *ring = adapter->tx_ring[i]; ++ u8 reg_idx = ring->reg_idx; ++ ++ txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); ++ } ++ for (i = 0; i < adapter->num_xdp_queues; i++) { ++ struct ixgbe_ring *ring = adapter->xdp_ring[i]; ++ u8 reg_idx = ring->reg_idx; ++ ++ txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); ++ } ++ ++ if (!(txdctl & IXGBE_TXDCTL_ENABLE)) ++ goto dma_engine_disable; ++ } ++ ++ e_err(drv, ++ "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); ++ ++dma_engine_disable: ++ /* Disable the Tx DMA engine on 82599 and later MAC */ ++ switch (hw->mac.type) { ++ case ixgbe_mac_82599EB: ++ case ixgbe_mac_X540: ++ case ixgbe_mac_X550: ++ case ixgbe_mac_X550EM_x: ++ case ixgbe_mac_x550em_a: ++ IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ++ (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & ++ ~IXGBE_DMATXCTL_TE)); ++ /* fall through */ ++ default: ++ break; ++ } ++} ++ + void ixgbe_reset(struct ixgbe_adapter *adapter) + { + struct ixgbe_hw *hw = &adapter->hw; +@@ -5835,13 +6013,8 @@ void ixgbe_down(struct ixgbe_adapter *ad + netif_carrier_off(netdev); + netif_tx_disable(netdev); + +- /* disable receives */ +- hw->mac.ops.disable_rx(hw); +- +- /* disable all enabled rx queues */ +- for (i = 0; i < adapter->num_rx_queues; i++) +- /* this call also flushes the previous write */ +- ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); ++ /* Disable Rx */ ++ ixgbe_disable_rx(adapter); + + ixgbe_irq_disable(adapter); + +@@ -5869,30 +6042,7 @@ void ixgbe_down(struct ixgbe_adapter *ad + } + + /* disable transmits in the hardware now that interrupts are off */ +- for (i = 0; i < adapter->num_tx_queues; i++) { +- u8 reg_idx = adapter->tx_ring[i]->reg_idx; +- IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); +- } +- for (i = 0; i < adapter->num_xdp_queues; i++) { +- u8 reg_idx = adapter->xdp_ring[i]->reg_idx; +- +- IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); +- } +- +- /* Disable the Tx DMA engine on 82599 and later MAC */ +- switch (hw->mac.type) { +- case ixgbe_mac_82599EB: +- case ixgbe_mac_X540: +- case ixgbe_mac_X550: +- case ixgbe_mac_X550EM_x: +- case ixgbe_mac_x550em_a: +- IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, +- (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & +- ~IXGBE_DMATXCTL_TE)); +- break; +- default: +- break; +- } ++ ixgbe_disable_tx(adapter); + + if (!pci_channel_offline(adapter->pdev)) + ixgbe_reset(adapter); diff --git a/patches.drivers/ixgbe-Reorder-Tx-Rx-shutdown-to-reduce-time-needed-t.patch b/patches.drivers/ixgbe-Reorder-Tx-Rx-shutdown-to-reduce-time-needed-t.patch new file mode 100644 index 0000000..7425932 --- /dev/null +++ b/patches.drivers/ixgbe-Reorder-Tx-Rx-shutdown-to-reduce-time-needed-t.patch @@ -0,0 +1,58 @@ +From: Alexander Duyck +Date: Fri, 20 Jul 2018 18:29:29 -0400 +Subject: ixgbe: Reorder Tx/Rx shutdown to reduce time needed to stop device +Patch-mainline: v4.17-rc6 +Git-commit: 3b5f14b50ee2079190ae6cfe7477e74676651665 +References: bsc#1101557 + +This change is meant to help reduce the time needed to shutdown the +transmit and receive paths for the device. Specifically what we now do +after this patch is disable the transmit path first at the netdev level, +and then work on disabling the Rx. This way while we are waiting on the Rx +queues to be disabled the Tx queues have an opportunity to drain out. + +In addition I have dropped the 10ms timeout that was left in the ixgbe_down +function that seems to have been carried through from back in e1000 as far +as I can tell. We shouldn't need it since we don't actually disable the Tx +until much later and we have additional logic in place for verifying the Tx +queues have been disabled. + +Signed-off-by: Alexander Duyck +Tested-by: Don Buchholz +Signed-off-by: Jeff Kirsher +Acked-by: Thomas Bogendoerfer +--- + drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 15 +++++++-------- + 1 file changed, 7 insertions(+), 8 deletions(-) + +--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c ++++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +@@ -5828,6 +5828,13 @@ void ixgbe_down(struct ixgbe_adapter *ad + if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) + return; /* do nothing if already down */ + ++ /* Shut off incoming Tx traffic */ ++ netif_tx_stop_all_queues(netdev); ++ ++ /* call carrier off first to avoid false dev_watchdog timeouts */ ++ netif_carrier_off(netdev); ++ netif_tx_disable(netdev); ++ + /* disable receives */ + hw->mac.ops.disable_rx(hw); + +@@ -5836,14 +5843,6 @@ void ixgbe_down(struct ixgbe_adapter *ad + /* this call also flushes the previous write */ + ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); + +- usleep_range(10000, 20000); +- +- netif_tx_stop_all_queues(netdev); +- +- /* call carrier off first to avoid false dev_watchdog timeouts */ +- netif_carrier_off(netdev); +- netif_tx_disable(netdev); +- + ixgbe_irq_disable(adapter); + + ixgbe_napi_disable_all(adapter); diff --git a/series.conf b/series.conf index 3e6bf66..7dbd153 100644 --- a/series.conf +++ b/series.conf @@ -11145,6 +11145,7 @@ patches.drivers/cpufreq-powernv-Dont-assume-distinct-pstate-values-f.patch patches.drivers/PM-devfreq-Propagate-error-from-devfreq_add_device patches.drivers/PM-devfreq-Fix-potential-NULL-pointer-dereference-in + patches.drivers/ACPICA-iasl-Add-SMMUv3-device-ID-mapping-index-suppo.patch patches.drivers/ACPICA-ACPI-6.0A-Changes-to-the-NFIT-ACPI-table.patch patches.fixes/ACPI-NUMA-ia64-Parse-all-entries-of-SRAT-memory-affi.patch patches.drivers/ACPI-sysfs-Make-ACPI-GPE-mask-kernel-parameter-cover @@ -14223,6 +14224,7 @@ patches.fixes/ext4-add-bounds-checking-to-ext4_xattr_find_entry.patch patches.drivers/random-use-a-tighter-cap-in-credit_entropy_bits_safe patches.drivers/irqchip-gic-Take-lock-when-updating-irq-type + patches.drivers/ACPI-IORT-Remove-temporary-iort_get_id_mapping_index.patch patches.drivers/crypto-chelsio-Make-function-aead_ccm_validate_input.patch patches.drivers/crypto-sunxi-ss-Add-MODULE_ALIAS-to-sun4i-ss patches.drivers/hwrng-stm32-add-reset-during-probe @@ -16685,6 +16687,8 @@ patches.drivers/brcmsmac-fix-wrap-around-in-conversion-from-constant patches.drivers/rndis_wlan-potential-buffer-overflow-in-rndis_wlan_a patches.drivers/libertas-fix-suspend-and-resume-for-SDIO-connected-c + patches.drivers/ixgbe-Reorder-Tx-Rx-shutdown-to-reduce-time-needed-t.patch + patches.drivers/ixgbe-Refactor-queue-disable-logic-to-take-completio.patch patches.drivers/qed-remove-redundant-functions-qed_set_gft_event_id_.patch patches.drivers/qed-remove-redundant-functions-qed_get_cm_pq_idx_rl.patch patches.drivers/qed-Make-some-functions-static.patch