From 8f9d9525e69aaabe7b6b4c2188ba25a8836d4bff Mon Sep 17 00:00:00 2001
From: Jiri Slaby <jslaby@suse.cz>
Date: May 10 2023 08:00:42 +0000
Subject: PCI: xilinx-nwl: Enable the clock through CCF (git-fixes).


---

diff --git a/patches.suse/PCI-xilinx-nwl-Enable-the-clock-through-CCF.patch b/patches.suse/PCI-xilinx-nwl-Enable-the-clock-through-CCF.patch
new file mode 100644
index 0000000..24c4771
--- /dev/null
+++ b/patches.suse/PCI-xilinx-nwl-Enable-the-clock-through-CCF.patch
@@ -0,0 +1,60 @@
+From: Hyun Kwon <hyun.kwon@xilinx.com>
+Date: Fri, 25 Jun 2021 12:48:23 +0200
+Subject: PCI: xilinx-nwl: Enable the clock through CCF
+Git-commit: de0a01f5296651d3a539f2d23d0db8f359483696
+Patch-mainline: 5.15-rc1
+References: git-fixes
+
+Enable PCIe reference clock. There is no remove function that's why
+this should be enough for simple operation.
+Normally this clock is enabled by default by firmware but there are
+usecases where this clock should be enabled by driver itself.
+It is also good that PCIe clock is recorded in a clock framework.
+
+Link: https://lore.kernel.org/r/ee6997a08fab582b1c6de05f8be184f3fe8d5357.1624618100.git.michal.simek@xilinx.com
+Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller")
+Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
+Signed-off-by: Michal Simek <michal.simek@xilinx.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Jiri Slaby <jslaby@suse.cz>
+---
+ drivers/pci/host/pcie-xilinx-nwl.c |   12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/pci/host/pcie-xilinx-nwl.c
++++ b/drivers/pci/host/pcie-xilinx-nwl.c
+@@ -10,6 +10,7 @@
+  * (at your option) any later version.
+  */
+ 
++#include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+ #include <linux/irq.h>
+@@ -171,6 +172,7 @@ struct nwl_pcie {
+ 	u8 root_busno;
+ 	struct nwl_msi msi;
+ 	struct irq_domain *legacy_irq_domain;
++	struct clk *clk;
+ };
+ 
+ static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
+@@ -808,6 +810,16 @@ static int nwl_pcie_probe(struct platfor
+ 		return err;
+ 	}
+ 
++	pcie->clk = devm_clk_get(dev, NULL);
++	if (IS_ERR(pcie->clk))
++		return PTR_ERR(pcie->clk);
++
++	err = clk_prepare_enable(pcie->clk);
++	if (err) {
++		dev_err(dev, "can't enable PCIe ref clock\n");
++		return err;
++	}
++
+ 	err = nwl_pcie_bridge_init(pcie);
+ 	if (err) {
+ 		dev_err(dev, "HW Initialization failed\n");
diff --git a/series.conf b/series.conf
index a75f02a..c54514c 100644
--- a/series.conf
+++ b/series.conf
@@ -61606,6 +61606,7 @@
 	patches.suse/PCI-aardvark-Configure-PCIe-resources-from-ranges-DT.patch
 	patches.suse/PCI-aardvark-Fix-masking-and-unmasking-legacy-INTx-i.patch
 	patches.suse/msft-hv-2426-PCI-hv-Support-for-create-interrupt-v3.patch
+	patches.suse/PCI-xilinx-nwl-Enable-the-clock-through-CCF.patch
 	patches.suse/profiling-fix-shift-out-of-bounds-bugs.patch
 	patches.suse/prctl-allow-to-setup-brk-for-et_dyn-executables.patch
 	patches.suse/ceph-lockdep-annotations-for-try_nonblocking_invalidate.patch