From cb56da11f5d8ad0ca80a96f7607878cdcafec6d7 Mon Sep 17 00:00:00 2001 From: Denis Kirjanov Date: Feb 01 2021 20:52:25 +0000 Subject: Merge branch 'users/jroedel/SLE12-SP5/for-next' into SLE12-SP5 Pull x86 fixes from Joerg Roedel --- diff --git a/patches.kabi/kABI-Fix-kABI-for-extended-APIC-ID-support.patch b/patches.kabi/kABI-Fix-kABI-for-extended-APIC-ID-support.patch new file mode 100644 index 0000000..9549be4 --- /dev/null +++ b/patches.kabi/kABI-Fix-kABI-for-extended-APIC-ID-support.patch @@ -0,0 +1,32 @@ +From: Joerg Roedel +Date: Fri, 22 Jan 2021 16:56:17 +0100 +Subject: [PATCH] kABI: Fix kABI for extended APIC-ID support +Patch-mainline: Never, kABI fix +References: bsc#1181001, jsc#ECO-3191 + +Signed-off-by: Joerg Roedel +--- + arch/x86/include/asm/io_apic.h | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h +index 31bd718748c3..4f642bc3cc00 100644 +--- a/arch/x86/include/asm/io_apic.h ++++ b/arch/x86/include/asm/io_apic.h +@@ -76,9 +76,12 @@ struct IO_APIC_route_entry { + trigger : 1, /* 0: edge, 1: level */ + mask : 1, /* 0: enabled, 1: disabled */ + __reserved_2 : 15; +- ++#ifndef __GENKSYMS__ + __u32 __reserved_3 : 17, + ext_dest : 7, ++#else ++ __u32 __reserved_3 : 24, ++#endif + dest : 8; + } __attribute__ ((packed)); + +-- +2.25.0 + diff --git a/patches.suse/0001-x86-apic-Fix-x2apic-enablement-without-interrupt-rem.patch b/patches.suse/0001-x86-apic-Fix-x2apic-enablement-without-interrupt-rem.patch new file mode 100644 index 0000000..b7e0f7d --- /dev/null +++ b/patches.suse/0001-x86-apic-Fix-x2apic-enablement-without-interrupt-rem.patch @@ -0,0 +1,99 @@ +From: David Woodhouse +Date: Wed, 7 Oct 2020 13:20:42 +0100 +Subject: [PATCH 1/5] x86/apic: Fix x2apic enablement without interrupt + remapping +Patch-mainline: Never, upstream uses different implementation +References: bsc#1181001, jsc#ECO-3191 + +Currently, Linux as a hypervisor guest will enable x2apic only if there +are no CPUs present at boot time with an APIC ID above 255. + +Hotplugging a CPU later with a higher APIC ID would result in a CPU +which cannot be targeted by external interrupts. + +Add a filter in x2apic_apic_id_valid() which can be used to prevent +such CPUs from coming online, and allow x2apic to be enabled even if +they are present at boot time. + +Fixes: ce69a784504 ("x86/apic: Enable x2APIC without interrupt remapping under KVM") +Signed-off-by: David Woodhouse +Acked-by: Joerg Roedel +--- + arch/x86/include/asm/apic.h | 1 + + arch/x86/include/asm/x2apic.h | 5 +++++ + arch/x86/kernel/apic/apic.c | 14 ++++++++------ + arch/x86/kernel/apic/x2apic_phys.c | 6 ++++++ + 4 files changed, 20 insertions(+), 6 deletions(-) + +--- a/arch/x86/include/asm/apic.h ++++ b/arch/x86/include/asm/apic.h +@@ -235,6 +235,7 @@ static inline u64 native_x2apic_icr_read + + extern int x2apic_mode; + extern int x2apic_phys; ++extern void __init x2apic_set_max_apicid(u32 apicid); + extern void __init check_x2apic(void); + extern void x2apic_setup(void); + static inline int x2apic_enabled(void) +--- a/arch/x86/include/asm/x2apic.h ++++ b/arch/x86/include/asm/x2apic.h +@@ -9,8 +9,13 @@ + #include + #include + ++extern u32 x2apic_max_apicid; ++ + static int x2apic_apic_id_valid(int apicid) + { ++ if (x2apic_max_apicid && apicid > x2apic_max_apicid) ++ return 0; ++ + return 1; + } + +--- a/arch/x86/kernel/apic/apic.c ++++ b/arch/x86/kernel/apic/apic.c +@@ -1580,20 +1580,22 @@ static __init void try_to_enable_x2apic( + return; + + if (remap_mode != IRQ_REMAP_X2APIC_MODE) { +- /* IR is required if there is APIC ID > 255 even when running +- * under KVM ++ /* ++ * Using X2APIC without IR is not architecturally supported ++ * on bare metal but may be supported in guests. + */ +- if (max_physical_apicid > 255 || +- !x86_init.hyper.x2apic_available()) { ++ if (!x86_init.hyper.x2apic_available()) { + pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); + x2apic_disable(); + return; + } + + /* +- * without IR all CPUs can be addressed by IOAPIC/MSI +- * only in physical mode ++ * Without IR, all CPUs can be addressed by IOAPIC/MSI only ++ * in physical mode, and CPUs with an APIC ID that cannnot ++ * be addressed must not be brought online. + */ ++ x2apic_set_max_apicid(255); + x2apic_phys = 1; + } + x2apic_enable(); +--- a/arch/x86/kernel/apic/x2apic_phys.c ++++ b/arch/x86/kernel/apic/x2apic_phys.c +@@ -11,6 +11,12 @@ + int x2apic_phys; + + static struct apic apic_x2apic_phys; ++u32 x2apic_max_apicid; ++ ++void __init x2apic_set_max_apicid(u32 apicid) ++{ ++ x2apic_max_apicid = apicid; ++} + + static int set_x2apic_phys_mode(char *arg) + { diff --git a/patches.suse/0002-x86-msi-Only-use-high-bits-of-MSI-address-for-DMAR-u.patch b/patches.suse/0002-x86-msi-Only-use-high-bits-of-MSI-address-for-DMAR-u.patch new file mode 100644 index 0000000..18cf172 --- /dev/null +++ b/patches.suse/0002-x86-msi-Only-use-high-bits-of-MSI-address-for-DMAR-u.patch @@ -0,0 +1,97 @@ +From: David Woodhouse +Date: Wed, 7 Oct 2020 13:20:43 +0100 +Subject: [PATCH 2/5] x86/msi: Only use high bits of MSI address for DMAR unit +Patch-mainline: Never, upstream uses different implementation +References: bsc#1181001, jsc#ECO-3191 + +The Intel IOMMU has an MSI-like configuration for its interrupt, but +it isn't really MSI. So it gets to abuse the high 32 bits of the address, +and puts the high 24 bits of the extended APIC ID there. + +This isn't something that can be used in the general case for real MSIs, +since external devices using the high bits of the address would be +performing writes to actual memory space above 4GiB, not targeted at the +APIC. + +Factor the hack out and allow it only to be used when appropriate, +adding a WARN_ON_ONCE() if other MSIs are targeted at an unreachable +APIC ID. In *theory* that should never happen since the compatibility +MSI messages are not supposed to be used with Interrupt Remapping +enabled. In practice, if IR is enabled but some devices aren't within +scope of any given remapping unit, it might happen. But that's a longer +story and this warning is the right thing to do in that case for the +short term. + +The x2apic_enabled() check isn't needed because Linux won't bring up +CPUs with higher APIC IDs unless x2apic is enabled anyway. + +Signed-off-by: David Woodhouse +Acked-by: Joerg Roedel +--- + arch/x86/kernel/apic/msi.c | 36 +++++++++++++++++++++++++++++++----- + 1 file changed, 31 insertions(+), 5 deletions(-) + +--- a/arch/x86/kernel/apic/msi.c ++++ b/arch/x86/kernel/apic/msi.c +@@ -25,15 +25,13 @@ + + static struct irq_domain *msi_default_domain; + +-static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg) ++static void __irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg, ++ bool dmar) + { + struct irq_cfg *cfg = irqd_cfg(data); + + msg->address_hi = MSI_ADDR_BASE_HI; + +- if (x2apic_enabled()) +- msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid); +- + msg->address_lo = + MSI_ADDR_BASE_LO | + ((apic->irq_dest_mode == 0) ? +@@ -51,6 +49,34 @@ static void irq_msi_compose_msg(struct i + MSI_DATA_DELIVERY_FIXED : + MSI_DATA_DELIVERY_LOWPRI) | + MSI_DATA_VECTOR(cfg->vector); ++ ++ /* ++ * Only the IOMMU itself can use the trick of putting destination ++ * APIC ID into the high bits of the address. Anything else would ++ * just be writing to memory if it tried that, and needs IR to ++ * address higher APIC IDs. ++ */ ++ if (dmar) ++ msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid); ++ else ++ WARN_ON_ONCE(MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid)); ++} ++ ++static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg) ++{ ++ __irq_msi_compose_msg(data, msg, false); ++} ++ ++ ++/* ++ * The Intel IOMMU (ab)uses the high bits of the MSI address to contain the ++ * high bits of the destination APIC ID. This can't be done in the general ++ * case for MSIs as it would be targeting real memory above 4GiB not the ++ * APIC. ++ */ ++static void dmar_msi_compose_msg(struct irq_data *data, struct msi_msg *msg) ++{ ++ __irq_msi_compose_msg(data, msg, true); + } + + /* +@@ -186,7 +212,7 @@ static struct irq_chip dmar_msi_controll + .irq_ack = irq_chip_ack_parent, + .irq_set_affinity = msi_domain_set_affinity, + .irq_retrigger = irq_chip_retrigger_hierarchy, +- .irq_compose_msi_msg = irq_msi_compose_msg, ++ .irq_compose_msi_msg = dmar_msi_compose_msg, + .irq_write_msi_msg = dmar_msi_write_msg, + .flags = IRQCHIP_SKIP_SET_WAKE, + }; diff --git a/patches.suse/0003-x86-ioapic-Handle-Extended-Destination-ID-field-in-R.patch b/patches.suse/0003-x86-ioapic-Handle-Extended-Destination-ID-field-in-R.patch new file mode 100644 index 0000000..bc4e5d9 --- /dev/null +++ b/patches.suse/0003-x86-ioapic-Handle-Extended-Destination-ID-field-in-R.patch @@ -0,0 +1,115 @@ +From: David Woodhouse +Date: Wed, 7 Oct 2020 13:20:44 +0100 +Subject: [PATCH 3/5] x86/ioapic: Handle Extended Destination ID field in RTE +Patch-mainline: Never, upstream uses different implementation +References: bsc#1181001, jsc#ECO-3191 + +The IOAPIC Redirection Table Entries contain an 8-bit Extended +Destination ID field which maps to bits 11-4 of the MSI address. + +The lowest bit is used to indicate remappable format, when interrupt +remapping is in use. A hypervisor can use the other 7 bits to permit +guests to address up to 15 bits of APIC IDs, thus allowing 32768 vCPUs +before having to expose a vIOMMU and interrupt remapping to the guest. + +No behavioural change in this patch, since nothing yet permits APIC IDs +above 255 to be used with the non-IR IOAPIC domain. Except for the case +where IR is enabled but there are IOAPICs which aren't in the scope of +any IOMMU, which is totally hosed anyway and needs fixing independently +of this change. + +Signed-off-by: David Woodhouse +Acked-by: Joerg Roedel +--- + arch/x86/include/asm/io_apic.h | 3 ++- + arch/x86/kernel/apic/io_apic.c | 19 +++++++++++++------ + 2 files changed, 15 insertions(+), 7 deletions(-) + +--- a/arch/x86/include/asm/io_apic.h ++++ b/arch/x86/include/asm/io_apic.h +@@ -77,7 +77,8 @@ struct IO_APIC_route_entry { + mask : 1, /* 0: enabled, 1: disabled */ + __reserved_2 : 15; + +- __u32 __reserved_3 : 24, ++ __u32 __reserved_3 : 17, ++ ext_dest : 7, + dest : 8; + } __attribute__ ((packed)); + +--- a/arch/x86/kernel/apic/io_apic.c ++++ b/arch/x86/kernel/apic/io_apic.c +@@ -1268,10 +1268,10 @@ static void io_apic_print_entries(unsign + buf, (ir_entry->index << 15) | ir_entry->index, + ir_entry->zero); + else +- printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n", ++ printk(KERN_DEBUG "%s, %s, D(%02X%02X), M(%1d)\n", + buf, + entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ? +- "logical " : "physical", ++ "logical " : "physical", entry.ext_dest, + entry.dest, entry.delivery_mode); + } + } +@@ -1439,6 +1439,7 @@ void native_disable_io_apic(void) + */ + if (ioapic_i8259.pin != -1) { + struct IO_APIC_route_entry entry; ++ u32 apic_id = read_apic_id(); + + memset(&entry, 0, sizeof(entry)); + entry.mask = IOAPIC_UNMASKED; +@@ -1446,7 +1447,8 @@ void native_disable_io_apic(void) + entry.polarity = IOAPIC_POL_HIGH; + entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL; + entry.delivery_mode = dest_ExtINT; +- entry.dest = read_apic_id(); ++ entry.dest = apic_id & 0xff; ++ entry.ext_dest = apic_id >> 8; + + /* + * Add it to the IO-APIC irq-routing table: +@@ -1861,7 +1863,8 @@ static int ioapic_set_affinity(struct ir + raw_spin_lock_irqsave(&ioapic_lock, flags); + if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) { + cfg = irqd_cfg(irq_data); +- data->entry.dest = cfg->dest_apicid; ++ data->entry.dest = cfg->dest_apicid & 0xff; ++ data->entry.ext_dest = cfg->dest_apicid >> 8; + data->entry.vector = cfg->vector; + for_each_irq_pin(entry, data->irq_2_pin) + __ioapic_write_entry(entry->apic, entry->pin, +@@ -1969,6 +1972,7 @@ static inline void __init unlock_ExtINT_ + int apic, pin, i; + struct IO_APIC_route_entry entry0, entry1; + unsigned char save_control, save_freq_select; ++ u32 apic_id; + + pin = find_isa_irq_pin(8, mp_INT); + if (pin == -1) { +@@ -1984,11 +1988,13 @@ static inline void __init unlock_ExtINT_ + entry0 = ioapic_read_entry(apic, pin); + clear_IO_APIC_pin(apic, pin); + ++ apic_id = hard_smp_processor_id(); + memset(&entry1, 0, sizeof(entry1)); + + entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL; + entry1.mask = IOAPIC_UNMASKED; +- entry1.dest = hard_smp_processor_id(); ++ entry1.dest = apic_id & 0xff; ++ entry1.ext_dest = apic_id >> 8; + entry1.delivery_mode = dest_ExtINT; + entry1.polarity = entry0.polarity; + entry1.trigger = IOAPIC_EDGE; +@@ -2896,7 +2902,8 @@ static void mp_setup_entry(struct irq_cf + memset(entry, 0, sizeof(*entry)); + entry->delivery_mode = apic->irq_delivery_mode; + entry->dest_mode = apic->irq_dest_mode; +- entry->dest = cfg->dest_apicid; ++ entry->dest = cfg->dest_apicid & 0xff; ++ entry->ext_dest = cfg->dest_apicid >> 8; + entry->vector = cfg->vector; + entry->trigger = data->trigger; + entry->polarity = data->polarity; diff --git a/patches.suse/0004-x86-apic-Support-15-bits-of-APIC-ID-in-IOAPIC-MSI-wh.patch b/patches.suse/0004-x86-apic-Support-15-bits-of-APIC-ID-in-IOAPIC-MSI-wh.patch new file mode 100644 index 0000000..559b0ae --- /dev/null +++ b/patches.suse/0004-x86-apic-Support-15-bits-of-APIC-ID-in-IOAPIC-MSI-wh.patch @@ -0,0 +1,120 @@ +From: David Woodhouse +Date: Wed, 7 Oct 2020 13:20:45 +0100 +Subject: [PATCH 4/5] x86/apic: Support 15 bits of APIC ID in IOAPIC/MSI where + available +Patch-mainline: Never, upstream uses different implementation +References: bsc#1181001, jsc#ECO-3191 + +Some hypervisors can allow the guest to use the Extended Destination ID +field in the IOAPIC RTE and MSI address to address up to 32768 CPUs. + +Signed-off-by: David Woodhouse +Acked-by: Joerg Roedel +--- + arch/x86/include/asm/mpspec.h | 1 + + arch/x86/include/asm/x86_init.h | 2 ++ + arch/x86/kernel/apic/apic.c | 15 ++++++++++++++- + arch/x86/kernel/apic/msi.c | 9 ++++++++- + arch/x86/kernel/x86_init.c | 1 + + 5 files changed, 26 insertions(+), 2 deletions(-) + +--- a/arch/x86/include/asm/mpspec.h ++++ b/arch/x86/include/asm/mpspec.h +@@ -41,6 +41,7 @@ extern DECLARE_BITMAP(mp_bus_not_pci, MA + extern unsigned int boot_cpu_physical_apicid; + extern u8 boot_cpu_apic_version; + extern unsigned long mp_lapic_addr; ++extern int msi_ext_dest_id; + + #ifdef CONFIG_X86_LOCAL_APIC + extern int smp_found_config; +--- a/arch/x86/include/asm/x86_init.h ++++ b/arch/x86/include/asm/x86_init.h +@@ -117,11 +117,13 @@ struct x86_init_pci { + * struct x86_hyper_init - x86 hypervisor init functions + * @init_platform: platform setup + * @x2apic_available: X2APIC detection ++ * @msi_ext_dest_id: MSI and IOAPIC support 15-bit APIC IDs + * @init_mem_mapping: setup early mappings during init_mem_mapping() + */ + struct x86_hyper_init { + void (*init_platform)(void); + bool (*x2apic_available)(void); ++ bool (*msi_ext_dest_id)(void); + void (*init_mem_mapping)(void); + }; + +--- a/arch/x86/kernel/apic/apic.c ++++ b/arch/x86/kernel/apic/apic.c +@@ -1576,9 +1576,21 @@ static __init void x2apic_enable(void) + + static __init void try_to_enable_x2apic(int remap_mode) + { ++ u32 apic_limit = 255; ++ + if (x2apic_state == X2APIC_DISABLED) + return; + ++ /* ++ * If the hypervisor supports extended destination ID in IOAPIC ++ * and MSI, that increases the maximum APIC ID that can be used ++ * for non-remapped IRQ domains. ++ */ ++ if (x86_init.hyper.msi_ext_dest_id()) { ++ msi_ext_dest_id = 1; ++ apic_limit = 32767; ++ } ++ + if (remap_mode != IRQ_REMAP_X2APIC_MODE) { + /* + * Using X2APIC without IR is not architecturally supported +@@ -1595,9 +1607,10 @@ static __init void try_to_enable_x2apic( + * in physical mode, and CPUs with an APIC ID that cannnot + * be addressed must not be brought online. + */ +- x2apic_set_max_apicid(255); ++ x2apic_set_max_apicid(apic_limit); + x2apic_phys = 1; + } ++ + x2apic_enable(); + } + +--- a/arch/x86/kernel/apic/msi.c ++++ b/arch/x86/kernel/apic/msi.c +@@ -25,6 +25,8 @@ + + static struct irq_domain *msi_default_domain; + ++int msi_ext_dest_id; ++ + static void __irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg, + bool dmar) + { +@@ -54,10 +56,15 @@ static void __irq_msi_compose_msg(struct + * Only the IOMMU itself can use the trick of putting destination + * APIC ID into the high bits of the address. Anything else would + * just be writing to memory if it tried that, and needs IR to +- * address higher APIC IDs. ++ * address APICs which can't be addressed in the normal 32-bit ++ * address range at 0xFFExxxxx. That is typically just 8 bits, but ++ * some hypervisors allow the extended destination ID field in bits ++ * 11-5 to be used, giving support for 15 bits of APIC IDs in total. + */ + if (dmar) + msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid); ++ else if (msi_ext_dest_id && cfg->dest_apicid < 0x8000) ++ msg->address_lo |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid) >> 3; + else + WARN_ON_ONCE(MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid)); + } +--- a/arch/x86/kernel/x86_init.c ++++ b/arch/x86/kernel/x86_init.c +@@ -87,6 +87,7 @@ struct x86_init_ops x86_init __initdata + .hyper = { + .init_platform = x86_init_noop, + .x2apic_available = bool_x86_init_noop, ++ .msi_ext_dest_id = bool_x86_init_noop, + .init_mem_mapping = x86_init_noop, + }, + }; diff --git a/patches.suse/0005-x86-kvm-Add-KVM_FEATURE_MSI_EXT_DEST_ID.patch b/patches.suse/0005-x86-kvm-Add-KVM_FEATURE_MSI_EXT_DEST_ID.patch new file mode 100644 index 0000000..18c9740 --- /dev/null +++ b/patches.suse/0005-x86-kvm-Add-KVM_FEATURE_MSI_EXT_DEST_ID.patch @@ -0,0 +1,39 @@ +From: David Woodhouse +Date: Wed, 7 Oct 2020 13:20:46 +0100 +Subject: [PATCH 5/5] x86/kvm: Add KVM_FEATURE_MSI_EXT_DEST_ID +Patch-mainline: Never, upstream uses different implementation +References: bsc#1181001, jsc#ECO-3191 + +This allows the host to indicate that IOAPIC and MSI emulation supports +15-bit destination IDs, allowing up to 32768 CPUs without interrupt +remapping. + +cf. https://patchwork.kernel.org/patch/11816693/ for qemu + +Signed-off-by: David Woodhouse +Acked-by: Paolo Bonzini +Acked-by: Joerg Roedel +--- + arch/x86/kernel/kvm.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/x86/kernel/kvm.c ++++ b/arch/x86/kernel/kvm.c +@@ -578,11 +578,17 @@ static uint32_t __init kvm_detect(void) + return kvm_cpuid_base(); + } + ++static bool __init kvm_msi_ext_dest_id(void) ++{ ++ return kvm_para_has_feature(KVM_FEATURE_MSI_EXT_DEST_ID); ++} ++ + const __initconst struct hypervisor_x86 x86_hyper_kvm = { + .name = "KVM", + .detect = kvm_detect, + .type = X86_HYPER_KVM, + .init.x2apic_available = kvm_para_available, ++ .init.msi_ext_dest_id = kvm_msi_ext_dest_id, + }; + + static __init int activate_jump_labels(void) diff --git a/patches.suse/iommu-vt-d-don-t-dereference-iommu_device-if-iommu_api-is-not-built b/patches.suse/iommu-vt-d-don-t-dereference-iommu_device-if-iommu_api-is-not-built new file mode 100644 index 0000000..07093ba --- /dev/null +++ b/patches.suse/iommu-vt-d-don-t-dereference-iommu_device-if-iommu_api-is-not-built @@ -0,0 +1,64 @@ +From: Bartosz Golaszewski +Date: Tue, 13 Oct 2020 09:30:55 +0200 +Subject: iommu/vt-d: Don't dereference iommu_device if IOMMU_API is not built +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +Git-commit: 9def3b1a07c41e21c68a0eb353e3e569fdd1d2b1 +Patch-mainline: v5.10-rc1 +References: bsc#1181001, jsc#ECO-3191 + +Since commit c40aaaac1018 ("iommu/vt-d: Gracefully handle DMAR units +with no supported address widths") dmar.c needs struct iommu_device to +be selected. We can drop this dependency by not dereferencing struct +iommu_device if IOMMU_API is not selected and by reusing the information +stored in iommu->drhd->ignored instead. + +This fixes the following build error when IOMMU_API is not selected: + +drivers/iommu/dmar.c: In function ‘free_iommu’: +drivers/iommu/dmar.c:1139:41: error: ‘struct iommu_device’ has no member named ‘ops’ + 1139 | if (intel_iommu_enabled && iommu->iommu.ops) { + ^ + +Fixes: c40aaaac1018 ("iommu/vt-d: Gracefully handle DMAR units with no supported address widths") +Signed-off-by: Bartosz Golaszewski +Acked-by: Lu Baolu +Acked-by: David Woodhouse +Link: https://lore.kernel.org/r/20201013073055.11262-1-brgl@bgdev.pl +Signed-off-by: Joerg Roedel +--- + drivers/iommu/dmar.c | 3 ++- + include/linux/intel-iommu.h | 2 ++ + 2 files changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/iommu/dmar.c ++++ b/drivers/iommu/dmar.c +@@ -1125,6 +1125,7 @@ static int alloc_iommu(struct dmar_drhd_ + } + + drhd->iommu = iommu; ++ iommu->drhd = drhd; + + return 0; + +@@ -1139,7 +1140,7 @@ error: + + static void free_iommu(struct intel_iommu *iommu) + { +- if (intel_iommu_enabled && iommu->iommu.ops) { ++ if (intel_iommu_enabled && !iommu->drhd->ignored) { + iommu_device_unregister(&iommu->iommu); + iommu_device_sysfs_remove(&iommu->iommu); + } +--- a/include/linux/intel-iommu.h ++++ b/include/linux/intel-iommu.h +@@ -435,6 +435,8 @@ struct intel_iommu { + struct iommu_device iommu; /* IOMMU core code handle */ + int node; + u32 flags; /* Software defined flags */ ++ ++ struct dmar_drhd_unit *drhd; + }; + + static inline void __iommu_flush_cache( diff --git a/patches.suse/iommu-vt-d-gracefully-handle-dmar-units-with-no-supported-address-widths b/patches.suse/iommu-vt-d-gracefully-handle-dmar-units-with-no-supported-address-widths new file mode 100644 index 0000000..bd671fa --- /dev/null +++ b/patches.suse/iommu-vt-d-gracefully-handle-dmar-units-with-no-supported-address-widths @@ -0,0 +1,95 @@ +From: David Woodhouse +Date: Thu, 24 Sep 2020 15:08:42 +0100 +Subject: iommu/vt-d: Gracefully handle DMAR units with no supported address + widths +Git-commit: c40aaaac1018ff1382f2d35df5129a6bcea3df6b +Patch-mainline: v5.10-rc1 +References: bsc#1181001, jsc#ECO-3191 + +Instead of bailing out completely, such a unit can still be used for +interrupt remapping. + +Signed-off-by: David Woodhouse +Reviewed-by: Lu Baolu +Link: https://lore.kernel.org/linux-iommu/549928db2de6532117f36c9c810373c14cf76f51.camel@infradead.org/ +Signed-off-by: Joerg Roedel +--- + drivers/iommu/dmar.c | 46 +++++++++++++++++++++++++++++++--------------- + 1 file changed, 31 insertions(+), 15 deletions(-) + +--- a/drivers/iommu/dmar.c ++++ b/drivers/iommu/dmar.c +@@ -1031,8 +1031,8 @@ static int alloc_iommu(struct dmar_drhd_ + { + struct intel_iommu *iommu; + u32 ver, sts; +- int agaw = 0; +- int msagaw = 0; ++ int agaw = -1; ++ int msagaw = -1; + int err; + + if (!drhd->reg_base_addr) { +@@ -1057,17 +1057,28 @@ static int alloc_iommu(struct dmar_drhd_ + } + + err = -EINVAL; +- agaw = iommu_calculate_agaw(iommu); +- if (agaw < 0) { +- pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n", +- iommu->seq_id); +- goto err_unmap; +- } +- msagaw = iommu_calculate_max_sagaw(iommu); +- if (msagaw < 0) { +- pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n", +- iommu->seq_id); +- goto err_unmap; ++ if (cap_sagaw(iommu->cap) == 0) { ++ pr_info("%s: No supported address widths. Not attempting DMA translation.\n", ++ iommu->name); ++ drhd->ignored = 1; ++ } ++ ++ if (!drhd->ignored) { ++ agaw = iommu_calculate_agaw(iommu); ++ if (agaw < 0) { ++ pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n", ++ iommu->seq_id); ++ drhd->ignored = 1; ++ } ++ } ++ if (!drhd->ignored) { ++ msagaw = iommu_calculate_max_sagaw(iommu); ++ if (msagaw < 0) { ++ pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n", ++ iommu->seq_id); ++ drhd->ignored = 1; ++ agaw = -1; ++ } + } + iommu->agaw = agaw; + iommu->msagaw = msagaw; +@@ -1094,7 +1105,12 @@ static int alloc_iommu(struct dmar_drhd_ + + raw_spin_lock_init(&iommu->register_lock); + +- if (intel_iommu_enabled) { ++ /* ++ * This is only for hotplug; at boot time intel_iommu_enabled won't ++ * be set yet. When intel_iommu_init() runs, it registers the units ++ * present at boot time, then sets intel_iommu_enabled. ++ */ ++ if (intel_iommu_enabled && !drhd->ignored) { + err = iommu_device_sysfs_add(&iommu->iommu, NULL, + intel_iommu_groups, + "%s", iommu->name); +@@ -1123,7 +1139,7 @@ error: + + static void free_iommu(struct intel_iommu *iommu) + { +- if (intel_iommu_enabled) { ++ if (intel_iommu_enabled && iommu->iommu.ops) { + iommu_device_unregister(&iommu->iommu); + iommu_device_sysfs_remove(&iommu->iommu); + } diff --git a/patches.suse/x86-kvm-reserve-kvm_feature_msi_ext_dest_id b/patches.suse/x86-kvm-reserve-kvm_feature_msi_ext_dest_id new file mode 100644 index 0000000..59dbc9e --- /dev/null +++ b/patches.suse/x86-kvm-reserve-kvm_feature_msi_ext_dest_id @@ -0,0 +1,48 @@ +From: David Woodhouse +Date: Mon, 19 Oct 2020 15:55:56 +0100 +Subject: x86/kvm: Reserve KVM_FEATURE_MSI_EXT_DEST_ID +Git-commit: 5a169bf04cd2bfdbac967d12eb5b70915b29d7ee +Patch-mainline: v5.10-rc2 +References: bsc#1181001, jsc#ECO-3191 + +No functional change; just reserve the feature bit for now so that VMMs +can start to implement it. + +This will allow the host to indicate that MSI emulation supports 15-bit +destination IDs, allowing up to 32768 CPUs without interrupt remapping. + +cf. https://patchwork.kernel.org/patch/11816693/ for qemu + +Signed-off-by: David Woodhouse +Acked-by: Paolo Bonzini +Message-Id: <4cd59bed05f4b7410d3d1ffd1e997ab53683874d.camel@infradead.org> +Signed-off-by: Paolo Bonzini +Acked-by: Joerg Roedel +--- + Documentation/virtual/kvm/cpuid.txt | 4 ++++ + arch/x86/include/uapi/asm/kvm_para.h | 1 + + 2 files changed, 5 insertions(+) + +--- a/Documentation/virtual/kvm/cpuid.txt ++++ b/Documentation/virtual/kvm/cpuid.txt +@@ -58,6 +58,10 @@ KVM_FEATURE_ASYNC_PF_VMEXIT || + || || can be enabled by setting bit 2 + || || when writing to msr 0x4b564d02 + ------------------------------------------------------------------------------ ++KVM_FEATURE_MSI_EXT_DEST_ID || 15 || guest checks this feature bit ++ || || before using extended destination ++ || || ID bits in MSI address bits 11-5. ++------------------------------------------------------------------------------ + KVM_FEATURE_CLOCKSOURCE_STABLE_BIT || 24 || host will warn if no guest-side + || || per-cpu warps are expected in + || || kvmclock. +--- a/arch/x86/include/uapi/asm/kvm_para.h ++++ b/arch/x86/include/uapi/asm/kvm_para.h +@@ -24,6 +24,7 @@ + #define KVM_FEATURE_PV_EOI 6 + #define KVM_FEATURE_PV_UNHALT 7 + #define KVM_FEATURE_ASYNC_PF_VMEXIT 10 ++#define KVM_FEATURE_MSI_EXT_DEST_ID 15 + + /* The last 8 bits are used to indicate how to interpret the flags field + * in pvclock structure. If no bits are set, all flags are ignored. diff --git a/series.conf b/series.conf index e791f11..5e4e516 100644 --- a/series.conf +++ b/series.conf @@ -56966,6 +56966,7 @@ patches.suse/PM-hibernate-remove-the-bogus-call-to-get_gendisk-in.patch patches.suse/ACPI-video-use-ACPI-backlight-for-HP-635-Notebook.patch patches.suse/ACPI-extlog-Check-for-RDMSR-failure.patch + patches.suse/iommu-vt-d-gracefully-handle-dmar-units-with-no-supported-address-widths patches.suse/scsi-smartpqi-identify-physical-devices-without-issuing-inquiry.patch patches.suse/scsi-smartpqi-add-id-support-for-smartraid-3152-8i.patch patches.suse/scsi-smartpqi-update-logical-volume-size-after-expansion.patch @@ -57204,6 +57205,7 @@ patches.suse/0010-xen-events-use-a-common-cpu-hotplug-hook-for-event-c.patch patches.suse/0011-xen-events-defer-eoi-in-case-of-excessive-number-of-.patch patches.suse/0012-xen-events-block-rogue-events-for-some-time.patch + patches.suse/iommu-vt-d-don-t-dereference-iommu_device-if-iommu_api-is-not-built patches.suse/power-supply-test_power-add-missing-newlines-when-pr.patch patches.suse/NFS-fix-nfs_path-in-case-of-a-rename-retry.patch patches.suse/NFSv4.2-support-EXCHGID4_FLAG_SUPP_FENCE_OPS-4.2-EXC.patch @@ -57287,6 +57289,7 @@ patches.suse/btrfs-fix-use-after-free-on-readahead-extent-after-f.patch patches.suse/scsi-qla2xxx-Return-EBUSY-on-fcport-deletion.patch patches.suse/scsi-ibmvscsi-Fix-potential-race-after-loss-of-trans.patch + patches.suse/x86-kvm-reserve-kvm_feature_msi_ext_dest_id patches.suse/usb-host-fsl-mph-dr-of-check-return-of-dma_set_mask.patch patches.suse/usb-cdc-acm-fix-cooldown-mechanism.patch patches.suse/usb-typec-tcpm-reset-hard_reset_count-for-any-discon.patch @@ -58624,6 +58627,16 @@ patches.suse/0005-xen-revert-Allow-watches-discard-events-before-queue.patch patches.suse/0006-xen-support-having-only-one-event-pending-per-watch.patch + + ################################################################# + # Extended APIC-ID patches to support large AWS instance types + ################################################################# + patches.suse/0001-x86-apic-Fix-x2apic-enablement-without-interrupt-rem.patch + patches.suse/0002-x86-msi-Only-use-high-bits-of-MSI-address-for-DMAR-u.patch + patches.suse/0003-x86-ioapic-Handle-Extended-Destination-ID-field-in-R.patch + patches.suse/0004-x86-apic-Support-15-bits-of-APIC-ID-in-IOAPIC-MSI-wh.patch + patches.suse/0005-x86-kvm-Add-KVM_FEATURE_MSI_EXT_DEST_ID.patch + ######################################################## # kABI consistency patches ######################################################## @@ -58744,6 +58757,7 @@ patches.kabi/b53_kabi.patch patches.kabi/kABI-ath10k-move-a-new-structure-member-to-the-end.patch patches.kabi/snd-hda-codec-generic-kabi-workaround.patch + patches.kabi/kABI-Fix-kABI-for-extended-APIC-ID-support.patch ######################################################## # You'd better have a good reason for adding a patch