From e9791f4e3db8ffe75517a34b357816402f7ff8b5 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Mar 19 2024 10:37:20 +0000 Subject: drm/amd/display: For prefetch mode > 0, extend prefetch if possible (git-fixes). --- diff --git a/patches.suse/drm-amd-display-For-prefetch-mode-0-extend-prefetch-.patch b/patches.suse/drm-amd-display-For-prefetch-mode-0-extend-prefetch-.patch new file mode 100644 index 0000000..39ab70e --- /dev/null +++ b/patches.suse/drm-amd-display-For-prefetch-mode-0-extend-prefetch-.patch @@ -0,0 +1,124 @@ +From dd4e4bb28843393065eed279e869fac248d03f0f Mon Sep 17 00:00:00 2001 +From: Alvin Lee +Date: Wed, 6 Dec 2023 14:52:31 -0500 +Subject: [PATCH] drm/amd/display: For prefetch mode > 0, extend prefetch if possible +Git-commit: dd4e4bb28843393065eed279e869fac248d03f0f +Patch-mainline: v6.8-rc1 +References: git-fixes + +[Description] +For mode programming we want to extend the prefetch as much as possible +(up to oto, or as long as we can for equ) if we're not already applying +the 60us prefetch requirement. This is to avoid intermittent underflow +issues during prefetch. + +The prefetch extension is applied under the following scenarios: +1. We're in prefetch mode 1 (i.e. we don't support MCLK switch in blank) +2. We're using subvp or drr methods of p-state switch, in which case we + we don't care if prefetch takes up more of the blanking time + +Mode programming typically chooses the smallest prefetch time possible +(i.e. highest bandwidth during prefetch) presumably to create margin between +p-states / c-states that happen in vblank and prefetch. Therefore we only +apply this prefetch extension when p-state in vblank is not required (UCLK +p-states take up the most vblank time). + +Reviewed-by: Jun Lei +Acked-by: Aurabindo Pillai +Signed-off-by: Alvin Lee +Signed-off-by: Alex Deucher +Acked-by: Takashi Iwai + +--- + .../dc/dml/dcn32/display_mode_vba_32.c | 3 ++ + .../dc/dml/dcn32/display_mode_vba_util_32.c | 33 +++++++++++++++---- + .../dc/dml/dcn32/display_mode_vba_util_32.h | 1 + + 3 files changed, 31 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +index cbdfb762c10c..6c84b0fa40f4 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +@@ -813,6 +813,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman + (v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ || + v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ? + mode_lib->vba.ip.min_prefetch_in_strobe_us : 0, ++ mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] > 0 || mode_lib->vba.DRAMClockChangeRequirementFinal == false, ++ + /* Output */ + &v->DSTXAfterScaler[k], + &v->DSTYAfterScaler[k], +@@ -3317,6 +3319,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l + v->SwathHeightCThisState[k], v->TWait, + (v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ? + mode_lib->vba.ip.min_prefetch_in_strobe_us : 0, ++ mode_lib->vba.PrefetchModePerState[i][j] > 0 || mode_lib->vba.DRAMClockChangeRequirementFinal == false, + + /* Output */ + &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k], +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +index d940dfa5ae43..80fccd4999a5 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +@@ -3423,6 +3423,7 @@ bool dml32_CalculatePrefetchSchedule( + unsigned int SwathHeightC, + double TWait, + double TPreReq, ++ bool ExtendPrefetchIfPossible, + /* Output */ + double *DSTXAfterScaler, + double *DSTYAfterScaler, +@@ -3892,12 +3893,32 @@ bool dml32_CalculatePrefetchSchedule( + /* Clamp to oto for bandwidth calculation */ + LinesForPrefetchBandwidth = dst_y_prefetch_oto; + } else { +- *DestinationLinesForPrefetch = dst_y_prefetch_equ; +- TimeForFetchingMetaPTE = Tvm_equ; +- TimeForFetchingRowInVBlank = Tr0_equ; +- *PrefetchBandwidth = prefetch_bw_equ; +- /* Clamp to equ for bandwidth calculation */ +- LinesForPrefetchBandwidth = dst_y_prefetch_equ; ++ /* For mode programming we want to extend the prefetch as much as possible ++ * (up to oto, or as long as we can for equ) if we're not already applying ++ * the 60us prefetch requirement. This is to avoid intermittent underflow ++ * issues during prefetch. ++ * ++ * The prefetch extension is applied under the following scenarios: ++ * 1. We're in prefetch mode > 0 (i.e. we don't support MCLK switch in blank) ++ * 2. We're using subvp or drr methods of p-state switch, in which case we ++ * we don't care if prefetch takes up more of the blanking time ++ * ++ * Mode programming typically chooses the smallest prefetch time possible ++ * (i.e. highest bandwidth during prefetch) presumably to create margin between ++ * p-states / c-states that happen in vblank and prefetch. Therefore we only ++ * apply this prefetch extension when p-state in vblank is not required (UCLK ++ * p-states take up the most vblank time). ++ */ ++ if (ExtendPrefetchIfPossible && TPreReq == 0 && VStartup < MaxVStartup) { ++ MyError = true; ++ } else { ++ *DestinationLinesForPrefetch = dst_y_prefetch_equ; ++ TimeForFetchingMetaPTE = Tvm_equ; ++ TimeForFetchingRowInVBlank = Tr0_equ; ++ *PrefetchBandwidth = prefetch_bw_equ; ++ /* Clamp to equ for bandwidth calculation */ ++ LinesForPrefetchBandwidth = dst_y_prefetch_equ; ++ } + } + + *DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0; +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h +index 592d174df6c6..5d34735df83d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h +@@ -747,6 +747,7 @@ bool dml32_CalculatePrefetchSchedule( + unsigned int SwathHeightC, + double TWait, + double TPreReq, ++ bool ExtendPrefetchIfPossible, + /* Output */ + double *DSTXAfterScaler, + double *DSTYAfterScaler, +-- +2.43.0 + diff --git a/series.conf b/series.conf index 4abf604..d46bd63 100644 --- a/series.conf +++ b/series.conf @@ -45216,6 +45216,7 @@ patches.suse/drm-radeon-check-the-alloc_workqueue-return-value-in.patch patches.suse/drm-radeon-dpm-fix-a-memleak-in-sumo_parse_power_tab.patch patches.suse/drm-radeon-trinity_dpm-fix-a-memleak-in-trinity_pars.patch + patches.suse/drm-amd-display-For-prefetch-mode-0-extend-prefetch-.patch patches.suse/drm-amdgpu-fix-ftrace-event-amdgpu_bo_move-always-mo.patch patches.suse/drm-amdgpu-debugfs-fix-error-code-when-smc-register-.patch patches.suse/drm-amd-pm-fix-a-double-free-in-si_dpm_init.patch